RU2840388C1 - Binary subtractor - Google Patents

Abstract

FIELD: digital computer engineering.

SUBSTANCE: binary subtractor contains eleven EXCLUSIVE OR elements, six elements AND, and two OR elements, connected to each other with implementation of subtraction of four-bit binary numbers, set by binary signals.

EFFECT: reduced circuit complexity of the device while maintaining the possibility of generating a binary code of the difference of two four-bit binary numbers.

1 cl, 1 dwg, 1 tbl

Description

The invention relates to computer technology and can be used for constructing automation equipment, functional units of control systems, etc.

A binary subtractor is known [1], which contains logical elements and forms a binary code of the difference of two three-digit binary numbers specified by binary signals, and a bit that determines its sign.

The reason that prevents the achievement of the technical result specified below when using the known binary subtractor is the limited functionality due to the fact that the processing of four-digit binary numbers is not allowed.

The closest device of the same purpose to the claimed invention in terms of its features is the binary subtractor [2], adopted as a prototype, which contains eleven elements of exclusive OR, six elements of AND and forms a binary code of the difference of two four-digit binary numbers specified by binary signals, and a bit determining its sign. In this case, the circuit depth of the prototype is 9.

The reason preventing the achievement of the technical result specified below when using the prototype is the complexity of the circuit, due to the fact that the Quine price of the prototype circuit is 46.

The technical result of the invention is a simplification of the binary subtractor circuit by reducing its Quine price while maintaining the functional capabilities of the prototype and a circuit depth no greater than that of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in a binary subtractor containing eleven exclusive OR elements and six AND elements, the k -th ( ), ( )-th inputs and the first output of the binary subtractor, the first and second inputs of the m -th ( ) element and are connected respectively to the first, second inputs of the k -th element of exclusive OR and the first input of the first element of AND, the output and the first input of the m -th element of exclusive OR, the peculiarity is that two OR elements are additionally introduced into it, the first, second inputs of the fifth element of exclusive OR, the first, second inputs and the output of the i -th ( ) OR elements are connected respectively to the outputs of the ninth, third, first, second inputs ( )-th and the first entrance ( )-th elements exclusive OR, first input ( )-th and exit ( )-th elements exclusive OR, the second input of the sixth and the output ( )-th AND elements are connected respectively to the output ( )-th AND element and the second input of the i -th OR element, the output of the fifth AND element and the second input ( )-th element of the exclusive OR, the first input of the eleventh element of the exclusive OR is connected to the output of the sixth element of the AND, and the second inputs of the sixth, eleventh and the output of the seventh elements of the exclusive OR are connected, respectively, to the outputs of the eighth, tenth elements of the exclusive OR and the second output of the binary subtractor, the third, fourth and fifth outputs of which are connected, respectively, to the outputs of the fifth, sixth and eleventh elements of the exclusive OR.

The drawing shows the circuit diagram of the proposed binary subtractor.

The binary subtractor contains the elements exclusive OR 1 ₁ ,…,1 ₁₁ , the elements AND 2 ₁ ,…,2 ₆ and the elements OR 3 ₁ , 3 ₂ , where the first input of the element is 1 ₁₁ , the first input and output of the element are 1 _m ( ) are connected respectively to the output of element 2 ₆ , the second and first inputs of element 2 _m , the first, second inputs of element 1 ₅ , the first, second inputs and output of element 3 _i ( ) are connected respectively to the outputs of elements 1 ₉ , 1 ₃ , the first, second inputs of element 1 _{i +6} and the first input of element 1 _{i +8} , the first input of element 1 _{i +6} and the output of element 1 _{2 × i ,} the second input of element 2 ₆ and the output of elements 2 _{2 × i} are connected respectively to the output of element 2 _{2 × i -1} and the second input of element 3 _i , the output of element 2 ₅ and the second input of element 1 _{i +8} , and the second inputs of elements 1 ₆ , 1 ₁₁ and the outputs of elements 1 ₁ , 1 ₇ , 1 ₅ , 1 ₆ , 1 ₁₁ are connected respectively to the outputs of elements 1 ₈ , 1 ₁₀ and the first, second, third, fourth, fifth outputs of the binary subtractor, the k -th ( ) And ( )-th inputs of which are connected respectively to the first and second inputs of element 1 _k .

The proposed binary subtractor operates as follows. Binary signals are fed to its first, sixth, third, eighth and fifth, second, seventh, fourth inputs, respectively. And , which specify the four-digit binary numbers to be processed , , and And define the values of the senior and junior digits respectively. Since the sets 00 and 11 of signal values ( ), are equivalent for elements 1 _k , 2 _k , it is sufficient to consider the operation of the proposed subtractor for the following sets of values of these signals: 00, 01, 10. The table below shows the values of the output signals of the proposed subtractor, obtained taking into account the operation of its elements for all possible combinations of the specified sets.

00 00 00 00 00000 01 01 10 00 10110 00 00 00 01 11111 01 01 10 01 10101 00 00 00 10 00001 01 01 10 10 10111 00 00 01 00 11110 01 10 00 00 11100 00 00 01 01 11101 01 10 00 01 11011 00 00 01 10 11111 01 10 00 10 11101 00 00 10 00 00010 01 10 01 00 11010 00 00 10 01 00001 01 10 01 01 11001 00 00 10 10 00011 01 10 01 10 11011 00 01 00 00 11100 01 10 10 00 11110 00 01 00 01 11011 01 10 10 01 11101 00 01 00 10 11101 01 10 10 10 11111 00 01 01 00 11010 10 00 00 00 01000 00 01 01 01 11001 10 00 00 01 00111 00 01 01 10 11011 10 00 00 10 01001 00 01 10 00 11110 10 00 01 00 00110 00 01 10 01 11101 10 00 01 01 00101 00 01 10 10 11111 10 00 01 10 00111 00 10 00 00 00100 10 00 10 00 01010 00 10 00 01 00011 10 00 10 01 01001 00 10 00 10 00101 10 00 10 10 01011 00 10 01 00 00010 10 01 00 00 00100 00 10 01 01 00001 10 01 00 01 00011 00 10 01 10 00011 10 01 00 10 00101 00 10 10 00 00110 10 01 01 00 00010 00 10 10 01 00101 10 01 01 01 00001 00 10 10 10 00111 10 01 01 10 00011 01 00 00 00 11000 10 01 10 00 00110 01 00 00 01 10111 10 01 10 01 00101 01 00 00 10 11001 10 01 10 10 00111 01 00 01 00 10110 10 10 00 00 01100 01 00 01 01 10101 10 10 00 01 01011 01 00 01 10 10111 10 10 00 10 01101 01 00 10 00 11010 10 10 01 00 01010 01 00 10 01 11001 10 10 01 01 01001 01 00 10 10 11011 10 10 01 10 01011 01 01 00 00 10100 10 10 10 00 01110 01 01 00 01 10011 10 10 10 01 01101 01 01 00 10 10101 10 10 10 10 01111 01 01 01 00 10010 01 01 01 01 10001 01 01 01 10 10011

According to the table presented we have , Where – a four-digit binary number specified by binary signals ( And determine the values of the senior and junior digits, respectively), and if the number D is positive or , That , if negative, then and it is presented in additional code.

The above information allows us to conclude that the proposed binary subtractor has a circuit depth equal to 9 and forms a binary code of the difference of two four-digit binary numbers specified by binary signals and a bit determining its sign. At the same time, the circuit of the proposed binary subtractor is simpler than that of the prototype, since its Quine price is 38.

Sources of information:

1. Russian Federation Patent 2629453, class G06F7/50, 2017.

2. Russian Federation Patent 2789722, class G06F7/50, 2023.

Claims (1)

A binary subtractor containing eleven exclusive OR elements and six AND elements, with the k -th ( ), ( )-th inputs and the first output of the binary subtractor, the first and second inputs of the m -th ( ) element and are connected respectively to the first, second inputs of the k -th exclusive OR element and the first input of the first AND element, the output and the first input of the m -th exclusive OR element, characterized in that two OR elements are additionally introduced into it, the first, second inputs of the fifth exclusive OR element, the first, second inputs and output of the i -th ( ) OR elements are connected respectively to the outputs of the ninth, third, first, second inputs ( )-th and the first entrance ( )-th elements exclusive OR, first input ( )-th and exit ( )-th elements exclusive OR, the second input of the sixth and the output ( )-th AND elements are connected respectively to the output ( )-th AND element and the second input of the i -th OR element, the output of the fifth AND element and the second input ( )-th element of the exclusive OR, the first input of the eleventh element of the exclusive OR is connected to the output of the sixth element of the AND, and the second inputs of the sixth, eleventh and the output of the seventh elements of the exclusive OR are connected, respectively, to the outputs of the eighth, tenth elements of the exclusive OR and the second output of the binary subtractor, the third, fourth and fifth outputs of which are connected, respectively, to the outputs of the fifth, sixth and eleventh elements of the exclusive OR.