RU2843505C1 - Binary number selector - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and specifically to binary number selectors, and can be used as an information preprocessing means. Binary number selector includes 10×n 2AND-NOT elements, which are grouped by ten elements into n groups.

EFFECT: simplification of the selector circuit due to reduction of its Quine price and provision for homogeneity of the hardware composition while preserving functional capabilities.

1 cl, 1 dwg, 1 tbl

Description

The invention relates to computer technology and can be used for constructing automation equipment, functional units of control systems, etc.

A binary number selector is known [1], which contains logical elements and performs the selection of the smaller of two n -bit binary numbers specified by binary signals.

The reason preventing the achievement of the technical result specified below when using the known binary number selector includes limited functional capabilities and heterogeneity of the hardware composition, due to the fact that the selection of the larger of the mentioned binary numbers is not performed, and the named analogue contains elements of two types.

The closest device of the same purpose to the claimed invention in terms of its set of features is the binary number selector [2], which has the following characteristics: inputs, outputs and performs the selection of the larger and smaller of two n -bit binary numbers specified by binary signals.

The reason preventing the achievement of the technical result specified below when using the prototype is the complexity of the circuit, due to the fact that the Quine price of the prototype circuit is equal to , and it contains elements of four types (Inhibit elements, 2OR elements, opening and closing keys).

The technical result of the invention is the simplification of the binary number selector circuit by reducing its cost according to Quine and ensuring the homogeneity of the hardware composition while maintaining the functional capabilities of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in the binary number selector, having inputs and outputs, the peculiarity is that it is entered into 2NAND elements, which are grouped into n groups of ten elements, with the j -th ( ) group outputs i -th ( ), ( )-th and the first, second inputs of the tenth 2AND-NOT elements are connected respectively to the first, second inputs ( )-th and outputs of the first, second elements of 2AND-NOT, and the first, second inputs of the k -th ( ) and the second entrance ( )-th, exit ( )-th elements of 2AND-NOT are connected respectively to the first inputs ( )-th, ( )-th and exit ( )-th, the second entrance ( )-th 2AND-NOT elements, output ( )-th element of the 2AND-NOT of the previous group and the second input of the k -th element of the 2AND-NOT of the first group are connected respectively to the second input of the k -th element of the 2AND-NOT of the next group and the unit potential bus, and the first inputs of the sixth, third and outputs of the tenth, ninth elements of the 2AND-NOT of the j -th group are connected respectively to the j -th, ( )-th input and j -th, ( )-th outputs of the binary number selector.

The figure shows a schematic diagram of the proposed binary number selector.

The binary number selector contains 2NAND elements 1 ₁₁ ,…,1 ₁₀₁ ,…,1 _{1 n} ,…,1 _{10 n} , which are grouped into n groups such that the j -th ( ) the group contains elements 1 _{1 j} ,…,1 _{10 j} , and the outputs of elements 1 _ij ( ), 1 _{( i +3) j} and the first, second inputs of element 1 _{10 j} are connected respectively to the first, second inputs of element 1 _{( i +6) j} and the outputs of elements 1 _{1 j} , 1 _{2 j} , the first, second inputs of element 1 _kj ( ) and the second input of element 1 _{( k +3) j} , the output of element 1 _{( k +6) j} are connected respectively to the first inputs of elements 1 _{(3 × k ) j} , 1 _{( k +3) j} and the output of element 1 _{(3- k ) j} , the second input of element 1 _{(9-3 × k ) j} , the output of element 1 _{( k +6) m} ( ) and the second input of element 1 _{k 1} are connected respectively to the second input of element 1 _{k ( m +1)} and the unit potential bus, and the first inputs of elements 1 _{6 j} , 1 _{3 j} and the outputs of elements 1 _{10 j} , 1 _{9 j} are connected respectively to the j -th, ( )-th input and j -th, ( )-th outputs of the binary number selector.

The proposed binary number selector operates as follows. On its first,…, n -th and ( )-th,…, ( )-th inputs are supplied with arbitrary binary signals, respectively And , which specify the n -bit binary numbers to be processed , ( , And , determine the values of the senior and junior digits, respectively). Then the signals on the j -th ( ) And ( )-th outputs of the proposed selector will be determined by the expressions

And , (1)

in which

;

.

The table below shows the output signal values. , of the proposed selector, obtained from expressions (1) for all possible sets of signal values , based on the values of its internal signals , , for example, when .

00 00 11 11 11 00 00 00 01 11 11 01 01 00 00 10 11 01 01 10 00 00 11 11 01 01 11 00 01 00 11 11 10 01 00 01 01 11 11 11 01 01 01 10 11 01 01 10 01 01 11 11 01 01 11 01 10 00 11 10 10 10 00 10 01 11 10 10 10 01 10 10 11 11 11 10 10 10 11 11 11 01 11 10 11 00 11 10 10 11 00 11 01 11 10 10 11 01 11 10 11 11 10 11 10 11 11 11 11 11 11 11

According to the presented table and taking into account the regular nature of the increase in the bit depth of the proposed selector, we have , , Where And there are n -bit binary numbers given by binary signals ( , And , determine the values of the senior and junior digits, respectively).

The above information allows us to conclude that the proposed binary number selector performs the selection of the larger and smaller of two n -bit binary numbers specified by binary signals, and that the circuit of the proposed binary number selector is simpler than that of the prototype, since it has a uniform hardware composition, and its Quine price is equal to .

List of references

1. Russian Federation Patent 2300130, class G06F7/02, 2007.

2. Russian Federation Patent 2365975, class G06F7/06, 2009.

Claims (1)

A binary number selector that has inputs and outputs, characterized in that they are entered into it 2NAND elements, which are grouped into n groups of ten elements, with the j -th ( ) group outputs i -th ( ), ( )-th and the first, second inputs of the tenth 2AND-NOT elements are connected respectively to the first, second inputs ( )-th and outputs of the first, second elements of 2AND-NOT, and the first, second inputs of the k -th ( ) and the second entrance ( )-th, exit ( )-th elements of 2AND-NOT are connected respectively to the first inputs ( )-th, ( )-th and exit ( )-th, the second entrance ( )-th 2AND-NOT elements, output ( )-th element of the 2AND-NOT of the previous group and the second input of the k -th element of the 2AND-NOT of the first group are connected respectively to the second input of the k -th element of the 2AND-NOT of the next group and the unit potential bus, and the first inputs of the sixth, third and outputs of the tenth, ninth elements of the 2AND-NOT of the j -th group are connected respectively to the j -th, ( )-th input and j -th, ( )-th outputs of the binary number selector.