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WO2018120364A1 - 一种显示面板的驱动装置及驱动方法 - Google Patents

一种显示面板的驱动装置及驱动方法 Download PDF

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Publication number
WO2018120364A1
WO2018120364A1 PCT/CN2017/073590 CN2017073590W WO2018120364A1 WO 2018120364 A1 WO2018120364 A1 WO 2018120364A1 CN 2017073590 W CN2017073590 W CN 2017073590W WO 2018120364 A1 WO2018120364 A1 WO 2018120364A1
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WO
WIPO (PCT)
Prior art keywords
signal
voltage signal
charging voltage
scan
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/073590
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English (en)
French (fr)
Inventor
吴宇
王磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/519,538 priority Critical patent/US20180301108A1/en
Publication of WO2018120364A1 publication Critical patent/WO2018120364A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a driving device and a driving method for a display panel.
  • the data line driving circuit disposed in the display panel needs to extract a large current to fill the parasitic capacitance of the data line first.
  • the charging voltage is pulled down, so that the pixels of the first few rows of the positive polarity are not fully charged, and the brightness of the positive pixel points of the rows is dark.
  • the parasitic capacitance on the data line is full, the charging voltage output from the data line driving circuit is not pulled down so that the brightness of each pixel point remains normal.
  • FIG. 1 is a schematic diagram showing changes in charging voltage with time in an embodiment of the prior art
  • FIG. 2 is a schematic diagram showing luminance distribution of each pixel in an embodiment of the prior art.
  • the charging voltage V is pulled down, so that the first row, the second row, and the The luminance of the positive pixel points in the three rows of pixels is dark; in the charging cycle of the fourth row and subsequent rows of pixels, the charging voltage V is normal, and the brightness of each pixel in the fourth row and subsequent rows of pixels remains normal.
  • the technical problem to be solved by the present invention is to provide a driving device and a driving method for a display panel, which can improve the problem of uneven lighting of pixels in the display panel.
  • the present invention adopts a technical solution to provide a driving device for a display panel, the driving device comprising: a timing control circuit, configured to receive a current data frame and parse the current data frame to obtain a frame to be output.
  • the data line drive circuit is configured to: first charge the first charge voltage signal under the control of the precharge signal Outputting to each data line to pre-charge the parasitic capacitance of each data line, and outputting a second charging voltage signal to each data line to charge each pixel line line by line under the control of the scanning clock pulse signal; scan driving circuit And receiving a scan clock pulse signal to generate a line scan drive signal corresponding to each scan line and outputting to the scan line; wherein, the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse of the first charging voltage signal The width is greater than or equal to the pulse width of the second charging voltage signal.
  • the timing control circuit is further configured to parse the current data frame to obtain a pixel voltage signal corresponding to each pixel point; the data line driving circuit is configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line to perform a line scan.
  • the drive signal charges each pixel point by row and applies a corresponding pixel voltage.
  • the timing control circuit is further configured to generate a data clock pulse signal according to the frame open signal; the data line driving circuit is further configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • a driving device for a display panel comprising: a timing control circuit, configured to receive a current data frame and parse the current data frame to obtain a to-be-outputted a frame on signal, which generates a precharge signal and a scan clock pulse signal according to the frame enable signal, wherein the precharge signal is output before the scan clock pulse signal; and the data line drive circuit is configured to: first charge the first charge voltage under the control of the precharge signal The signal is output to each data line to precharge the parasitic capacitance of each data line, and then the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the driving device further comprises a scan driving circuit; the scan driving circuit is configured to receive the scan clock pulse signal to generate a line scan driving signal corresponding to each scan line and output to the scan line.
  • the timing control circuit is further configured to parse the current data frame to obtain a pixel voltage signal corresponding to each pixel point; the data line driving circuit is configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line to perform a line scan.
  • the drive signal charges each pixel point by row and applies a corresponding pixel voltage.
  • the timing control circuit is further configured to generate a data clock pulse signal according to the frame open signal; the data line driving circuit is further configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • a driving method of a display panel is provided.
  • the driving method is based on a timing control circuit, a scan driving circuit, and a data line driving circuit.
  • the driving method includes: receiving, by the timing control circuit, a current data frame and parsing the current data frame to obtain a frame to be output.
  • a signal a pre-charge signal and a scan clock pulse signal are generated by the timing control circuit according to the frame turn-on signal, wherein the pre-charge signal is output before the scan clock pulse signal; and the first charge voltage is controlled by the data line drive circuit under the control of the pre-charge signal
  • the signal is output to each data line to precharge the parasitic capacitance of each data line, and then the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the method further comprises: receiving, by the scan driving circuit, the scan clock pulse signal to generate a line scan drive signal corresponding to each scan line and outputting to the scan line.
  • the method further includes: parsing the current data frame by the timing control circuit to obtain a pixel voltage signal corresponding to each pixel; and outputting the second charging voltage signal to each data line by the data line driving circuit to control the scanning clock signal
  • the step of charging each pixel point row by row includes: sequentially outputting the second charging voltage signal and the pixel voltage signal to each data line by the data line driving circuit to charge each pixel point row by row by the line scanning driving signal Apply the corresponding pixel voltage.
  • the method further includes: generating, by the timing control circuit, the data clock pulse signal according to the frame open signal; and sequentially outputting, by the data line driving circuit, the second charging voltage signal and the pixel voltage signal to each data line, comprising: driving by the data line The circuit sequentially outputs the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • the invention has the beneficial effects that the driving device and the driving method of the display panel of the present invention are different from the prior art, and the first charging voltage signal is output to each data line under the control of the pre-charging signal to parasitize the data lines. After the capacitor is precharged, the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the present invention can improve the problem of uneven brightness of pixel points in the display panel due to the parasitic capacitance of the data lines.
  • FIG. 1 is a schematic diagram showing changes in charging voltage with time in an embodiment of the prior art
  • FIG. 2 is a schematic diagram of luminance distribution of each pixel in an embodiment of the prior art
  • FIG. 3 is a schematic structural view of a driving device of a display panel according to a first embodiment of the present invention
  • Figure 4 is a signal waveform diagram of the driving device shown in Figure 1 during operation
  • FIG. 5 is a schematic structural view of a driving device of a display panel according to a second embodiment of the present invention.
  • FIG. 6 is a flow chart showing a driving method of a display panel according to a first embodiment of the present invention.
  • Fig. 7 is a flow chart showing a driving method of a display panel according to a second embodiment of the present invention.
  • the driving device 100 includes a timing control circuit 10 and a data line driving circuit 11.
  • the timing control circuit 10 is configured to receive the current data frame and parse the current data frame to obtain a frame enable signal to be output, and generate a precharge signal and a scan clock pulse signal according to the frame open signal, wherein the precharge signal is output before the scan clock pulse signal .
  • the precharge signal is output prior to the frame enable signal, and the frame open signal is output prior to the scan clock pulse signal.
  • the precharge signal is valid, the frame turn-on signal is valid, and finally the scan clock pulse signal is valid.
  • the frame open signal may be output prior to the precharge signal, and the precharge signal is output prior to the scan clock pulse signal.
  • the data line driving circuit 11 is configured to output a first charging voltage signal to each data line under the control of the precharge signal to precharge the parasitic capacitance of each data line, and then output the second charging voltage signal to each data line.
  • Each pixel is charged line by line under the control of the scan clock signal.
  • FIG. 4 is a signal waveform diagram of the driving device shown in FIG. 3 during operation.
  • ST1 is a precharge signal
  • STV1 is a frame open signal
  • CKV1 is a scan clock pulse signal
  • TP is a signal applied to the data line, which includes a first charging voltage signal V1 and a second charging voltage signal V2. .
  • the precharge signal ST1 is output prior to the frame enable signal STV1, wherein after the precharge signal ST1 is asserted, the signal TP applied to each data line is the first charge voltage signal V1.
  • the first charging voltage signal V1 applied to the data line does not charge each pixel point, and directly charges the parasitic capacitance on the data line. .
  • the first charging voltage signal V1 is a single-pulse signal of a positive voltage, and the pulse width thereof corresponds to the magnitude of the parasitic capacitance on the data line. Specifically, when the parasitic capacitance is large, the positive voltage in the first charging voltage signal V1 lasts for a long time; when the parasitic capacitance is small, the positive voltage in the first charging voltage signal V1 lasts for a short time.
  • each data line is the second charge voltage signal V2 to row each pixel point under the control of the scan clock pulse signal CKV1. Charge it. That is, in each pulse period of the scan clock signal CKV1, each data line is correspondingly applied with a second charging voltage signal V2 to charge a pixel of a certain row.
  • the pulse width of the first charging voltage signal V1 is equal to the pulse width of the second charging voltage signal V2, and the time interval of the first charging voltage signal V1 and the adjacent second charging voltage signal V2 is equal to two adjacent ones.
  • the first charging voltage signal V1 is a signal extending forward of the repeatedly arranged second charging voltage V2.
  • the pulse width of the first charging voltage signal V1 may also be greater than the pulse width of the second charging voltage signal V2, and the time interval of the first charging voltage signal V1 and the adjacent second charging voltage signal V2 may also be based on The actual situation is set as long as it satisfies the parasitic capacitance that the first charging voltage signal V1 can fill the respective data lines.
  • Fig. 5 is a schematic structural view of a driving device of a display panel according to a second embodiment of the present invention.
  • each pixel 210 includes a pixel FET T and a capacitor unit A (or a pixel electrode); the pixel FET T has a gate (G), a source (S) and a drain (D);
  • the unit A includes a parallel liquid crystal capacitor Clc (or a pixel capacitor, a liquid crystal pixel) and a storage capacitor Cs, one end of which is connected to the drain (D), and the other end is connected to a common voltage (Vcom); and is disposed in the pixel 210 of the same row.
  • the gate (G) of the pixel FET T is connected to the scan line Xm of the row.
  • the source (S) of the pixel FET T is connected to the corresponding data line Ym in the pixel 210 of the same column. .
  • the driving device 300 includes a timing control circuit 30, a data line driving circuit 31, and a scan driving circuit 32.
  • the data line driving circuit 31 is connected to the plurality of columns of data lines Ym
  • the scanning driving circuit 32 is connected to the plurality of rows of scanning lines Xm.
  • the timing control circuit 30 is configured to receive the current data frame and parse the current data frame to obtain a frame open signal to be output and a pixel voltage signal corresponding to each pixel point, and generate a precharge signal ST2, a scan clock pulse signal CKV2, and data according to the frame open signal. Clock pulse signal CKL2.
  • the data line driving circuit 31 is connected to the timing control circuit 30 for outputting the first charging voltage signal to each data line Ym under the control of the precharge signal ST2 to precharge the parasitic capacitance of each data line Ym, in the data.
  • the second charging voltage signal and the pixel voltage signal are sequentially output to the respective data lines Ym under the control of the clock pulse signal CKL2 to row-by-row the drains of the respective pixel points by the row scanning driving signal Gm.
  • D or the capacitor unit A performs charging and applies a corresponding pixel voltage, thereby realizing display of the current data frame.
  • the precharge signal ST2 is output prior to the scan clock pulse signal CKV2. That is, when the precharge signal ST2 is valid, the scan clock pulse signal CKV2 is still in an inactive state. At this time, the gate (G) of each pixel is in a closed state, and the first charging voltage signal is output to each data line Ym. The parasitic capacitance of each data line Ym is charged.
  • the scan drive circuit 32 applies the level of the row scan drive signal Gm on a certain row of scan lines Xm such that the gate of the pixel point 210 of the row (G) Turning on or off, when turned on, receiving the second charging voltage signal and the pixel voltage signal applied on the data line Ym of the row of pixel points 210 by the data line driving circuit 31 under the control of the data clock pulse signal CKL, so as to make a drain pole (D) or the charging and receiving of the capacitor unit A needs to display the pixel voltage corresponding to the gray scale, so that the pixel point 210 of the row is driven by the voltage on the scanning line Xm and the data line Ym to display an image image corresponding to the gray scale,
  • the scan line Xm is turned on line by line, the normal display of the picture is realized by writing the second charging voltage through the data line Ym and the pixel voltage corresponding to the gray scale.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and a pulse width of the first charging voltage signal is greater than or equal to a pulse width of the second charging voltage signal. That is, each data line is charged with the first charging voltage signal for a time longer than or equal to the time at which the same row of pixels is charged with the second charging voltage signal.
  • the voltage values of the first charging voltage signal and the second charging voltage signal are the same. In other embodiments, the magnitudes of the voltage values of the first charging voltage signal and the second charging voltage signal may also be different.
  • Fig. 6 is a flow chart showing a driving method of the display panel according to the first embodiment of the present invention, which is based on the driving device shown in Fig. 3. It should be noted that the method of the present invention is not limited to the sequence of processes shown in FIG. 6 if substantially the same result is obtained. As shown in FIG. 6, the method includes the steps of:
  • Step S101 The current data frame is received by the timing control circuit and the current data frame is parsed to obtain a frame open signal to be output.
  • Step S102 The pre-charge signal and the scan clock pulse signal are generated by the timing control circuit according to the frame turn-on signal.
  • step S102 the precharge signal is output prior to the scan clock pulse signal.
  • Step S103 The data line driving circuit outputs the first charging voltage signal to each data line under the control of the pre-charging signal to pre-charge the parasitic capacitance of each data line, and then outputs the second charging voltage signal to each data line.
  • Each pixel point is charged line by line under the control of the scan clock pulse signal.
  • Fig. 7 is a flowchart of a driving method of a display panel according to a second embodiment of the present invention, which is based on the driving device shown in Fig. 5. It should be noted that the method of the present invention is not limited to the sequence of processes shown in FIG. 7 if substantially the same result is obtained. As shown in Figure 7, the method includes the steps of:
  • Step S201 The current data frame is received by the timing control circuit and the current data frame is parsed to obtain a frame open signal to be output and a pixel voltage signal corresponding to each pixel.
  • Step S202 The pre-charge signal, the scan clock pulse signal and the data clock pulse signal are generated by the timing control circuit according to the frame turn-on signal.
  • step S202 the precharge signal is output prior to the scan clock pulse signal. Specifically, the precharge signal is output prior to the frame enable signal, and the frame open signal is output prior to the scan clock pulse signal.
  • Step S203 The data line driving circuit outputs a first charging voltage signal to each data line under the control of the precharge signal to precharge the parasitic capacitance of each data line.
  • step S203 when the precharge signal is output before the scan clock pulse signal, so that each data line of the display panel is applied with the first charging voltage signal, the pixel FET in the pixel cannot be turned on because the scan clock pulse signal is invalid. Therefore, the first charging voltage signal does not charge each pixel point and directly charges the parasitic capacitance on the data line.
  • Step S204 The scan clock signal is received by the scan driving circuit to generate a line scan drive signal corresponding to each scan line and output to the scan line.
  • Step S205 The data line driving circuit sequentially outputs the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal, so as to charge and apply corresponding pixels to each pixel row by row scanning driving signal.
  • the pixel voltage The pixel voltage.
  • step S205 the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • the invention has the beneficial effects that the driving device and the driving method of the display panel of the present invention are different from the prior art, and the first charging voltage signal is output to each data line under the control of the pre-charging signal before displaying the current data frame. Precharging the parasitic capacitance of each data line; in the process of displaying the current data frame, outputting the second charging voltage signal and the pixel voltage signal to each data line to row-by-row each pixel under the control of the scanning clock pulse signal The point is charged and the pixel voltage is applied.
  • the present invention can improve the problem of uneven brightness of pixel points in the display panel due to the parasitic capacitance of the data lines.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板的驱动装置（100）及驱动方法。该驱动装置（100）包括：时序控制电路（10），用于接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号（STV1），根据帧开启信号（STV1）产生预充电信号（ST1）和扫描时钟脉冲信号（CKV1），其中，预充电信号（ST1）先于扫描时钟脉冲信号（CKV1）输出；数据线驱动电路（11），用于在预充电信号（ST1）的控制下将第一充电电压信号（V1）输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号（V2）输出至各数据线以在扫描时钟脉冲信号（CKV1）的控制下逐行对各像素点进行充电。通过上述方式，能够改善由于数据线存在寄生电容而导致显示面板中像素点亮度不均的问题。

Description

一种显示面板的驱动装置及驱动方法
【技术领域】
本发明涉及液晶显示领域，特别涉及一种显示面板的驱动装置及驱动方法。
【背景技术】
在传统的显示面板的驱动过程中，需要逐行对显示面板中的像素点进行充电后显示图像。在实际充电的过程中，由于整条数据线有很大的寄生电容且存储的是负极性的电荷，设置于显示面板中的数据线驱动电路需要抽取大电流将数据线的寄生电容先行充满。此时，若数据线驱动电路的自身推力不足会导致充电电压下拉，使得前几行正极性的像素点充不饱，进而导致这些行的正极性的像素点的亮度偏暗。当数据线上的寄生电容被充满后，数据线驱动电路输出的充电电压不会被下拉从而使得各像素点的亮度保持正常。
请一并参考图1和图2，图1是现有技术一实施例中充电电压随时间变化的示意图，图2是现有技术一实施例中各像素点的亮度分布示意图。如图1和图2所示，在第一行、第二行和第三行像素点的充电周期t1、t2和t3，充电电压V被下拉，从而使得在第一行、第二行和第三行像素点中正极性的像素点的亮度偏暗；在第四行以及后续行像素点的充电周期，充电电压V正常，第四行以及后续行像素点中各像素点的亮度保持正常。
【发明内容】
本发明主要解决的技术问题是提供一种显示面板的驱动装置及驱动方法，能够改善显示面板中像素点亮暗不均的问题。为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示面板的驱动装置，该驱动装置包括：时序控制电路，用于接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号，根据帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，预充电信号先于扫描时钟脉冲信号输出；数据线驱动电路，用于在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电；扫描驱动电路，用于接收扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至扫描线；其中，第一充电电压信号和第二充电电压信号为脉冲信号，第一充电电压信号的脉冲宽度大于或等于第二充电电压信号的脉冲宽度。
其中，时序控制电路还用于解析当前数据帧以获得各像素点对应的像素电压信号；数据线驱动电路用于依次将第二充电电压信号和像素电压信号输出至各数据线，以通过行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
其中，时序控制电路还用于根据帧开启信号产生数据时钟脉冲信号；数据线驱动电路还用于在数据时钟脉冲信号的控制下依次将第二充电电压信号和像素电压信号输出至各数据线。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种显示面板的驱动装置，该驱动装置包括：时序控制电路，用于接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号，根据帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，预充电信号先于扫描时钟脉冲信号输出；数据线驱动电路，用于在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
其中，驱动装置进一步包括扫描驱动电路；扫描驱动电路用于接收扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至扫描线。
其中，时序控制电路还用于解析当前数据帧以获得各像素点对应的像素电压信号；数据线驱动电路用于依次将第二充电电压信号和像素电压信号输出至各数据线，以通过行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
其中，时序控制电路还用于根据帧开启信号产生数据时钟脉冲信号；数据线驱动电路还用于在数据时钟脉冲信号的控制下依次将第二充电电压信号和像素电压信号输出至各数据线。
其中，第一充电电压信号和第二充电电压信号为脉冲信号，第一充电电压信号的脉冲宽度大于或等于第二充电电压信号的脉冲宽度。
为解决上述技术问题，本发明采用的再一个技术方案是： 提供一种显示面板的驱动方法，驱动方法基于时序控制电路、扫描驱动电路和数据线驱动电路，该驱动方法包括：由时序控制电路接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号；由时序控制电路根据帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，预充电信号先于扫描时钟脉冲信号输出；由数据线驱动电路在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
其中，该方法进一步包括：由扫描驱动电路接收扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至扫描线。
其中，该方法进一步包括：由时序控制电路解析当前数据帧以获得各像素点对应的像素电压信号；由数据线驱动电路将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电的步骤包括：由数据线驱动电路依次将第二充电电压信号和像素电压信号输出至各数据线，以通过行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
其中，该方法进一步包括：由时序控制电路根据帧开启信号产生数据时钟脉冲信号；由数据线驱动电路依次将第二充电电压信号和像素电压信号输出至各数据线的步骤包括：由数据线驱动电路在数据时钟脉冲信号的控制下依次将第二充电电压信号和像素电压信号输出至各数据线。
其中，第一充电电压信号和第二充电电压信号为脉冲信号，第一充电电压信号的脉冲宽度大于或等于第二充电电压信号的脉冲宽度。
本发明的有益效果是：区别于现有技术，本发明的显示面板的驱动装置及驱动方法通过在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电。通过上述方式，本发明能够改善由于数据线存在寄生电容而导致显示面板中像素点亮度不均的问题。
【附图说明】
图1是现有技术一实施例中充电电压随时间变化的示意图；
图2是现有技术一实施例中各像素点的亮度分布示意图；
图3是本发明第一实施例的显示面板的驱动装置的结构示意图；
图4是图1所示的驱动装置在工作过程中的信号波形图；
图5是本发明第二实施例的显示面板的驱动装置的结构示意图；
图6是本发明第一实施例的显示面板的驱动方法的流程图；
图7是本发明第二实施例的显示面板的驱动方法的流程图。
【具体实施方式】
在说明书及权利要求书当中使用了某些词汇来指称特定的组件，所属领域中的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。下面结合附图和实施例对本发明进行详细说明。
图3是本发明第一实施例的显示面板的驱动装置的结构示意图。如图3所示，驱动装置100包括时序控制电路10和数据线驱动电路11。
时序控制电路10用于接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号，根据帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，预充电信号先于扫描时钟脉冲信号输出。
在本实施例中，预充电信号先于帧开启信号输出，帧开启信号先于扫描时钟脉冲信号输出。换个角度来说，预充电信号有效后，接着帧开启信号有效，最后扫描时钟脉冲信号有效。
在其它实施例中，也可以是帧开启信号先于预充电信号输出，预充电信号先于扫描时钟脉冲信号输出。
数据线驱动电路11用于在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
请一并参考图4，图4是图3所示的驱动装置在工作过程中的信号波形图。如图4所示，ST1为预充电信号，STV1为帧开启信号，CKV1为扫描时钟脉冲信号，TP为施加在数据线上的信号，其包括第一充电电压信号V1和第二充电电压信号V2。
预充电信号ST1先于帧开启信号STV1输出，其中，在预充电信号ST1有效后，施加在各数据线上的信号TP为第一充电电压信号V1。
此时，由于帧开启信号STV1和扫描时钟脉冲信号CKV1处于无效状态，施加在数据线上的第一充电电压信号V1不会对各像素点进行充电而会直接对数据线上的寄生电容进行充电。
其中，第一充电电压信号V1为正电压的单脉冲信号，其脉冲宽度与数据线上的寄生电容的大小相对应。具体来说，当寄生电容较大时，第一充电电压信号V1中正电压持续的时间较长；当寄生电容较小时，第一充电电压信号V1中正电压持续的时间较短。
接着，当帧开启信号STV1有效进而扫描时钟脉冲信号CKV1有效后，施加在各数据线上的信号TP为第二充电电压信号V2，以在扫描时钟脉冲信号CKV1的控制下逐行对各像素点进行充电。也就是说，在扫描时钟脉冲信号CKV1的每一脉冲周期，各数据线对应施加一个第二充电电压信号V2以对某一行的像素点进行充电。
在本实施例中，第一充电电压信号V1的脉冲宽度等于第二充电电压信号V2的脉冲宽度，第一充电电压信号V1和相邻的第二充电电压信号V2的时间间隔等于相邻的两个第二充电电压信号V2的时间间隔。换个角度来说，为了实现上的方便，第一充电电压信号V1为重复排列的第二充电电压V2向前延伸的一个信号。
在其它实施例中，第一充电电压信号V1的脉冲宽度也可以大于第二充电电压信号V2的脉冲宽度，第一充电电压信号V1和相邻的第二充电电压信号V2的时间间隔也可以根据实际情况进行设定，只要能满足第一充电电压信号V1能充满各数据线的寄生电容即可。
图5是本发明第二实施例的显示面板的驱动装置的结构示意图。如图5所示，显示面板200包括多行平行排列的扫描线Xm(m=1，2，…N)，多列平行排列的数据线Ym（m=1，2，…N），以及设于数据线Xm与扫描线Ym交叉处的多个像素点210。
其中，每个像素点210包括像素场效应管T及电容单元A(或称像素电极)；像素场效应管T具有栅极(G)、源极(S)和漏极(D)；该电容单元A包括并列的液晶电容Clc(或称像素电容、液晶像素)和存储电容Cs，其一端连接漏极(D)，另一端连接公共电压(Vcom)；且配置在同一行的像素点210中像素场效应管T的栅极(G)与该行的扫描线Xm连接，同理，配置在同一列的像素点210中像素场效应管T的源极(S)与对应的数据线Ym连接。
驱动装置300包括时序控制电路30、数据线驱动电路31和扫描驱动电路32。其中，数据线驱动电路31与多列数据线Ym连接，扫描驱动电路32与多行扫描线Xm连接。
时序控制电路30用于接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号和各像素点对应的像素电压信号，根据帧开启信号产生预充电信号ST2、扫描时钟脉冲信号CKV2和数据时钟脉冲信号CKL2。
扫描驱动电路32与时序控制电路30连接，用于接收扫描时钟脉冲信号CKV2以产生与各扫描线Xm对应的行扫描驱动信号Gm(m=1，2，…n)并输出至扫描线Xm。
数据线驱动电路31与时序控制电路30连接，用于在预充电信号ST2的控制下将第一充电电压信号输出至各数据线Ym以对各数据线Ym的寄生电容进行预充电后，在数据时钟脉冲信号CKL2的控制下依次将第二充电电压信号和像素电压信号输出至各数据线Ym，以通过行扫描驱动信号Gm逐行对各像素点的漏极 (D)或电容单元A进行充电和施加对应的像素电压，从而实现当前数据帧的显示。
在本实施例中，预充电信号ST2先于扫描时钟脉冲信号CKV2输出。也就是说，当预充电信号ST2有效时，扫描时钟脉冲信号CKV2还处于无效状态，此时，各像素点的栅极（G）处于关闭状态，第一充电电压信号输出至各数据线Ym以对各数据线Ym的寄生电容充电。
当扫描时钟脉冲信号CKV2以及数据时钟脉冲信号CKL2处于有效状态后，扫描驱动电路32施加在某一行扫描线Xm上的行扫描驱动信号Gm的高低使得该行的像素点210的栅极(G)打开或关闭，在打开时可接收数据线驱动电路31在数据时钟脉冲信号CKL控制下，在该行像素点210的数据线Ym上施加的第二充电电压信号和像素电压信号，以使得对漏极 (D)或电容单元A充电和接收需要显示灰阶对应的像素电压，进而使得该行的像素点210在扫描线Xm和数据线Ym上的电压驱动下实现显示对应灰阶的图像画面，依此逐行开启扫描线Xm时，通过数据线Ym写入第二充电电压和需要显示灰阶对应的像素电压来实现画面的正常显示。
在本实施例中，第一充电电压信号和第二充电电压信号为脉冲信号，第一充电电压信号的脉冲宽度大于或等于第二充电电压信号的脉冲宽度。也就是说，以第一充电电压信号对各数据线充电的时间长于或等于以第二充电电压信号对同一行像素点充电的时间。
在本实施例中，第一充电电压信号和第二充电电压信号的电压值大小相同。在其它实施例中，第一充电电压信号和第二充电电压信号的电压值大小也可以不相同。
图6是本发明第一实施例的显示面板的驱动方法的流程图，该方法基于图3所示的驱动装置。需注意的是，若有实质上相同的结果，本发明的方法并不以图6所示的流程顺序为限。如图6所示，该方法包括步骤：
步骤S101：由时序控制电路接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号。
步骤S102：由时序控制电路根据帧开启信号产生预充电信号和扫描时钟脉冲信号。
在步骤S102中，预充电信号先于扫描时钟脉冲信号输出。
步骤S103：由数据线驱动电路在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电后，将第二充电电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
图7是本发明第二实施例的显示面板的驱动方法的流程图，该方法基于图5所示的驱动装置。需注意的是，若有实质上相同的结果，本发明的方法并不以图7所示的流程顺序为限。如图7所示，该方法包括步骤：
步骤S201：由时序控制电路接收当前数据帧并解析当前数据帧以获得待输出的帧开启信号和各像素点对应的像素电压信号。
步骤S202：由时序控制电路根据帧开启信号产生预充电信号、扫描时钟脉冲信号和数据时钟脉冲信号。
在步骤S202中，预充电信号先于扫描时钟脉冲信号输出。具体来说，预充电信号先于帧开启信号输出，帧开启信号先于扫描时钟脉冲信号输出。
步骤S203：由数据线驱动电路在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电。
在步骤S203中，当预充电信号先于扫描时钟脉冲信号输出，以使得显示面板的各数据线被施加第一充电电压信号时，由于扫描时钟脉冲信号无效无法打开像素点中的像素场效应管，从而使得第一充电电压信号不会对各像素点进行充电而会直接对数据线上的寄生电容进行充电。
步骤S204：由扫描驱动电路接收扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至扫描线。
步骤S205：由数据线驱动电路在数据时钟脉冲信号的控制下依次将第二充电电压信号和像素电压信号输出至各数据线，以通过行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
在步骤S205中，第一充电电压信号和第二充电电压信号为脉冲信号，第一充电电压信号的脉冲宽度大于或等于第二充电电压信号的脉冲宽度。
本发明的有益效果是：区别于现有技术，本发明的显示面板的驱动装置及驱动方法通过在显示当前数据帧之前，在预充电信号的控制下将第一充电电压信号输出至各数据线以对各数据线的寄生电容进行预充电；在显示当前数据帧的过程中，将第二充电电压信号和像素电压信号输出至各数据线以在扫描时钟脉冲信号的控制下逐行对各像素点进行充电和施加像素电压。通过上述方式，本发明能够改善由于数据线存在寄生电容而导致显示面板中像素点亮度不均的问题。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种显示面板的驱动装置，其中，所述驱动装置包括：
    时序控制电路，用于接收当前数据帧并解析所述当前数据帧以获得待输出的帧开启信号，根据所述帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，所述预充电信号先于所述扫描时钟脉冲信号输出；
    数据线驱动电路，用于在所述预充电信号的控制下将第一充电电压信号输出至各数据线以对各所述数据线的寄生电容进行预充电后，将第二充电电压信号输出至各所述数据线以在所述扫描时钟脉冲信号的控制下逐行对各像素点进行充电；
    扫描驱动电路，用于接收所述扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至所述扫描线；
    其中，所述第一充电电压信号和所述第二充电电压信号为脉冲信号，所述第一充电电压信号的脉冲宽度大于或等于所述第二充电电压信号的脉冲宽度。
  2. 根据权利要求1所述的驱动装置，其中，所述时序控制电路还用于解析所述当前数据帧以获得各像素点对应的像素电压信号；
    所述数据线驱动电路用于依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线，以通过所述行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
  3. 根据权利要求2所述的驱动装置，其中，
    所述时序控制电路还用于根据所述帧开启信号产生数据时钟脉冲信号；
    所述数据线驱动电路还用于在所述数据时钟脉冲信号的控制下依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线。
  4. 一种显示面板的驱动装置，其中，所述驱动装置包括：
    时序控制电路，用于接收当前数据帧并解析所述当前数据帧以获得待输出的帧开启信号，根据所述帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，所述预充电信号先于所述扫描时钟脉冲信号输出；
    数据线驱动电路，用于在所述预充电信号的控制下将第一充电电压信号输出至各数据线以对各所述数据线的寄生电容进行预充电后，将第二充电电压信号输出至各所述数据线以在所述扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
  5. 根据权利要求4所述的驱动装置，其中，所述驱动装置进一步包括扫描驱动电路；
    所述扫描驱动电路用于接收所述扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至所述扫描线。
  6. 根据权利要求5所述的驱动装置，其中，所述时序控制电路还用于解析所述当前数据帧以获得各像素点对应的像素电压信号；
    所述数据线驱动电路用于依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线，以通过所述行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
  7. 根据权利要求6所述的驱动装置，其中，
    所述时序控制电路还用于根据所述帧开启信号产生数据时钟脉冲信号；
    所述数据线驱动电路还用于在所述数据时钟脉冲信号的控制下依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线。
  8. 根据权利要求4所述的驱动装置，其中，所述第一充电电压信号和所述第二充电电压信号为脉冲信号，所述第一充电电压信号的脉冲宽度大于或等于所述第二充电电压信号的脉冲宽度。
  9. 一种显示面板的驱动方法，其中，所述驱动方法基于显示面板的驱动装置，所述驱动装置包括时序控制电路和数据线驱动电路，所述驱动方法包括：
    由所述时序控制电路接收当前数据帧并解析所述当前数据帧以获得待输出的帧开启信号；
    由所述时序控制电路根据所述帧开启信号产生预充电信号和扫描时钟脉冲信号，其中，所述预充电信号先于所述扫描时钟脉冲信号输出；
    由所述数据线驱动电路在所述预充电信号的控制下将第一充电电压信号输出至各数据线以对各所述数据线的寄生电容进行预充电后，将第二充电电压信号输出至各所述数据线以在所述扫描时钟脉冲信号的控制下逐行对各像素点进行充电。
  10. 根据权利要求9所述的驱动方法，其中，所述驱动装置进一步包括扫描驱动电路，所述方法进一步包括：
    由所述扫描驱动电路接收所述扫描时钟脉冲信号以产生与各扫描线对应的行扫描驱动信号并输出至所述扫描线。
  11. 根据权利要求10所述的驱动方法，其中，所述方法进一步包括：
    由所述时序控制电路解析所述当前数据帧以获得各像素点对应的像素电压信号；
    由所述数据线驱动电路将第二充电电压信号输出至各所述数据线以在所述扫描时钟脉冲信号的控制下逐行对各像素点进行充电的步骤包括：
    由所述数据线驱动电路依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线，以通过所述行扫描驱动信号逐行对各像素点进行充电和施加对应的像素电压。
  12. 根据权利要求11所述的驱动方法，其中，所述方法进一步包括：
    由所述时序控制电路根据所述帧开启信号产生数据时钟脉冲信号；
    由所述数据线驱动电路依次将所述第二充电电压信号和所述像素电压信号输出至各所述数据线的步骤包括：
    由所述数据线驱动电路在所述数据时钟脉冲信号的控制下依次将第二充电电压信号和所述像素电压信号输出至各所述数据线。
  13. 根据权利要求9所述的驱动方法，其中，所述第一充电电压信号和所述第二充电电压信号为脉冲信号，所述第一充电电压信号的脉冲宽度大于或等于所述第二充电电压信号的脉冲宽度。
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