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WO2015021660A1 - 阵列基板及液晶显示装置 - Google Patents

阵列基板及液晶显示装置 Download PDF

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Publication number
WO2015021660A1
WO2015021660A1 PCT/CN2013/081717 CN2013081717W WO2015021660A1 WO 2015021660 A1 WO2015021660 A1 WO 2015021660A1 CN 2013081717 W CN2013081717 W CN 2013081717W WO 2015021660 A1 WO2015021660 A1 WO 2015021660A1
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WIPO (PCT)
Prior art keywords
switch
capacitor
reversed
pixel electrode
polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2013/081717
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English (en)
French (fr)
Inventor
董成才
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US14/006,104 priority Critical patent/US9891489B2/en
Priority to JP2016533771A priority patent/JP6360892B2/ja
Priority to KR1020167006006A priority patent/KR20160042014A/ko
Priority to RU2016104431A priority patent/RU2623184C1/ru
Priority to GB1600078.8A priority patent/GB2532621B/en
Publication of WO2015021660A1 publication Critical patent/WO2015021660A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the field of display device technologies, and in particular, to an array substrate and a liquid crystal display device.
  • the TFT-LCD includes an array substrate.
  • the array substrate is provided with a plurality of pixel regions respectively corresponding to R, G, and B, and scan lines, data lines, TFTs, storage capacitors, and liquid crystal capacitors for controlling the pixel regions.
  • the current common practice is to divide a pixel area into two partitions, primary partition A and sub-partition B.
  • the junction of the two partitions is opaque, and the voltages of the two zones are different under the same video signal (grayscale). , presenting different gamma (gamma) curves.
  • the ⁇ curve synthesized in the two regions is reduced from the positive viewing angle at a large viewing angle, which significantly improves the problem of the dominant role of the big view.
  • each pixel region includes a data line 110 , a first scan line 120 , a second scan line 130 , a first pixel electrode 140 , a second pixel electrode 150 , a first thin film transistor TFT_A, a second thin film transistor TFT_B, The third thin film transistor TFT_C.
  • the data line 110 is connected to the sources of the first thin film transistor TFT_A and the second thin film transistor TFT_B, the first pixel electrode 140 is connected to the drain of the first thin film transistor TFT_A, and the drain of the second pixel electrode 150 and the second thin film transistor TFT_B Connecting; the second scan line 130 is connected to the gate of the third thin film transistor TFT_C to provide a scan signal, the drain of the third thin film transistor TFT_C is connected to the second pixel electrode 550, and the source of the third thin film transistor TFT_C passes through the capacitor Cs1 and The common electrode is connected.
  • the driving of the TFT-LCD is a step-by-step scanning driving.
  • the signal Vgn on the first scanning line 120 is at a high potential (the signal Vgn+1 on the second scanning line 130 is low)
  • the first film The transistor TFT_A and the second thin film transistor TFT_B are turned on (the third thin film transistor TFT_C is turned off)
  • the data line 110 starts to the first storage capacitor Cst_A and the first liquid crystal capacitor Clc_A connected to the first pixel electrode 140, and the second pixel electrode 150
  • the connected second storage capacitor Cst_B and the second liquid crystal capacitor Clc_B are charged, and the pixel voltage (VA) of the first pixel electrode 140 and the pixel voltage (VB) of the second pixel electrode 150 are both charged to the voltage Vd on the data line 110.
  • the signal Vgn on the first scan line 120 is switched to a low potential, and the signal Vgn+1 on the second scan line 130 is switched to a high potential, the first thin film transistor TFT_A and the second thin film transistor
  • the third thin film transistor TFT_C is turned on, and the pixel voltage (VB) of the second pixel electrode 150 starts to leak to the common electrode through the first capacitor Cs1, thereby changing the pixel voltage (VB) of the second pixel electrode 150, thereby
  • the pixel voltage (VA) of the first pixel electrode 140 is different from the pixel voltage (VB) of the second pixel electrode 150, achieving a low color shift (Low) Color Shift) effect.
  • FIG. 2 is a schematic structural view of a capacitor Cs1 of FIG. 1 .
  • the capacitor Cs1 includes a first metal layer M1, an insulating layer SiNx, a semiconductor layer AS (a-si), and a second metal layer M2 in this order.
  • the first metal layer M1 and the second metal layer M2 correspond to the gate metal layer and the source metal layer of the array substrate, that is, when the gate metal layer is sputtered on the array substrate to form the metal gate of the thin film transistor,
  • the first metal layer M1 is etched on the gate metal layer
  • the second metal layer M2 is etched on the source metal layer when the source metal layer is sputtered on the array substrate to form a metal source of the thin film transistor
  • the layer SiNx corresponds to the gate insulating layer on the array substrate
  • the semiconductor layer AS corresponds to the TFT semiconductor layer on the array substrate, that is, when the semiconductor layer of the TFT is formed on the array substrate, the semiconductor layer required for forming the TFT by a photolithography process or the like
  • the semiconductor layer AS of the capacitor is also formed by a process such as photolithography.
  • M2 is generally connected to the pixel electrode voltage
  • M1 is generally connected to the common electrode trace.
  • FIG. 3 is a schematic diagram of a C-V (capacitance-voltage) curve of the capacitor Cs1.
  • the CV curve of the capacitor Cs1 is characterized in that the positive half cycle capacitance value is greater than the negative half cycle capacitance value, wherein when the pixel electrode voltage (such as VB, VA) is greater than the common electrode voltage (Vcom) is positive half cycle, the pixel The voltage of the electrode is less than the common electrode voltage (Vcom) and is a negative half cycle.
  • the positive half cycle and the negative half cycle alternately are a basic requirement when driving a TFT-LCD.
  • the CS08 low-color-off circuit has a positive or negative half-cycle asymmetry in the VB/VA value in practical applications. In addition to affecting the low color shift effect, it may also bring effects such as afterimages. Sticking) affects the quality of the panel display.
  • the technical problem to be solved by the present application is to provide an array substrate and a liquid crystal display device, which can compensate for the problem that the voltage ratios of the two partitions in the positive and negative half cycles are not equal, thereby improving the dominant role of the liquid crystal display device and eliminating the residual image. quality.
  • a technical solution adopted by the present invention is to provide an array substrate, the array substrate including a pixel unit, a common electrode trace, a data line, and a first intersecting with the data line and parallel to each other a scan line and a second scan line; the second scan line corresponding to one of the pixel units is the same scan line as the first scan line corresponding to the next next pixel unit; the pixel unit includes the first pixel An electrode, a second pixel electrode, a first switch, a second switch, and a third switch, wherein the pixel unit further includes a control circuit; the first switch and the second switch both include a control end, an input end, and an output end, The first scan line is connected to the control ends of the first switch and the second switch to provide scan signals to the first switch and the second switch, the data line and the first switch and the second switch Connected to the input end, the first pixel electrode is connected to the output end of the first switch, the second pixel electrode is connected to the output end of the
  • a second metal layer of the first capacitor and a first metal layer of the second capacitor are connected to a second end of the third switch, a first metal layer of the first capacitor and a second capacitor a second metal layer is connected to the common electrode trace;
  • a positive polarity when a scan signal is input to the second scan line to control the third switch to be turned on, a voltage of the second pixel electrode passes through The first capacitor and the second capacitor are reduced.
  • the negative polarity when the scan signal is input to the second scan line to control the third switch to be turned on, the voltage of the second pixel electrode passes.
  • the first capacitor and the second capacitor increase,
  • the capacitance value of the first capacitor when the polarity is reversed is greater than the capacitance value when the polarity is reversed, and the capacitance of the second capacitor when the polarity is reversed is smaller than the value of the capacitor when the polarity is reversed.
  • the sum of the capacitance value of the first capacitor and the capacitance value of the second capacitor when the polarity is reversed is equal to the sum of the capacitance values of the first capacitor and the second capacitor when the polarity is reversed, thereby causing
  • the capacitance value of the effective capacitance of the control circuit when the positive polarity is reversed is equal to the capacitance value of the effective capacitance when the negative polarity is inverted.
  • the first switch, the second switch, and the third switch are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the control terminal, the input end, and the output of the first switch
  • the terminals respectively correspond to the gate, the source and the drain of the first thin film transistor, and the control end, the input end and the output end of the second switch respectively correspond to the gate and the source of the second thin film transistor
  • the drain, the control end, the first end and the second end of the third switch respectively correspond to a gate, a source and a drain of the third thin film transistor.
  • the first switch, the second switch, and the third switch are respectively a first Darlington or a triode, a second Darlington or a triode, and a third Darlington or a triode, and the first switch
  • the control end, the input end and the output end respectively correspond to a base, a collector and an emitter of the first Darlington tube or the triode
  • the control end, the input end and the output end of the second switch respectively correspond to the a base, a collector and an emitter of the second Darlington tube or the transistor
  • the control end, the first end and the second end of the third switch respectively correspond to a base, a set of a third Darlington or a triode Electrode and emitter.
  • an array substrate including a pixel unit, a common electrode trace, a data line, and a line intersecting the data line and parallel to each other.
  • a scan line and a second scan line the pixel unit includes a first pixel electrode, a second pixel electrode, a first switch, a second switch, and a third switch, the pixel unit further comprising a control circuit;
  • the first switch And the second switch includes a control end, an input end and an output end, wherein the first scan line is connected to the control ends of the first switch and the second switch to provide the first switch and the second switch a scan signal, the data line being connected to the input ends of the first switch and the second switch, the first pixel electrode being connected to an output end of the first switch, the second pixel electrode and the second An output end of the switch is connected,
  • the third switch includes a control end, a first end and a second end, and the second scan line is connected to the control end of the third switch to
  • the control circuit includes a first capacitor and a second capacitor, and the first capacitor has the same structure as the second capacitor, and sequentially includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer. a second metal layer of a capacitor and a first metal layer of the second capacitor are connected to a second end of the third switch, a first metal layer of the first capacitor and a second metal of the second capacitor a layer is connected to the common electrode trace; when a positive polarity is reversed, when a scan signal is input to the second scan line to control the third switch to be turned on, a voltage of the second pixel electrode passes through the first a capacitor and the second capacitor are reduced, and when the scan signal is input to the second scan line to control the third switch to be turned on when the polarity is reversed, the voltage of the second pixel electrode passes through the The first capacitor and the second capacitor are increased, the capacitance of the first capacitor when the polarity is reversed is greater than the value of the capacitor when the polarity is reversed
  • the first switch, the second switch, and the third switch are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the control terminal, the input end, and the output of the first switch
  • the terminals respectively correspond to the gate, the source and the drain of the first thin film transistor, and the control end, the input end and the output end of the second switch respectively correspond to the gate and the source of the second thin film transistor
  • the drain, the control end, the first end and the second end of the third switch respectively correspond to a gate, a source and a drain of the third thin film transistor.
  • the first switch, the second switch, and the third switch are respectively a first Darlington or a triode, a second Darlington or a triode, and a third Darlington or a triode, and the first switch
  • the control end, the input end and the output end respectively correspond to a base, a collector and an emitter of the first Darlington tube or the triode
  • the control end, the input end and the output end of the second switch respectively correspond to the a base, a collector and an emitter of the second Darlington tube or the transistor
  • the control end, the first end and the second end of the third switch respectively correspond to a base, a set of a third Darlington or a triode Electrode and emitter.
  • the second scan line corresponding to one of the pixel units is the same scan line as the first scan line corresponding to the next next pixel unit.
  • a liquid crystal display device including a first substrate, a second substrate disposed opposite to each other, and being clamped on the first substrate and a liquid crystal layer between the second substrates; wherein the second substrate comprises: a pixel unit, a common electrode trace, a data line, and a first scan line and a second scan that intersect with the data line and are parallel to each other a pixel unit including a first pixel electrode, a second pixel electrode, a first switch, a second switch, and a third switch, the pixel unit further including a control circuit; the first switch and the second switch are both a control terminal, an input terminal, and an output terminal, wherein the first scan line is connected to the control ends of the first switch and the second switch to provide a scan signal to the first switch and the second switch, the data line Connected to the input ends of the first switch and the second switch, the first pixel electrode is connected to an output end of the first switch, and the output end
  • the control circuit includes a first capacitor and a second capacitor, and the first capacitor has the same structure as the second capacitor, and sequentially includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer. a second metal layer of a capacitor and a first metal layer of the second capacitor are connected to a second end of the third switch, a first metal layer of the first capacitor and a second metal of the second capacitor a layer is connected to the common electrode trace; when a positive polarity is reversed, when a scan signal is input to the second scan line to control the third switch to be turned on, a voltage of the second pixel electrode passes through the first a capacitor and the second capacitor are reduced, and when the scan signal is input to the second scan line to control the third switch to be turned on when the polarity is reversed, the voltage of the second pixel electrode passes through the The first capacitor and the second capacitor are increased, the capacitance of the first capacitor when the polarity is reversed is greater than the value of the capacitor when the polarity is reversed
  • the first switch, the second switch, and the third switch are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the control terminal, the input end, and the output of the first switch
  • the terminals respectively correspond to the gate, the source and the drain of the first thin film transistor, and the control end, the input end and the output end of the second switch respectively correspond to the gate and the source of the second thin film transistor
  • the drain, the control end, the first end and the second end of the third switch respectively correspond to a gate, a source and a drain of the third thin film transistor.
  • the first switch, the second switch, and the third switch are respectively a first Darlington or a triode, a second Darlington or a triode, and a third Darlington or a triode, and the first switch
  • the control end, the input end and the output end respectively correspond to a base, a collector and an emitter of the first Darlington tube or the triode
  • the control end, the input end and the output end of the second switch respectively correspond to the a base, a collector and an emitter of the second Darlington tube or the transistor
  • the control end, the first end and the second end of the third switch respectively correspond to a base, a set of a third Darlington or a triode Electrode and emitter.
  • the second scan line corresponding to one of the pixel units is the same scan line as the first scan line corresponding to the next next pixel unit.
  • the invention has the beneficial effects that the present invention is different from the prior art, and the present invention improves the ratio of the voltage of the second pixel electrode to the voltage of the first pixel electrode by adding a control circuit, thereby improving the large-view function of the liquid crystal display device. Partial, eliminating afterimages improves display quality.
  • FIG. 1 is a circuit diagram of a charge sharing circuit in an array substrate of a prior art TFT-LCD
  • FIG. 2 is a schematic structural view of a capacitor Cs1 of FIG. 1;
  • FIG. 3 is a schematic diagram of a C-V (capacitance-voltage) curve of the capacitor Cs1 of FIG. 1;
  • FIG. 4 is a schematic structural view of an embodiment of a liquid crystal display device of the present invention.
  • FIG. 5 is a pixel equivalent circuit diagram of the pixel unit of FIG. 4;
  • FIG. 6 is a schematic structural view of the control circuit of FIG. 5.
  • the present invention is directed to an array substrate, and a liquid crystal display device comprising the array substrate, comprising a plurality of pixel units.
  • FIG. 4 is a schematic structural view of an embodiment of a liquid crystal display device of the present invention.
  • the liquid crystal display device 40 includes a first substrate 410, a second substrate 420, and a liquid crystal layer (not shown) sandwiched between the first substrate and the second substrate.
  • the first substrate 410 is CF (Color). Filter, color filter) substrate, common electrode 430 is disposed on CF substrate 410, and second substrate 420 is TFT (Thin Film Transistor, thin film transistor) array substrate.
  • TFT Thin Film Transistor, thin film transistor
  • FIG. 5 is a pixel equivalent circuit diagram of the pixel unit of FIG. 4.
  • the TFT array substrate 420 of the liquid crystal display device 40 includes: a pixel unit 421 , a common electrode trace 440 , a data line 510 , and a data line 510 .
  • the first scan line 520 and the second scan line 530 intersect and are parallel to each other.
  • the pixel unit 421 includes a first pixel electrode 540, a second pixel electrode 550, a first switch 560, a second switch 570, a third switch 580, and a control circuit 590.
  • the first switch 560 and the second switch 570 each include a control end. , input and output.
  • the first scan line 520 is coupled to the control terminals of the first switch 560 and the second switch 570 to provide scan signals to the first switch 560 and the second switch 570; the input of the data line 510 and the first switch 560 and the second switch 570
  • the first pixel electrode 540 is connected to the output end of the first switch 560, and the first pixel electrode 540 is further connected to the first storage capacitor Cst_1 and the first liquid crystal capacitor C1c_1 connected in parallel, and the second pixel electrode 550 and the second
  • the output of the switch 570 is connected, and the second pixel electrode 550 is also connected to the second storage capacitor Cst_2 and the second liquid crystal capacitor C1c_2 connected in parallel.
  • the first liquid crystal capacitor C1c_1 is an equivalent capacitance formed by sandwiching liquid crystal molecules between the first pixel electrode 540 and the common electrode 430 of the first substrate 410
  • the second liquid crystal capacitor C1c_2 is the second pixel electrode 550 and the first substrate.
  • the first storage capacitor Cst_1 is composed of a first pixel electrode 540 and a common electrode trace 440 disposed on the second substrate 420, and the second storage capacitor Cst_2
  • the second pixel electrode 550 and the common electrode trace 440 disposed on the second substrate 420 are formed.
  • the third switch 580 includes a control end, a first end and a second end.
  • the control end of the third switch 580 is connected to the second scan line 530 to provide a scan signal to the third switch 580.
  • the first end of the third switch 580 is The second pixel electrode 550 is connected, and the second end of the third switch is connected to the control circuit 590.
  • the control circuit 590 includes a first capacitor Cs1 and a second capacitor Cs2.
  • the first capacitor Cs1 and the second capacitor Cs2 have the same structure, and each includes a first metal layer M1, an insulating layer SiNx, a semiconductor layer AS, and a second metal layer M2.
  • the first metal layer M2 of the first capacitor Cs1 and the first metal layer M1 of the second capacitor Cs2 are connected to the second end of the third switch 580, and the first metal layer M1 of the first capacitor Cs1 and the second capacitor Cs2 are second.
  • the metal layer M2 is connected to the common electrode traces 440 on the second substrate 420.
  • the first metal layer M1 and the second metal layer M2 correspond to the gate metal layer and the source metal layer of the array substrate, that is, when the gate metal layer is sputtered on the array substrate to form the metal gate of the thin film transistor,
  • the first metal layer M1 is etched on the gate metal layer
  • the second metal layer M2 is etched on the source metal layer when the source metal layer is sputtered on the array substrate to form a metal source of the thin film transistor
  • the layer SiNx corresponds to the gate insulating layer on the array substrate
  • the semiconductor layer AS corresponds to the TFT semiconductor layer on the array substrate, that is, when the semiconductor layer of the TFT is formed on the array substrate, the semiconductor layer required for forming the TFT by a photolithography process or the like
  • the semiconductor layer AS of the capacitor is also formed by a process such as photolithography.
  • the control circuit 590 acts on the second pixel electrode 550 when the third switch 580 is turned on to change the voltage of the second pixel electrode 550, and the control circuit 580 is inverted in the positive polarity.
  • the capacitance value of the effective capacitance at the time is equal to the capacitance value of the effective capacitance when the negative polarity is reversed, so that the voltage difference between the second pixel electrode 550 and the common electrode trace 440 is opposite to the first pixel when the positive polarity is reversed.
  • the first switch 560, the second switch 570, and the third switch 580 are all thin film transistors as an example.
  • the first switch 560, the second switch 570, and the third switch 580 are respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor.
  • the control terminal, the input end, and the output end of the first switch 560 respectively correspond to the first film.
  • the gate, the source and the drain of the transistor, the control terminal, the input terminal and the output terminal of the second switch 570 respectively correspond to the gate, the source and the drain of the second thin film transistor, and the control terminal of the third switch 580
  • One end and the second end respectively correspond to a gate, a drain and a source of the third thin film transistor.
  • the driving of the TFT-LCD is a step-by-step scan driving.
  • the signal Vgn on the first scan line 520 ie, the first scan line Gn
  • the second scan line 530 ie, the second
  • the signal Vgn+1 on the scan line Gn+1) is at a low level
  • the first thin film transistor 560, the second thin film transistor 570 are turned on
  • the third thin film transistor 580 is turned off, and the data line 510 starts the first storage for the parallel connection.
  • the capacitor Cst_1 and the first liquid crystal capacitor C1c_1, and the second storage capacitor Cst_2 and the second liquid crystal capacitor C1c_2 connected in parallel are charged, so that the first pixel electrode 540 and the second pixel electrode 550 obtain the same voltage.
  • the signal Vgn+1 on the second scan line 530 is at a high level, and the signal Vgn on the first scan line 520 is switched to a low level.
  • the first thin film transistor 560, The second thin film transistor 570 is turned off, and the third thin film transistor 580 is turned on.
  • the second pixel electrode 550 Since there is a voltage difference between the second pixel electrode 550 and the common electrode trace 440, the second pixel electrode 550 is common to the first capacitor Cs1 and the second capacitor Cs2. The electrode trace 440 is discharged, thereby changing the voltage of the second pixel electrode 550.
  • the third thin film transistor 580 when the positive polarity is reversed, that is, when the voltage of the second pixel electrode 550 is greater than the voltage between the common electrode traces 440, the first capacitance Cs1 is in the positive half cycle, and the second The capacitor Cs2 is in a negative half cycle, the capacitance value of the first capacitor Cs1 is greater than the capacitance value of the second capacitor Cs2, and the voltage of the second pixel electrode 550 is decreased by the first capacitor Cs1 and the second capacitor Cs2;
  • the first capacitor Cs1 is in the negative half cycle
  • the second capacitor Cs2 is in the positive half cycle
  • the capacitance value of the first capacitor Cs1 is smaller than the capacitance value of the second capacitor Cs2.
  • the voltage of the second pixel electrode 550 is increased by the first capacitor Cs1 and the second capacitor Cs2; since the structure and the capacitance of the first capacitor Cs1 and the second capacitor Cs2 are the same, the positive polarity inversion and the negative polarity inversion can be made
  • the sum of the capacitance values of the first capacitor Cs1 and the second capacitor Cs2 is kept constant, that is, the capacitance value of the effective capacitor when the positive polarity is reversed by the control circuit 590 is equal to the capacitance value of the effective capacitor when the negative polarity is reversed.
  • the ratio of the voltage difference between the second pixel electrode 550 and the common electrode trace 440 at the time of the polarity inversion to the voltage difference between the first pixel electrode 540 and the common electrode trace 440, and when the polarity is reversed The ratio of the voltage difference between the two pixel electrode 550 and the common electrode trace 440 is equal to the voltage difference between the first pixel electrode 540 and the common electrode trace 440.
  • the signal Vgn+1 on the second scan line 530 is at a low level, the third thin film transistor 580 is turned off, and the second pixel electrode 550 passes through the first capacitor Cs1 and the second capacitor Cs2.
  • the common electrode trace 440 stops discharging, and the voltage on the second pixel electrode 550 remains until the next frame is displayed.
  • the second scan line 530 corresponding to the pixel unit 421 is the same scan line as the first scan line corresponding to the next adjacent pixel unit.
  • the common electrode trace 440 on the second substrate 420 and the common electrode 430 on the first substrate 410 may not be directly connected, but the voltage is supplied through two different voltage sources, but Strictly ensure that the voltages of the two voltage sources are equal.
  • the voltage value supplied to the common electrode 430 and the common electrode trace 440 is preferably 5 V or more and 7 V or less; the voltage supplied to the first scan line 520 and the second scan line 530 is preferably 20 V or more and 30 V or less.
  • the first switch 560, the second switch 570, and the third switch 580 are all thin film transistors.
  • the first switch 560, the second switch 570, and the third switch 580 can also be triodes, Darlington.
  • the control terminal, the input terminal and the output terminal of the first switch 560 correspond to the base, collector and emitter of the first Darlington or transistor, respectively
  • the second switch 570 The control end, the input end and the output end respectively correspond to the base, collector and emitter of the second Darlington or the triode
  • the control end, the first end and the second end of the third switch 580 respectively correspond to the third The base, collector, and emitter of a Darlington or triode.
  • control circuit 590 is a first capacitor Cs1 and a second capacitor Cs2, and the control circuit 590 may also be two or more structures, connections, and capacitors with the first capacitor Cs1 and the second capacitor Cs2.
  • the capacitors of the same value are used to ensure that the capacitance values of the effective capacitances of the positive polarity and the negative polarity control circuit 590 are equal when the third switch is turned on, thereby forming other embodiments, which are not specifically limited.
  • FIG. 5 is a pixel equivalent circuit diagram of an embodiment of a pixel unit of an array substrate.
  • the pixel unit includes a first pixel electrode 540, a second pixel electrode 550, a first switch 560, a second switch 570, a third switch 580, and a control circuit 590.
  • the first switch 560 and the second switch 570 each include a control terminal. Input and output.
  • the specific implementation process is as described in the foregoing embodiment, and details are not described herein.
  • the ratio of the voltage of the second pixel electrode to the voltage of the first pixel electrode is made constant to improve the large-view role of the liquid crystal display device, and to eliminate image sticking and improve display quality.

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Abstract

一种阵列基板，其包括像素单元（421）、公共电极（440）、数据线（510）、与数据线（510）相交且互相平行的第一扫描线（520）和第二扫描线（530）；像素单元（421）包括第一像素电极（540）、第二像素电极（550）、第一开关（560）、第二开关（570）、第三开关（580）和控制电路（590）；第一扫描线（520）与第一开关（560）和第二开关（570）的控制端连接，以提供扫描信号；数据线（510）与第一开关（560）和第二开关（570）的输入端连接；第一像素电极（540）与第一开关（560）的输出端连接；第二像素电极（550）与第二开关（570）的输出端连接；第三开关（580）的控制端与第二扫描线（530）连接，以提供扫描信号；第三开关（580）的第一端与第二像素电极（550）连接，第三开关（580）的第二端与控制电路（590）连接。还提供一种液晶显示装置。通过增加一个控制电路（590），以改善液晶显示装置的大视角色偏，消除残影提高显示质量。

Description

阵列基板及液晶显示装置
【技术领域】
本申请涉及显示设备技术领域，特别是涉及一种阵列基板及液晶显示装置。
【背景技术】
TFT-LCD包括阵列基板，阵列基板上矩阵设置有多个分别对应R、G、B的像素区域，还设置有控制像素区域的扫描线、数据线、TFT以及存储电容和液晶电容等。
在目前的TFT-LCD中，特别是采用垂直取向（VA）液晶模式的大尺寸LCD中，普遍存在大视角色偏（Color Shift）的问题。
为改善此问题，目前的普遍做法是将一个像素区域分成主分区A和子分区B两个分区，两个分区的交界处不透光，在同一视频讯号(灰阶)下，使两区电压不同，呈现不同的γ（伽马）曲线。两区合成的γ曲线在大视角下与正视角差异减小，明显改善大视角色偏的问题。
图1是现有技术TFT-LCD的阵列基板中电荷共享08（Charging Sharing，CS）电路的示意图。请参阅图1，每个像素区域包括数据线110、第一扫描线120、第二扫描线130、第一像素电极140、第二像素电极150、第一薄膜晶体管TFT_A、第二薄膜晶体管TFT_B、第三薄膜晶体管TFT_C。数据线110与第一薄膜晶体管TFT_A和第二薄膜晶体管TFT_B的源极连接，第一像素电极140与第一薄膜晶体管TFT_A的漏极连接，第二像素电极150与第二薄膜晶体管TFT_B的漏极连接；第二扫描线130与第三薄膜晶体管TFT_C的栅极连接以提供扫描信号，第三薄膜晶体管TFT_C的漏极与第二像素电极550连接，第三薄膜晶体管TFT_C的源极通过电容Cs1与公共电极连接。
TFT-LCD的驱动为逐步行扫描驱动，扫描至第n行时，第一扫描线120上的信号Vgn为高电位（第二扫描线130上的信号Vgn+1为低电位），第一薄膜晶体管TFT_A和第二薄膜晶体管TFT_B打开（第三薄膜晶体管TFT_C关闭），数据线110开始对与第一像素电极140相连的第一存储电容Cst_A和第一液晶电容Clc_A、以及与第二像素电极150相连的第二存储电容Cst_B和第二液晶电容Clc_B充电，第一像素电极140的像素电压（VA）和第二像素电极150的像素电压（VB）均被充至数据线110上的电压Vd。当扫描至第n+1行时，第一扫描线120上的信号Vgn切换为低电位，第二扫描线130上的信号Vgn+1切换为高电位，第一薄膜晶体管TFT_A和第二薄膜晶体管TFT_B关闭，第三薄膜晶体管TFT_C打开，第二像素电极150的像素电压（VB）开始通过第一电容Cs1向公共电极漏电，从而使第二像素电极150的像素电压（VB）发生变化，进而使第一像素电极140的像素电压（VA）和第二像素电极150的像素电压（VB）不同，达到低色偏（Low Color Shift）效果。设VA和VB分别为A区和B区的像素电压，则其比值VB/VA=(Cst_B+Clc_B)/(Cst_B+Clc_B+2Cs1)是设计时一个极为关键的参数，其中，电容Cs1的作用极为关键，其值决定了VB/VA值的大小。
图2是图1中电容Cs1常用的一种结构示意图。请参阅图2，电容Cs1依次包括第一金属层M1、绝缘层SiNx、半导体层AS（a-si）和第二金属层M2。其中，第一金属层M1和第二金属层M2对应为阵列基板的栅极金属层和源极金属层，即在阵列基板上溅射栅极金属层以形成薄膜晶体管的金属栅极时，在该栅极金属层上蚀刻形成第一金属层M1，在阵列基板上溅射源极金属层以形成薄膜晶体管的金属源极时，在该源极金属层上蚀刻形成第二金属层M2；绝缘层SiNx对应为阵列基板上的栅极绝缘层；半导体层AS对应为阵列基板上的TFT半导体层，即在阵列基板上形成TFT的半导体层时，通过光刻等工艺形成TFT所需的半导体层时，也通过光刻等工艺形成电容的半导体层AS。在实际阵列基板中，M2一般与像素电极电压相连，M1一般与公共电极走线相连。
图3是电容Cs1的C-V（电容-电压）曲线示意图。请参阅图3，电容Cs1的C-V曲线图的特点是正半周的电容值大于负半周的电容值，其中，当像素电极的电压（如VB、VA）大于公共电极电压（Vcom）为正半周，像素电极的电压小于公共电极电压（Vcom）则为负半周。对每个像素区域而言，正半周和负半周交替是驱动TFT-LCD时的一个基本要求。理想情况，最好是正负半周的VB/VA保持一致，但是实际上一般会出现Cs1（正半周）>Cs1(负半周)或反过来的情况，则导致VB/VA值正半周较负半周小。
因此，CS08这种低色偏电路在实际应用中存在的VB/VA值正负半周不对称的问题，除了影响低色偏效果，还可能会带来诸如残影（Image Sticking）等影响面板显示品质的问题。
【发明内容】
本申请主要解决的技术问题是提供一种阵列基板及液晶显示装置，能够补偿正负半周两个分区的电压比值不等的问题，进而改善液晶显示装置的大视角色偏，消除残影提高显示质量。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，所述阵列基板包括像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线；所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接；所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
其中，所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
其中，所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，所述阵列基板包括像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接，所述控制电路与所述第三开关的第二端连接；其中，在正极性反转和负极性反转时，所述控制电路在所述第三开关导通时作用于所述第二像素电极，以改变所述第二像素电极的电压，且所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，以使得在正极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值，和在负极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值相等。
其中，所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
其中，所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
其中，所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
其中，一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线。
为解决上述技术问题，本发明采用的再一个技术方案是：提供一种液晶显示装置，所述液晶显示装置包括相对设置的第一基板、第二基板，以及夹持在所述第一基板和第二基板之间的液晶层；其特征在于，所述第二基板包括：像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接，所述控制电路与所述第三开关的第二端连接；其中，在正极性反转和负极性反转时，所述控制电路在所述第三开关导通时作用于所述第二像素电极，以改变所述第二像素电极的电压，且所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，以使得在正极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值，和在负极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值相等。
其中，所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
其中，所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
其中，所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
其中，一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线。
本发明的有益效果是：区别于现有技术的情况，本发明通过增加一个控制电路，使第二像素电极的电压与第一像素电极的电压的比值恒定，从而改善液晶显示装置的大视角色偏，消除残影提高显示质量。
【附图说明】
图1是现有技术TFT-LCD的阵列基板中电荷共享电路的电路示意图；
图2是图1中电容Cs1常用的一种结构示意图；
图3是图1中电容Cs1的C-V（电容-电压）曲线示意图；
图4是本发明液晶显示装置一实施方式的结构示意图；
图5是图4中像素单元的像素等效电路图；
图6是图5中控制电路的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细说明。
本发明旨在提供一种阵列基板，以及一种由该阵列基板构成的液晶显示装置，其包括多个像素单元。
请参阅图4，图4是本发明液晶显示装置一实施方式的结构示意图。液晶显示装置40包括相对设置的第一基板410、第二基板420、夹持在第一基板和第二基板之间的液晶层（图未示），其中，第一基板410为CF（Color Filter，彩色滤光片）基板，公共电极430设置于CF基板410，第二基板420为TFT（Thin Film Transistor，薄膜晶体管）阵列基板。
图5是图4中像素单元的像素等效电路图。请参阅图4和图5，以一个像素单元为例，在本实施例中，液晶显示装置40的TFT阵列基板420包括：像素单元421、公共电极走线440、数据线510、与数据线510相交且互相平行的第一扫描线520和第二扫描线530。
像素单元421包括第一像素电极540、第二像素电极550、第一开关560、第二开关570、第三开关580和控制电路590；其中，第一开关560与第二开关570均包括控制端、输入端和输出端。
第一扫描线520与第一开关560和第二开关570的控制端连接，以对第一开关560和第二开关570提供扫描信号；数据线510与第一开关560和第二开关570的输入端连接；第一像素电极540与第一开关560的输出端连接，且第一像素电极540还与并联连接的第一存储电容Cst_1和第一液晶电容C1c_1连接，第二像素电极550与第二开关570的输出端连接，且第二像素电极550还与并联连接的第二存储电容Cst_2和第二液晶电容C1c_2连接。其中，第一液晶电容C1c_1为第一像素电极540和第一基板410的公共电极430之间夹有液晶分子而构成的等效电容，第二液晶电容C1c_2为第二像素电极550和第一基板410的公共电极430之间夹有液晶分子而构成的等效电容；第一存储电容Cst_1由第一像素电极540和设置于第二基板420上的公共电极走线440构成，第二存储电容Cst_2由第二像素电极550和设置于第二基板420上的公共电极走线440构成。
第三开关580包括控制端、第一端和第二端，第三开关580的控制端与第二扫描线530连接，以对第三开关580提供扫描信号，第三开关580的第一端与第二像素电极550连接，第三开关的第二端与控制电路590连接。
请一并参阅图6，图6图5中控制电路的结构示意图。控制电路590包括第一电容Cs1和第二电容Cs2，第一电容Cs1与第二电容Cs2的结构相同，均依次包括第一金属层M1、绝缘层SiNx、半导体层AS以及第二金属层M2，第一电容Cs1的第二金属层M2和第二电容Cs2的第一金属层M1与第三开关580的第二端连接，第一电容Cs1的第一金属层M1和第二电容Cs2的第二金属层M2与第二基板420上的公共电极走线440连接。其中，第一金属层M1和第二金属层M2对应为阵列基板的栅极金属层和源极金属层，即在阵列基板上溅射栅极金属层以形成薄膜晶体管的金属栅极时，在该栅极金属层上蚀刻形成第一金属层M1，在阵列基板上溅射源极金属层以形成薄膜晶体管的金属源极时，在该源极金属层上蚀刻形成第二金属层M2；绝缘层SiNx对应为阵列基板上的栅极绝缘层；半导体层AS对应为阵列基板上的TFT半导体层，即在阵列基板上形成TFT的半导体层时，通过光刻等工艺形成TFT所需的半导体层时，也通过光刻等工艺形成电容的半导体层AS。
在正极性反转和负极性反转时，控制电路590在第三开关580导通时作用于第二像素电极550，以改变第二像素电极550的电压，且控制电路580在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，以使得在正极性反转时第二像素电极550和公共电极走线440之间的电压差与第一像素电极540和公共电极走线440之间的电压差的比值，和在负极性反转时第二像素电极550和公共电极走线440之间的电压差与第一像素电极540和公共电极走线440之间的电压差的比值相等。
请继续参阅图5，以第一开关560、第二开关570、第三开关580均为薄膜晶体管为例进行说明。第一开关560、第二开关570、第三开关580分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，第一开关560的控制端、输入端和输出端分别对应为第一薄膜晶体管的栅极、源极和漏极，第二开关570的控制端、输入端和输出端分别对应为第二薄膜晶体管的栅极、源极和漏极，第三开关580的控制端、第一端和第二端分别对应为第三薄膜晶体管的栅极、漏极和源极。
TFT-LCD的驱动为逐步扫描驱动，扫描至第n行时，第一扫描线520（即第一扫描线Gn）上的信号Vgn为高电平，此时第二扫描线530（即第二扫描线Gn+1）上的信号Vgn+1为低电平，第一薄膜晶体管560、第二薄膜晶体管570被打开，而第三薄膜晶体管580关闭，数据线510开始对并联连接的第一存储电容Cst_1和第一液晶电容C1c_1、以及并联连接的第二存储电容Cst_2和第二液晶电容C1c_2充电，从而使得第一像素电极540和第二像素电极550获得相同的电压。当扫描到n+1行时，第二扫描线530上的信号Vgn+1为高电平，第一扫描线520上的信号Vgn切换为低电平，此时，第一第薄膜晶体管560、第二薄膜晶体管570被关闭，第三薄膜晶体管580打开，由于第二像素电极550与公共电极走线440之间存在压差，第二像素电极550通过第一电容Cs1和第二电容Cs2向公共电极走线440放电，从而改变第二像素电极550的电压。
在第三薄膜晶体管580导通的情况下，在正极性反转时，即当第二像素电极550的电压大于公共电极走线440之间的电压时，第一电容Cs1处于正半周，第二电容Cs2处于负半周，第一电容Cs1的电容值大于第二电容Cs2电容值，第二像素电极550的电压通过第一电容Cs1和第二电容Cs2减小；在负极性反转时，即当第二像素电极550的电压小于公共电极走线440之间的电压时，第一电容Cs1处于负半周，第二电容Cs2处于正半周，第一电容Cs1的电容值小于第二电容Cs2电容值，第二像素电极550的电压通过第一电容Cs1和第二电容Cs2增加；由于第一电容Cs1和第二电容Cs2的结构和容值都相同，因此能够使得在正极性反转和负极性反转时，第一电容Cs1和第二电容Cs2的电容值之和保持恒定，即控制电路590在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，进而使在正极性反转时第二像素电极550和公共电极走线440之间的电压差与第一像素电极540和公共电极走线440之间的电压差的比值，和在负极性反转时第二像素电极550和公共电极走线440之间的电压差与第一像素电极540和公共电极走线440之间的电压差的比值相等。
当扫描到第n+2行时，第二扫描线530上的信号Vgn+1为低电平，第三薄膜晶体管580被关闭，第二像素电极550通过第一电容Cs1和第二电容Cs2向公共电极走线440停止放电，第二像素电极550上的电压保持到下一帧显示。此时，像素单元421所对应的第二扫描线530与相邻下一个像素单元所对应的第一扫描线为同一条扫描线。
值得注意的是，在本发明中，第二基板420上的公共电极走线440和第一基板410上的公共电极430也可以不直接相连，而是通过两个不同的电压源提供电压，但严格保证两个电压源的电压大小相等。其中，向公共电极430和公共电极走线440提供的电压值优选为大于等于5V小于等于7V；向第一扫描线520和第二扫描线530提供的电压优选为大于等于20V小于等于30V。
在本实施例中，第一开关560、第二开关570、第三开关580均为薄膜晶体管，同样地，第一开关560、第二开关570、第三开关580也可以为三极管、达林顿管或其它的晶体管代替以形成其它实施例，第一开关560的控制端、输入端和输出端分别对应为第一达林顿管或三极管的基极、集电极和发射极，第二开关570的控制端、输入端和输出端分别对应为第二达林顿管或三极管的基极、集电极和发射极，第三开关580的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
另外，在本实施例中，控制电路590为第一电容Cs1和第二电容Cs2，控制电路590也可以为两个或多个与第一电容Cs1和第二电容Cs2组成结构、连接方式、容值相同的电容以保证当第三开关导通时在正极性发转和负极性反控制电路590的有效电容的电容值相等，从而形成其他形式的实施例，本发明不作具体限定。
请继续参阅图5，图5是阵列基板的像素单元一实施方式的像素等效电路图。像素单元包括第一像素电极540、第二像素电极550、第一开关560、第二开关570、第三开关580和控制电路590；其中，第一开关560与第二开关570均包括控制端、输入端和输出端。具体实现过程如上述实施例所述，此处不赘述。
上述方案，通过增加一个控制电路，使第二像素电极的电压与第一像素电极的电压的比值恒定，以改善液晶显示装置的大视角色偏，消除残影提高显示质量。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板，其中，所述阵列基板包括像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；
    一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线；
    所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接；
    所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；
    在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
  3. 根据权利要求1所述的阵列基板，其中，
    所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
  4. 一种阵列基板，其中，所述阵列基板包括像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；
    所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接，所述控制电路与所述第三开关的第二端连接；
    其中，在正极性反转和负极性反转时，所述控制电路在所述第三开关导通时作用于所述第二像素电极，以改变所述第二像素电极的电压，且所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，以使得在正极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值，和在负极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值相等。
  5. 根据权利要求4所述的阵列基板，其中，
    所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；
    在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
  6. 根据权利要求4所述的阵列基板，其中，
    所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
  7. 根据权利要求4所述的阵列基板，其中，
    所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
  8. 根据权利要求4所述的阵列基板，其中，
    一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线。
  9. 一种液晶显示装置，其中，所述液晶显示装置包括相对设置的第一基板、第二基板，以及夹持在所述第一基板和第二基板之间的液晶层；其特征在于，所述第二基板包括：
    像素单元、公共电极走线、数据线、以及与所述数据线相交且互相平行的第一扫描线和第二扫描线；
    所述像素单元包括第一像素电极、第二像素电极、第一开关、第二开关和第三开关，所述像素单元还包括控制电路；所述第一开关与所述第二开关均包括控制端、输入端和输出端，所述第一扫描线与所述第一开关和第二开关的控制端连接，以对所述第一开关和第二开关提供扫描信号，所述数据线与所述第一开关和第二开关的输入端连接，所述第一像素电极与所述第一开关的输出端连接，所述第二像素电极与所述第二开关的输出端连接，所述第三开关包括控制端、第一端和第二端，所述第二扫描线与所述第三开关的控制端连接，以对所述第三开关提供扫描信号，所述第二像素电极与第三开关的第一端连接，所述控制电路与所述第三开关的第二端连接；
    其中，在正极性反转和负极性反转时，所述控制电路在所述第三开关导通时作用于所述第二像素电极，以改变所述第二像素电极的电压，且所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等，以使得在正极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值，和在负极性反转时所述第二像素电极和公共电极走线之间的电压差与所述第一像素电极和公共电极走线之间的电压差的比值相等。
  10. 根据权利要求9所述的液晶显示装置，其中，
    所述控制电路包括第一电容和第二电容，所述第一电容与第二电容的结构相同，均依次包括第一金属层、绝缘层、半导体层以及第二金属层，所述第一电容的第二金属层和所述第二电容的第一金属层与所述第三开关的第二端连接，所述第一电容的第一金属层和所述第二电容的第二金属层与所述公共电极走线连接；
    在正极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容减小，在负极性反转时，在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第二像素电极的电压通过所述第一电容和所述第二电容增加，所述第一电容在正极性反转时的电容值大于在负极性反转时的电容值，所述第二电容在正极性反转时的电容值小于在负极性反转时的电容值，以使得在正极性反转时所述第一电容的电容值与第二电容的电容值之和与在负极性反转时所述第一电容和第二电容的电容值之和相等，进而使得所述控制电路在正极性反转时的有效电容的电容值和在负极性反转时的有效电容的电容值相等。
  11. 根据权利要求9所述的液晶显示装置，其中，
    所述第一开关、第二开关以及第三开关均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一开关的控制端、输入端和输出端分别对应为所述第一薄膜晶体管的栅极、源极和漏极，所述第二开关的控制端、输入端和输出端分别对应为所述第二薄膜晶体管的栅极、源极和漏极，所述第三开关的控制端、第一端和第二端分别对应为所述第三薄膜晶体管的栅极、源极和漏极。
  12. 根据权利要求9所述的液晶显示装置，其中，
    所述第一开关、第二开关以及第三开关分别为第一达林顿管或三极管、第二达林顿管或三极管以及第三达林顿管或三极管，所述第一开关的控制端、输入端和输出端分别对应为所述第一达林顿管或三极管的基极、集电极和发射极，所述第二开关的控制端、输入端和输出端分别对应为所述第二达林顿管或三极管的基极、集电极和发射极，所述第三开关的控制端、第一端和第二端分别对应为第三达林顿管或三极管的基极、集电极和发射极。
  13. 根据权利要求9所述的液晶显示装置，其中，
    一个所述像素单元所对应的所述第二扫描线与相邻下一个像素单元所对应的第一扫描线为同一条扫描线。
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