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WO2015165124A1 - 用于窄边框液晶显示器的栅极驱动器 - Google Patents

用于窄边框液晶显示器的栅极驱动器 Download PDF

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Publication number
WO2015165124A1
WO2015165124A1 PCT/CN2014/076783 CN2014076783W WO2015165124A1 WO 2015165124 A1 WO2015165124 A1 WO 2015165124A1 CN 2014076783 W CN2014076783 W CN 2014076783W WO 2015165124 A1 WO2015165124 A1 WO 2015165124A1
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Prior art keywords
coupled
shift buffer
node
transistor
buffer unit
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PCT/CN2014/076783
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English (en)
French (fr)
Inventor
肖军城
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/373,872 priority Critical patent/US9501989B2/en
Publication of WO2015165124A1 publication Critical patent/WO2015165124A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of flat display, and more particularly to a gate driver for a narrow bezel liquid crystal display.
  • GOA Gate Driver On The Array circuit is a thin-film transistor liquid crystal display Array process in which a gate driver is fabricated on a thin film transistor array substrate to realize a progressive scan driving method.
  • the GOA circuit is mainly composed of a pull-up circuit and a pull-up control (Pull-up control). Circuit), transfer circuit, pull-down circuit, pull-down circuit (Pull-down) Holding circuit), and a rising circuit (Boost circuit) responsible for potential rise.
  • the pull-up circuit is mainly responsible for outputting the input clock signal (Clock) to the thin film transistor (thin film)
  • the gate of the transistor (TFT) serves as a driving signal for the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal (that is, the potential of the gate of the thin film transistor) to a low level after outputting the scan signal.
  • the pull-down holding circuit is responsible for keeping the scan signal and the signal of the pull-up circuit (that is, the signal applied to the Q point) in the off state (ie, the set negative potential), and usually two pull-down holding circuits alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • the traditional GOA circuit has the following shortcomings: (1) The number of TFTs and signal lines of the circuit is large, which is not conducive to the design of a narrow bezel display device or even a bezelless display device; (2) the number of more TFTs and signal lines It will inevitably increase the RC effect, which will make the circuit have higher energy consumption. The standard for low energy consumption is difficult to meet, and it cannot meet the design requirements of future green environmental protection.
  • the present invention provides a gate driver comprising: a plurality of shift buffer units, the plurality of shift buffer units being coupled in series, each shift buffer unit for using the first clock signal, The two clock signals and the drive signal pulses of the previous shift buffer unit of each of the shift buffer units output an output signal pulse at the output of each of the shift buffer units.
  • Each of the shifting buffer units includes: a pull-up circuit including a first transistor having a gate coupled to the first node, a source coupled to the first clock signal, and a drain coupled to the output terminal for According to the first clock signal, the output signal is provided by the output terminal;
  • the sub-transmission circuit includes a second transistor having a gate coupled to the first node, a source coupled to the first clock signal, and a drain
  • the driving signal terminal is configured to output a driving signal pulse by the driving signal terminal according to the first clock signal;
  • a pull-up control circuit includes a third transistor, and a gate thereof is coupled to each of the shift buffers An output signal end of the previous shift buffer unit of the unit, the source is coupled to the driving signal end of the previous shift buffer unit of each shift buffer unit, and the drain is coupled to the first node for
  • the driving signal pulse of the previous shift buffer unit of each shift buffer unit turns on the pull-up circuit;
  • a rising circuit is coupled between the first node and the output terminal for raising the first Potential
  • the first pull-down holding circuit includes: a fourth transistor having a gate coupled to the first clock signal, a source coupled to the first clock signal, and a drain coupled to the second node; a fifth transistor having a gate coupled to the driving signal terminal, a source coupled to the second node, a drain coupled to the second power supply voltage, and a sixth transistor having a gate coupled to each of the shifts a driving signal end of the buffering unit of the buffer unit, the source is coupled to the second node, the drain is coupled to the second power voltage, and the seventh transistor is coupled to the second clock signal Or the second node, the source is coupled to the first clock signal, and the drain is coupled to the second node; the eighth transistor has a gate coupled to the second node, and a source coupled to the output
  • the first drain voltage is coupled to the first power supply voltage
  • the ninth transistor has a gate coupled to the second node, a source coupled to the first node, and a drain coupled to the first power supply voltage
  • a tenth transistor having a
  • the second pull-down holding circuit comprises: An eleventh transistor having a gate coupled to a driving signal end of the next two shift buffer units of each of the shift buffer units, a source coupled to the first node, and a drain coupled to the first power source Voltage.
  • the second pull-down holding circuit further includes: a twelfth transistor having a gate coupled to a driving signal end of the next two shift buffer units of each shift buffer unit, the source being coupled to the source The output terminal is coupled to the first power supply voltage.
  • the pull-down circuit includes: a thirteenth transistor, a gate of which is coupled to a driving signal end of a next shift buffer unit of each shift buffer unit, and a source coupled to the driving signal end, The drain is coupled to the second power voltage.
  • the pull-down circuit further includes: a fourteenth transistor, the gate of which is coupled to the driving signal end of the next shift buffer unit of each shift buffer unit, and the source is coupled to the output end, The drain is coupled to the first power voltage.
  • the pull-down circuit further includes: a fifteenth transistor, the gate of which is coupled to the driving signal end of the next shift buffer unit of each shift buffer unit, and the source is coupled to the first node The drain is coupled to the first power voltage.
  • the pull-down circuit further includes: a fifteenth transistor, the gate of which is coupled to the driving signal end of the next shift buffer unit of each shift buffer unit, and the source is coupled to the first node And a sixteenth transistor, the gate and the source are coupled to the drain of the fifteenth transistor, and the drain is coupled to the first power voltage.
  • the rising circuit is a capacitor.
  • the voltage of the first fixed voltage is greater than the second fixed voltage.
  • the gate driver of the present invention effectively combines the pull-down holding circuit and the signal, and can effectively cut the structure of the circuit, and can truly realize the design of the ultra-narrow bezel gate driver.
  • the seventh transistor of the first pull-down holding circuit adopts the connection mode of the equivalent diode to effectively reduce the voltage offset effect of the second node P(N), prolong the operation time of the GOA circuit, and increase the service life of the liquid crystal display.
  • reducing the number of transistors and signals used by the first and second pull-down holding circuits can reduce the RC delay of the circuit, can effectively reduce the power consumption of the circuit, and more effectively reduce the power consumption of the liquid crystal display.
  • Figure 1 is a functional block diagram of a liquid crystal display of the present invention.
  • FIG. 2 is a block diagram of a shift buffer unit of a gate driver of the present invention.
  • 3A is a circuit diagram of a first embodiment of the shift buffer unit of FIG. 2.
  • FIG. 3B is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 3A.
  • 4A is a circuit diagram of a second embodiment of the shift buffer unit of FIG. 2.
  • FIG. 4B is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 4A.
  • Figure 5A is a circuit diagram of a third embodiment of the shift buffer unit of Figure 2.
  • Figure 5B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 5A.
  • Figure 6A is a circuit diagram of a fourth embodiment of the shift buffer unit of Figure 2.
  • Figure 6B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 6A.
  • Figure 7A is a circuit diagram of a fifth embodiment of the shift buffer unit of Figure 2.
  • Figure 7B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 7A.
  • Figure 8A is a circuit diagram of a sixth embodiment of the shift buffer unit of Figure 2.
  • Figure 8B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 8A.
  • Figure 9A is a circuit diagram of a seventh embodiment of the shift buffer unit of Figure 2.
  • Figure 9B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 9A.
  • Figure 10A is a circuit diagram of an eighth embodiment of the shift buffer unit of Figure 2.
  • Figure 10B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 10A.
  • Figure 11A is a circuit diagram of a ninth embodiment of the shift buffer unit of Figure 2.
  • Figure 11B is a timing diagram of various input signals, output signals, and node voltages shown in Figure 11A.
  • FIG. 1 is a functional block diagram of a liquid crystal display device 10 of the present invention.
  • the liquid crystal display 10 includes a liquid crystal display panel 12 and a gate driver (gate Driver) 14 and source driver (source Driver)16.
  • the liquid crystal display panel 12 includes a plurality of pixels, and each of the pixels includes three pixel units 20 respectively representing three primary colors of red, green and blue (RGB). Take a 1024 ⁇ For the 768 resolution LCD panel 12, a total of 1024 ⁇ 768 ⁇ Three pixel units 20 are combined.
  • the gate driver 14 outputs a scan signal such that the transistors 22 of each row are sequentially turned on, while the source driver 16 outputs corresponding data signals to an entire column of pixel units 20 to charge them to respective required voltages to display different grays. Order. When the same row is charged, the gate driver 14 turns off the scan signal of the row, and then the gate driver 14 outputs the scan signal to turn on the transistor 22 of the next row, and then the source driver 16 pairs the pixel unit 20 of the next row. Charge and discharge. This is continued until all the pixel units 20 of the liquid crystal display panel 12 are fully charged, and charging is started from the first column.
  • the gate driver 14 is equivalently a shift register (shift Register), the purpose of which is to output a scan signal to the liquid crystal display panel 12 at regular intervals.
  • shift Register shift Register
  • the source driver 16 charges and discharges the pixel unit 20 to a desired voltage during the 21.7 ⁇ s period to display the corresponding gray scale.
  • FIG. 2 is a block diagram of the shift buffer unit SR(N) of the gate driver 14 of the present invention.
  • the gate driver 14 includes a plurality of cascade-connected shift buffer units SR(N), N is 0 or a positive integer.
  • the shift buffer unit SR(N) is configured to be based on the first clock signal CK, a second clock signal XCK, and a driving signal of the first stage shift buffer unit SR(N-1) of each shift buffer unit SR(N).
  • Pulse ST(N-1) output per shift buffer unit SR(N) Scanning signal.
  • the shift buffer unit 100(1) receives a start pulse from the input terminal ST(0), the shift buffer unit 100(1) is separated by a standard clock (clock).
  • each shift buffer unit SR(N) is based on the first clock signal CK, the second clock signal XCK, and each shift buffer unit SR(N).
  • the drive signal pulse outputted by the previous stage shift buffer unit SR(N-1) at the drive signal terminal ST(N-1) outputs the shift register at the output terminal OUT(N) every other standard clock.
  • the output signal of the unit SR(N), which is a scan signal pulse, is used to output and turn on the transistor of the corresponding pixel unit 112.
  • the phase of the first clock signal CK and the second clock signal XCK are 180 degrees out of phase.
  • Each shift buffer unit SR(N) includes a pull-up control circuit (pull-up control) Circuit) 100, pull-up circuit 200, transfer circuit 300, pull-down circuit (pull-down) Circuit) 400 and pull-down hold circuit 500.
  • the pull-down holding circuit 500 includes a first pull-down holding circuit 510 and a second pull-down holding circuit 520.
  • FIG. 3A is a circuit diagram of a first embodiment of the shift buffer unit SR(N) of FIG.
  • the pull-up circuit 200 can be a first transistor T1 having a gate coupled to the first node Q(N), a source coupled to the first clock signal CK, and a drain coupled to the output terminal G(N).
  • the output signal pulse is provided by the output terminal G(N) according to the first clock signal CK.
  • the lower pass circuit 300 may be a second transistor T2 having a gate coupled to the first node Q(N), a source coupled to the first clock signal CK, and a drain coupled to the drive signal terminal ST(N).
  • the driving signal pulse is output from the driving signal terminal ST(N) according to the first clock signal CK.
  • the pull-up control circuit 100 can be a third transistor T3 whose gate is coupled to the output signal terminal G(N-1) of the previous shift buffer unit SR(N-1), and the source is coupled to the previous shift.
  • the driving signal terminal ST(N-1) of the buffer unit SR(N-1) is coupled to the first node Q(N) for driving signals according to the previous shift buffer unit SR(N-1).
  • Pulsed, the pull-up circuit 200 is turned on.
  • the rising circuit 600 can be a capacitor Cb coupled between the first node Q(N) and the output terminal G(N) for raising the potential Q(N) of the first node.
  • the first pull-down holding circuit 510 is coupled to the first node G(N), the first clock signal CK, the first fixed voltage VSS1, and the second fixed voltage VSS2 for maintaining the low voltage of the first node Q(N). level.
  • the second pull-down holding circuit 520 is coupled to the first node Q(N), the driving signal terminal ST(N+2) of the next two shift buffer units SR(N+2) of each shift buffer unit, and the first The fixed voltage VSS1 and the second fixed voltage VSS2 are used to pull down the potential of the first node Q(N) according to the driving signal of the next two shift buffer units SR(N+2) of each shift buffer unit.
  • the pull-down circuit 400 is coupled to the first fixed voltage VSS1, the driving signal terminal ST(N), and the driving signal terminal ST(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, It is used to pull down the potential of the first node Q(N) to the first fixed voltage VSS1.
  • the voltage of the first fixed voltage VSS1 is greater than the second fixed voltage VSS2.
  • the first pull-down holding circuit 510 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.
  • the gate of the fourth transistor T4 is coupled to the first clock signal CK
  • the source is coupled to the first clock signal CK
  • the drain is coupled to the second node P(N).
  • the gate of the fifth transistor T5 is coupled to the driving signal terminal ST(N)
  • the source is coupled to the second node P(N)
  • the drain is coupled to the second power voltage VSS2.
  • the gate of the sixth transistor T6 is coupled to the driving signal terminal ST(N-1) of the previous shift buffer unit SR(N-1), the source is coupled to the second node P(N), and the drain is coupled. At the second power supply voltage VSS2.
  • the gate of the seventh transistor T7 is coupled to the second clock signal XCK, the source is coupled to the first clock signal CK, and the drain is coupled to the second node P(N).
  • the gate of the eighth transistor T8 is coupled to the second node P(N), the source is coupled to the output terminal G(N), and the drain is coupled to the first power supply voltage VSS1.
  • the gate of the ninth transistor T9 is coupled to the second node P(N), the source is coupled to the first node Q(N), and the drain is coupled to the first power supply voltage VSS1.
  • the gate of the tenth transistor T10 is coupled to the second node P(N), the source is coupled to the driving signal terminal ST(N), and the drain is coupled to the second power voltage VSS2.
  • the second pull-down holding circuit 520 includes an eleventh transistor T11 and a twelfth transistor T12.
  • the gate of the eleventh transistor T11 is coupled to the driving signal terminal ST(N+2) of the next two shift buffer units SR(N+2) of each shift buffer unit, and the source is coupled to the first
  • the node Q(N) has a drain coupled to the first power supply voltage VSS1.
  • the gate of the twelfth transistor T12 is coupled to the driving signal terminal ST(N+2) of the next two shift buffer units SR(N+2) of each shift buffer unit, and the source is coupled to the output end.
  • G(N) the drain is coupled to the first power supply voltage VSS1.
  • the pull-down circuit 400 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15.
  • the gate of the thirteenth transistor T13 is coupled to the driving signal terminal ST(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the driving signal end.
  • ST (N) the drain is coupled to the second power voltage VSS2.
  • the gate of the fourteenth transistor T14 is coupled to the driving signal terminal ST(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the output terminal G.
  • the drain is coupled to the first power supply voltage VSS1.
  • the gate of the fifteenth transistor T15 is coupled to the driving signal terminal ST(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the first node Q. (N), the drain is coupled to the first power supply voltage VSS1.
  • FIG. 3B is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 3A.
  • the eighth transistor T8 is used to output the terminal G(N) Maintain at a low level.
  • the ninth transistor T9 is used to maintain the first node Q(N) at a low level.
  • the fifth transistor T5 is for using the second node P(N) when the driving signal terminal ST(N) is at a high level. The potential is pulled down.
  • the sixth transistor T6 is for using the second node P(N) when the driving signal terminal ST(N-1) is at a high level.
  • the potential is pulled down to turn off the pull-down holding circuit 510 during the action to prevent the effects on the output of the first node Q(N) and the output terminal G(N).
  • the potential of the second fixed voltage VSS2 is lower than the first fixed voltage VSS1
  • the purpose of (VSS2 ⁇ VSS1) is to lower the potential of the second node P(N) by the two-stage voltage division principle. Therefore, the lower the potential of the second node P(N) during the action is pulled, the eighth transistor T8 and the ninth transistor T9 will be turned off more efficiently without being turned on, and the output terminal G(N) can be prevented.
  • the discharge causes the output to be abnormal.
  • the twelfth transistor T12 and the eleventh transistor T11 are respectively used to pull down the potentials of the first node Q(N) and the output terminal G(N) at the next period after the output terminal G(N) is output, to ensure the first The potential of node Q(N) and output G(N) can be quickly pulled down.
  • the output terminal G(N) is pulled to the same low level as the first fixed voltage VSS1, and the second node P(N) is at the first node Q(N) and the output terminal G(N).
  • FIG. 4A is a circuit diagram of a second embodiment of the shift buffer unit SR(N) of FIG. 2.
  • 4B is a timing diagram of various input signals, output signals, and node voltages shown in FIG. 4A.
  • the shift buffer unit SR(N) of FIG. 4A has the same label component as the shift buffer unit SR(N) of FIG. 3A, and its operation principle is the same, and will not be further described herein.
  • the difference between FIG. 4A and FIG. 3A is that the pull-down circuit 400 further includes a sixteenth transistor T16, and the connection of the fifteenth transistor T15 and the sixteenth transistor T16 is also different.
  • the gate of the fifteenth transistor T15 is coupled to the driving signal terminal ST(n+1) of the next shift buffer unit SR(n+1) of each shift buffer unit, and the source is coupled to the first Node Q(N).
  • the gate and the source of the sixteenth transistor T16 are coupled to the drain of the fifteenth transistor T15, and the drain is coupled to the first power supply voltage VSS1.
  • the shift buffer unit SR(N) of FIG. 4A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 3A, and will not be further described herein.
  • Figure 5A is a circuit diagram of a third embodiment of the shift buffer unit of Figure 2.
  • Figure 5B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 5A.
  • the shift buffer unit SR(N) of FIG. 5A has the same label component as the shift buffer unit SR(N) of FIG. 3A, and the operation principle is the same, and no further details are provided herein.
  • the difference between FIG. 5A and FIG. 3A is that the gate of the seventh transistor T7 of the first pull-down holding circuit 510 is coupled to the second node P(N), and the first clock signal CK and the second clock signal XCK signal can be reduced. Cross-line crosstalk between. Compared with FIG.
  • the shift buffer unit SR(N) of FIG. 5A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 3A, and will not be further described herein.
  • Figure 6A is a circuit diagram of a fourth embodiment of the shift buffer unit of Figure 2.
  • Figure 6B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 6A.
  • the shift buffer unit SR(N) of FIG. 6A has the same label component as the shift buffer unit SR(N) of FIG. 3A, and its operation principle is the same, and will not be further described herein.
  • the difference between FIG. 6A and FIG. 3A is that the second pull-down holding circuit 520 without the twelfth transistor T12 can further reduce the number of transistors to reduce the RC delay.
  • the shift buffer unit SR(N) of FIG. 6A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 3A, and will not be further described herein.
  • Figure 7A is a circuit diagram of a fifth embodiment of the shift buffer unit of Figure 2.
  • Figure 7B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 7A.
  • the shift buffer unit SR(N) of FIG. 6A has the same label component as the shift buffer unit SR(N) of FIG. 7A, and its operation principle is the same, and will not be further described herein.
  • the difference between FIG. 7A and FIG. 6A is that the gate of the seventh transistor T7 of the first pull-down holding circuit 510 is coupled to the second node P(N), and the first clock signal CK and the second clock signal XCK signal can be reduced. Cross-line crosstalk between. Compared with FIG.
  • the shift buffer unit SR(N) of FIG. 7A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 6A, and will not be further described herein.
  • Figure 8A is a circuit diagram of a sixth embodiment of the shift buffer unit of Figure 2.
  • Figure 8B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 8A.
  • the shift buffer unit SR(N) of FIG. 8A has the same label component as the shift buffer unit SR(N) of FIG. 6A, and the operation principle is the same, and no further details are provided herein.
  • the difference between FIG. 8A and FIG. 6A is that the absence of the fifteenth transistor T15 of the pull-down circuit 400 can further reduce the number of transistors to reduce the RC delay.
  • the shift buffer unit SR(N) of FIG. 8A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 6A, and will not be further described herein.
  • Figure 9A is a circuit diagram of a seventh embodiment of the shift buffer unit of Figure 2.
  • Figure 9B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 9A.
  • the shift buffer unit SR(N) of FIG. 9A has the same label component as the shift buffer unit SR(N) of FIG. 8A, and its operation principle is the same, and will not be further described herein.
  • the difference between FIG. 9A and FIG. 8A is that the gate of the seventh transistor T7 of the first pull-down holding circuit 510 is coupled to the second node P(N), and the first clock signal CK and the second clock signal XCK signal can be reduced. Cross-line crosstalk between. Compared with FIG.
  • the shift buffer unit SR(N) of FIG. 9A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 8A, and will not be further described herein.
  • Figure 10A is a circuit diagram of an eighth embodiment of the shift buffer unit of Figure 2.
  • Figure 10B is a timing diagram of the various input signals, output signals, and node voltages shown in Figure 10A.
  • the shift buffer unit SR(N) of FIG. 10A has the same label component as the shift buffer unit SR(N) of FIG. 8A, and its operation principle is the same, and will not be further described herein.
  • the difference between FIG. 10A and FIG. 8A is that the pull-down circuit 400 without the fourteenth transistor T14 can further reduce the number of transistors to reduce the RC delay.
  • the shift buffer unit SR(N) of FIG. 10A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 8A, and will not be further described herein.
  • Figure 11A is a circuit diagram of a ninth embodiment of the shift buffer unit of Figure 2.
  • Figure 11B is a timing diagram of various input signals, output signals, and node voltages shown in Figure 11A.
  • the shift buffer unit SR(N) of FIG. 11A has the same label component as the shift buffer unit SR(N) of FIG. 10A, and the operation principle is the same, and no further details are provided herein.
  • the difference between FIG. 11A and FIG. 10A is that the gate of the seventh transistor T7 of the first pull-down holding circuit 510 is coupled to the second node P(N), and the first clock signal CK and the second clock signal XCK signal can be reduced. Cross-line crosstalk between. Compared to FIG.
  • the shift buffer unit SR(N) of FIG. 11A has the same operation principle and the same effect as the shift buffer unit SR(N) of FIG. 10A, and will not be further described herein.
  • the gate driver of the present invention effectively combines the pull-down holding circuit and the signal, and can effectively cut the structure of the circuit, and can truly realize the design of the ultra-narrow bezel gate driver.
  • the seventh transistor of the first pull-down holding circuit adopts the connection mode of the equivalent diode to effectively reduce the voltage offset effect of the second node, prolong the operation time of the GOA circuit, and increase the service life of the liquid crystal display.
  • reducing the number of transistors and signals used by the first and second pull-down holding circuits can reduce the RC delay of the circuit, can effectively reduce the power consumption of the circuit, and more effectively reduce the power consumption of the liquid crystal display.

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  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

在栅极驱动器中利用下拉保持电路对信号的作用，实现对电路的架构有效的删减，能真正的做到超窄边框栅极驱动器的设计。此外，第一下拉保持电路（510）的晶体管采用等效二极管的连接方式可以有效降低电压偏移作用，延长GOA电路的操作时间，增加液晶显示器的使用寿命。最后，减少第一（510）和第二下拉保持电路（520）使用的晶体管和信号数量，可以减小电路的RC延迟，可以有效地降低电路的功耗，更加有效的降低液晶显示器的能耗。

Description

用于窄边框液晶显示器的栅极驱动器 技术领域
本发明涉及平面显示领域，尤其一种用于窄边框液晶显示器的栅极驱动器。
 背景技术
GOA（Gate Driver On Array）电路是利用薄膜晶体管液晶显示器Array制程将栅极驱动器制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式。
GOA电路主要由上拉电路（Pull-up circuit）、上拉控制电路（Pull-up control circuit）、下传电路(Transfer circuit)、下拉电路（Pull-down circuit）、下拉保持电路（Pull-down Holding circuit）、以及负责电位抬升的上升电路(Boost circuit)组成。
上拉电路主要负责将输入的时钟信号（Clock）输出至薄膜晶体管(thin film transistor，TFT)的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速地将扫描信号(亦即薄膜晶体管的栅极的电位)拉低为低电平。下拉保持电路则负责将扫描信号和上拉电路的信号（亦即施加于Q点的信号）保持在关闭状态（即设定的负电位），通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
传统GOA电路存在如下不足之处：（1）电路的TFT和信号线的数量较多，这对不利于窄边框显示装置甚至无边框显示装置的设计；（2）较多TFT和信号线的数量，必然会增加RC效应，会使得电路具有较高的能耗，对于低能耗需求的标准较难满足，不能达到未来绿色环保的设计要求。
 技术问题
有鉴于此，本发明的目的是提供一种使用较少TFT的栅极驱动器，以解决现有技术的问题。
 技术解决方案
本发明提供一种栅极驱动器，其包含：数个移位缓存单元，所述数个移位缓存单元系以串联的方式耦接，每一移位缓存单元用来依据第一时钟信号、第二时钟信号以及该每一移位缓存单元的前一个移位缓存单元的驱动信号脉冲，在所述每一移位缓存单元的输出端输出输出信号脉冲。每一移位缓存单元包含：一上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于该输出端，用来依据该第一时钟信号，由该输出端提供该输出信号脉冲；一下传电路，其包含第二晶体管，其栅极耦接于该第一节点，源极耦接于第一时钟信号，漏极耦接于驱动信号端，用来依据该第一时钟信号，由该驱动信号端输出驱动信号脉冲；一上拉控制电路，其包含第三晶体管，其栅极耦接于该每一移位缓存单元的前一个移位缓存单元的输出信号端，源极耦接于该每一移位缓存单元的前一个移位缓存单元的驱动信号端，漏极耦接于该第一节点，用来依据该每一移位缓存单元的前一个移位缓存单元的该驱动信号脉冲，导通该上拉电路；一上升电路，耦接于该第一节点和该输出端之间，用来抬升该第一节点的电位；一第一下拉保持电路，耦接于该第一节点、该第一时钟信号、第一固定电压以及第二固定电压，用来依据维持该第一节点的低电平；一第二下拉保持电路，耦接于该第一节点、该每一移位缓存单元的下两个移位缓存单元的驱动信号端、该第一固定电压以及该第二固定电压，用来依据该每一移位缓存单元的下两个移位缓存单元的驱动信号，下拉该第一节点的电位；以及一下拉电路，耦接于该第一固定电压、该驱动信号端以及该每一移位缓存单元的下一个移位缓存单元的驱动信号端，用来下拉该第一节点的电位至该第一固定电压。
依据本发明，所述第一下拉保持电路包含：第四晶体管，其栅极耦接于该第一时钟信号，源极耦接于第一时钟信号，漏极耦接于第二节点；第五晶体管，其栅极耦接于该驱动信号端，源极耦接于该第二节点，漏极耦接于该第二电源电压；第六晶体管，其栅极耦接于该每一移位缓存单元的前一个移位缓存单元的驱动信号端，源极耦接于该第二节点，漏极耦接于该第二电源电压；第七晶体管，其栅极耦接于该第二时钟信号或是该第二节点，源极耦接于该第一时钟信号，漏极耦接于该第二节点；第八晶体管，其栅极耦接于该第二节点，源极耦接于该输出端，漏极耦接于该第一电源电压；第九晶体管，其栅极耦接于该第二节点，源极耦接于该第一节点，漏极耦接于该第一电源电压；以及第十晶体管，其栅极耦接于该第二节点，源极耦接于该驱动信号端，漏极耦接于该第二电源电压。
依据本发明，所述第二下拉保持电路包含： 第十一晶体管，其栅极耦接于该每一移位缓存单元的下两个移位缓存单元的驱动信号端，源极耦接于该第一节点，漏极耦接于该第一电源电压。
依据本发明，所述第二下拉保持电路另包含：第十二晶体管，其栅极耦接于该每一移位缓存单元的下两个移位缓存单元的驱动信号端，源极耦接于该输出端，漏极耦接于该第一电源电压。
依据本发明，所述下拉电路包含：第十三晶体管，其栅极耦接于该每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于该驱动信号端，漏极耦接于该第二电源电压。
依据本发明，所述下拉电路另包含：第十四晶体管，其栅极耦接于该每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于该输出端，漏极耦接于该第一电源电压。
依据本发明，所述下拉电路另包含：第十五晶体管，其栅极耦接于该每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于该第一节点，漏极耦接于该第一电源电压。
依据本发明，所述下拉电路另包含：第十五晶体管，其栅极耦接于该每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于该第一节点；以及第十六晶体管，其栅极和源极皆耦接于该第十五晶体管的漏极，漏极耦接于该第一电源电压。
依据本发明，所述上升电路是一电容。
依据本发明，该第一固定电压的电压大于该第二固定电压。
 有益效果
相较于现有技术，本发明的栅极驱动器将下拉保持电路和信号的有效结合，可以对电路的架构有效的删减，能真正的做到超窄边框栅极驱动器的设计。此外，第一下拉保持电路的第七晶体管采用等效二极管的连接方式可以有效低降低第二节点P(N)的电压偏移作用，延长GOA电路的操作时间，增加液晶显示器的使用寿命。最后，减少第一和第二下拉保持电路使用的晶体管和信号数量，可以减小电路的RC延迟，可以有效地降低电路的功耗，更加有效的降低液晶显示器的能耗。
 附图说明
图1是本发明的液晶显示器的功能方块图。
图2是本发明的栅极驱动器的移位缓存单元的方块图。
图3A是图2移位缓存单元的第一实施例的电路图。
图3B是图3A所示各种输入信号、输出信号和节点电压的时序图。
图4A是图2移位缓存单元的第二实施例的电路图。
图4B是图4A所示各种输入信号、输出信号和节点电压的时序图。
图5A是图2移位缓存单元的第三实施例的电路图。
图5B是图5A所示各种输入信号、输出信号和节点电压的时序图。
图6A是图2移位缓存单元的第四实施例的电路图。
图6B是图6A所示各种输入信号、输出信号和节点电压的时序图。
图7A是图2移位缓存单元的第五实施例的电路图。
图7B是图7A所示各种输入信号、输出信号和节点电压的时序图。
图8A是图2移位缓存单元的第六实施例的电路图。
图8B是图8A所示各种输入信号、输出信号和节点电压的时序图。
图9A是图2移位缓存单元的第七实施例的电路图。
图9B是图9A所示各种输入信号、输出信号和节点电压的时序图。
图10A是图2移位缓存单元的第八实施例的电路图。
图10B是图10A所示各种输入信号、输出信号和节点电压的时序图。
图11A是图2移位缓存单元的第九实施例的电路图。
图11B是图11A所示各种输入信号、输出信号和节点电压的时序图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，图1是本发明的液晶显示器10的功能方块图。液晶显示器10包含液晶显示面板12、栅极驱动器(gate driver)14以及源极驱动器(source driver)16。液晶显示面板12包含数个像素(pixel)，而每一个像素包含三个分别代表红绿蓝(RGB)三原色的像素单元20构成。以一个1024 × 768分辨率的液晶显示面板12来说，共需要1024 × 768 × 3个像素单元20组合而成。栅极驱动器14输出扫描信号使得每一行的晶体管22依序开启，同时源极驱动器16则输出对应的数据信号至一整列的像素单元20使其充电到各自所需的电压，以显示不同的灰阶。当同一行充电完毕后，栅极驱动器14便将该行的扫描信号关闭，然后栅极驱动器14再输出扫描信号将下一行的晶体管22打开，再由源极驱动器16对下一行的像素单元20进行充放电。如此依序下去，直到液晶显示面板12的所有像素单元20都充电完成，再从第一列开始充电。
在目前的液晶显示面板设计中，栅极驱动器14等效上为移位寄存器(shift register)，其目的即每隔一固定间隔输出扫描信号至液晶显示面板12。以一个1024 × 768分辨率的液晶显示面板12以及60Hz的更新频率为例，每一个画面的显示时间约为1/60=16.67ms。所以每一个扫描信号的脉波约为16.67ms/768=21.7μs。而源极驱动器16则在这21.7μs的时间内，将像素单元20充放电到所需的电压，以显示出相对应的灰阶。
请参阅图2，图2是本发明的栅极驱动器14的移位缓存单元SR(N)的方块图。栅极驱动器14包含数个串接(cascade-connected)的移位缓存单元SR(N)， N为0或正整数。移位缓存单元SR(N)用来依据第一时钟信号CK、一第二时钟信号XCK以及每一移位缓存单元SR(N)之前一级移位缓存单元SR(N-1)的驱动信号脉冲ST(N-1)输出每一移位缓存单元SR(N) 的扫描信号。当第一级移位缓存单元100(1)自输入端ST(0)接收到起始脉冲(start pulse)后，移位缓存单元100(1)就会隔一标准时钟(clock cycle)输出产生输出信号脉冲ST(1)，接下来，每一移位缓存单元SR(N)依据第一时钟信号CK、第二时钟信号XCK以及每一移位缓存单元SR(N) 的前一级移位缓存单元SR(N-1)于驱动信号端ST(N-1)输出的驱动信号脉冲，以每隔一标准时钟于输出端OUT(N)输出该每一移位缓存单元SR(N)的输出信号，该输出信号即扫描信号脉冲，用来输出并开启对应的像素单元112的晶体管。第一时钟信号CK与第二时钟信号XCK的相位相差180度。
每一移位缓存单元SR(N)包含上拉控制电路(pull-up control circuit)100、上拉电路(pull-up circuit)200、下传电路(transfer circuit)300、下拉电路(pull-down circuit)400以及下拉保持电路500。下拉保持电路500包含第一下拉保持电路510和第二下拉保持电路520。
请参阅图3A，图3A是图2移位缓存单元SR(N)的第一实施例的电路图。上拉电路200可以是第一晶体管T1，其栅极耦接于第一节点Q(N)，源极耦接于第一时钟信号CK，漏极耦接于该输出端G(N)，用来依据第一时钟信号CK，由输出端G(N)提供输出信号脉冲。下传电路300可以是第二晶体管T2，其栅极耦接于该第一节点Q(N)，源极耦接于第一时钟信号CK，漏极耦接于驱动信号端ST(N)，用来依据第一时钟信号CK，由驱动信号端ST(N)输出驱动信号脉冲。上拉控制电路100可以是第三晶体管T3，其栅极耦接于前一个移位缓存单元SR(N-1)的输出信号端G(N-1)，源极耦接于前一个移位缓存单元SR(N-1)的驱动信号端ST(N-1)，漏极耦接于第一节点Q(N)，用来依据前一个移位缓存单元SR(N-1)的驱动信号脉冲，导通上拉电路200。上升电路600可以是一电容Cb，其耦接于第一节点Q(N)和输出端G(N)之间，用来抬升第一节点的电位Q(N)。第一下拉保持电路510耦接于第一节点G(N)、第一时钟信号CK、第一固定电压VSS1以及第二固定电压VSS2，用来依据维持第一节点Q(N)的低电平。第二下拉保持电路520耦接于第一节点Q(N)、每一移位缓存单元的下两个移位缓存单元SR(N+2)的驱动信号端ST(N+2)、第一固定电压VSS1以及第二固定电压VSS2，用来依据每一移位缓存单元的下两个移位缓存单元SR(N+2)的驱动信号，下拉第一节点Q(N)的电位。下拉电路400耦接于第一固定电压VSS1、驱动信号端ST(N)以及每一移位缓存单元的下一个移位缓存单元SR(n+1)的驱动信号端ST(n+1)，用来下拉第一节点Q(N)的电位至第一固定电压VSS1。较佳实施例中，第一固定电压VSS1的电压大于第二固定电压VSS2。
第一下拉保持电路510包含第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9和第十晶体管T10。第四晶体管T4的栅极耦接于第一时钟信号CK，源极耦接于第一时钟信号CK，漏极耦接于第二节点P(N)。第五晶体管T5的栅极耦接于该驱动信号端ST(N)，源极耦接于该第二节点P(N)，漏极耦接于第二电源电压VSS2。第六晶体管T6的栅极耦接于前一个移位缓存单元SR(N-1)的驱动信号端ST(N-1)，源极耦接于第二节点P(N)，漏极耦接于第二电源电压VSS2。第七晶体管T7的栅极耦接于第二时钟信号XCK，源极耦接于该第一时钟信号CK，漏极耦接于第二节点P(N)。第八晶体管T8的栅极耦接于第二节点P(N)，源极耦接于输出端G(N)，漏极耦接于第一电源电压VSS1。第九晶体管T9的栅极耦接于第二节点P(N)，源极耦接于第一节点Q(N)，漏极耦接于第一电源电压VSS1。第十晶体管T10的栅极耦接于第二节点P(N)，源极耦接于驱动信号端ST(N)，漏极耦接于第二电源电压VSS2。
第二下拉保持电路520包含第十一晶体管T11和第十二晶体管T12。 第十一晶体管T11的栅极耦接于该每一移位缓存单元的下两个移位缓存单元SR(N+2)的驱动信号端ST(N+2)，源极耦接于第一节点Q(N)，漏极耦接于第一电源电压VSS1。第十二晶体管T12的栅极耦接于该每一移位缓存单元的下两个移位缓存单元SR(N+2)的驱动信号端ST(N+2)，源极耦接于输出端G(N)，漏极耦接于第一电源电压VSS1。
下拉电路400包含第十三晶体管T13、第十四晶体管T14和第十五晶体管T15。第十三晶体管T13的栅极耦接于该每一移位缓存单元的下一个移位缓存单元SR(n+1)的驱动信号端ST(n+1)，源极耦接于驱动信号端ST(N)，漏极耦接于第二电源电压VSS2。第十四晶体管T14的栅极耦接于该每一移位缓存单元的下一个移位缓存单元SR(n+1)的驱动信号端ST(n+1)，源极耦接于输出端G(N)，漏极耦接于第一电源电压VSS1。第十五晶体管T15的栅极耦接于每一移位缓存单元的下一个移位缓存单元SR(n+1)的驱动信号端ST(n+1)，源极耦接于第一节点Q(N)，漏极耦接于第一电源电压VSS1。
请一并参阅图3A和图3B。图3B是图3A所示各种输入信号、输出信号和节点电压的时序图。第八晶体管T8用来将输出端G(N) 维持在低电平。第九晶体管T9用来将第一节点Q(N) 维持在低电平。第五晶体管T5用来当驱动信号端ST(N)处于高电平的时候将第二节点P(N) 的电位下拉。第六晶体管T6用来当驱动信号端ST(N-1)处于高电平的时候将第二节点P(N) 的电位下拉，从而关闭作用期间的下拉保持电路510，以防止对第一节点Q(N)和输出端G(N)输出的影响。第二固定电压VSS2的电位低于第一固定电压VSS1 (VSS2<VSS1)的目的是为了通过两段分压原理降低第二节点P(N)的电位。因此第二节点P(N)在作用期间的电位被拉得越低，则第八晶体管T8和第九晶体管T9将会更有效地关闭而不导通，可防止对输出端G(N)的放电导致输出异常。第十二晶体管T12和第十一晶体管T11分别用来在输出端G(N)输出后，在下一时段时下拉第一节点Q(N)和输出端G(N)的电位，以确保第一节点Q(N)和输出端G(N)的电位能快速下拉。
从图3B可以看出，输出端G(N)会被拉到第一固定电压VSS1一样的低电平，第二节点P(N)在第一节点Q(N)和输出端G(N)处于高电平时会被拉到比第一固定电压VSS2更低的电平。这样第八晶体管T8和第九晶体管T9的栅极-源极电压Vgs=VSS2-VSS1<0，可以有效地降低第八晶体管T8和第九晶体管T9的漏电流。
请参阅图4A和图4B。图4A是图2移位缓存单元SR(N)的第二实施例的电路图。图4B是图4A所示各种输入信号、输出信号和节点电压的时序图。图4A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图4A和图3A的差异在于，下拉电路400另包含第十六晶体管T16，且第十五晶体管T15和第十六晶体管T16的连结也不相同。第十五晶体管T15的栅极耦接于该每一移位缓存单元的下一个移位缓存单元SR(n+1)的驱动信号端ST(n+1)，源极耦接于该第一节点Q(N)。第十六晶体管T16的栅极和源极皆耦接于该第十五晶体管T15的漏极，漏极耦接于第一电源电压VSS1。图4A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图5A和图5B。图5A是图2移位缓存单元的第三实施例的电路图。图5B是图5A所示各种输入信号、输出信号和节点电压的时序图。图5A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图5A和图3A的差异在于，第一下拉保持电路510的第七晶体管T7的栅极耦接于第二节点P(N)，可以减小第一时钟信号CK和第二时钟信号XCK信号之间的跨线串扰。相较于图3B，跟据第七晶体管T7的波形，第二节点P(N)能更有效的放电。图5A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图6A和图6B。图6A是图2移位缓存单元的第四实施例的电路图。图6B是图6A所示各种输入信号、输出信号和节点电压的时序图。图6A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图6A和图3A的差异在于，第二下拉保持电路520没有第十二晶体管T12可以进一步减少晶体管的数量，以减少RC延迟。图6A的移位缓存单元SR(N)与图3A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图7A和图7B。图7A是图2移位缓存单元的第五实施例的电路图。图7B是图7A所示各种输入信号、输出信号和节点电压的时序图。图6A的移位缓存单元SR(N)与图7A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图7A和图6A的差异在于，第一下拉保持电路510的第七晶体管T7的栅极耦接于第二节点P(N)，可以减小第一时钟信号CK和第二时钟信号XCK信号之间的跨线串扰。相较于图6B，跟据第七晶体管T7的波形，第二节点P(N)能更有效的放电。图7A的移位缓存单元SR(N)与图6A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图8A和图8B。图8A是图2移位缓存单元的第六实施例的电路图。图8B是图8A所示各种输入信号、输出信号和节点电压的时序图。图8A的移位缓存单元SR(N)与图6A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图8A和图6A的差异在于，下拉电路400没有第十五晶体管T15可以进一步减少晶体管的数量，以减少RC延迟。图8A的移位缓存单元SR(N)与图6A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图9A和图9B。图9A是图2移位缓存单元的第七实施例的电路图。图9B是图9A所示各种输入信号、输出信号和节点电压的时序图。图9A的移位缓存单元SR(N)与图8A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图9A和图8A的差异在于，第一下拉保持电路510的第七晶体管T7的栅极耦接于第二节点P(N)，可以减小第一时钟信号CK和第二时钟信号XCK信号之间的跨线串扰。相较于图8B，跟据第七晶体管T7的波形，第二节点P(N)能更有效的放电。图9A的移位缓存单元SR(N)与图8A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图10A和图10B。图10A是图2移位缓存单元的第八实施例的电路图。图10B是图10A所示各种输入信号、输出信号和节点电压的时序图。图10A的移位缓存单元SR(N)与图8A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图10A和图8A的差异在于，下拉电路400没有第十四晶体管T14可以进一步减少晶体管的数量，以减少RC延迟。图10A的移位缓存单元SR(N)与图8A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
请参阅图11A和图11B。图11A是图2移位缓存单元的第九实施例的电路图。图11B是图11A所示各种输入信号、输出信号和节点电压的时序图。图11A的移位缓存单元SR(N)与图10A的移位缓存单元SR(N)具有相同标号组件者，其操作原理相同，在此不另赘述。图11A和图10A的差异在于，第一下拉保持电路510的第七晶体管T7的栅极耦接于第二节点P(N)，可以减小第一时钟信号CK和第二时钟信号XCK信号之间的跨线串扰。相较于图10B，跟据第七晶体管T7的波形，第二节点P(N)能更有效的放电。图11A的移位缓存单元SR(N)与图10A的移位缓存单元SR(N)的运作原理相同和达成效果相同，在此不另赘述。
相较于现有技术，本发明的栅极驱动器将下拉保持电路和信号的有效结合，可以对电路的架构有效的删减，能真正的做到超窄边框栅极驱动器的设计。此外，第一下拉保持电路的第七晶体管采用等效二极管的连接方式可以有效低降低第二节点的电压偏移作用，延长GOA电路的操作时间，增加液晶显示器的使用寿命。最后，减少第一和第二下拉保持电路使用的晶体管和信号数量，可以减小电路的RC延迟，可以有效地降低电路的功耗，更加有效的降低液晶显示器的能耗。
综上所述，虽然本发明已以较佳实施例揭露如上，但该较佳实施例并非用以限制本发明，该领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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  1. 一种栅极驱动器，其包含：
    数个移位缓存单元，所述数个移位缓存单元系以串联的方式耦接，每一移位缓存单元用来依据第一时钟信号、第二时钟信号以及所述每一移位缓存单元的前一个移位缓存单元的驱动信号脉冲，在所述每一移位缓存单元的输出端输出输出信号脉冲，每一移位缓存单元包含：
    上拉电路，其包含第一晶体管，其栅极耦接于第一节点，源极耦接于第一时钟信号，漏极耦接于所述输出端，用来依据所述第一时钟信号，由所述输出端提供所述输出信号脉冲；
    下传电路，其包含第二晶体管，其栅极耦接于所述第一节点，源极耦接于第一时钟信号，漏极耦接于驱动信号端，用来依据所述第一时钟信号，由所述驱动信号端输出驱动信号脉冲；
    上拉控制电路，其包含第三晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的输出信号端，源极耦接于所述每一移位缓存单元的前一个移位缓存单元的驱动信号端，漏极耦接于所述第一节点，用来依据所述每一移位缓存单元的前一个移位缓存单元的所述驱动信号脉冲，导通所述上拉电路；
    上升电路，耦接于所述第一节点和所述输出端之间，用来抬升所述第一节点的电位；
    第一下拉保持电路，耦接于所述第一节点、所述第一时钟信号、第一固定电压以及第二固定电压，用来依据维持所述第一节点的低电平；
    第二下拉保持电路，耦接于所述第一节点、所述每一移位缓存单元的下两个移位缓存单元的驱动信号端、所述第一固定电压以及所述第二固定电压，用来依据所述每一移位缓存单元的下两个移位缓存单元的驱动信号，下拉所述第一节点的电位；以及
    下拉电路，耦接于所述第一固定电压、所述驱动信号端以及所述每一移位缓存单元的下一个移位缓存单元的驱动信号端，用来下拉所述第一节点的电位至所述第一固定电压。
  2. 如权利要求1所述的栅极驱动器，其中所述第一下拉保持电路包含：
    第四晶体管，其栅极耦接于所述第一时钟信号，源极耦接于第一时钟信号，漏极耦接于第二节点；
    第五晶体管，其栅极耦接于所述驱动信号端，源极耦接于所述第二节点，漏极耦接于所述第二电源电压；
    第六晶体管，其栅极耦接于所述每一移位缓存单元的前一个移位缓存单元的驱动信号端，源极耦接于所述第二节点，漏极耦接于所述第二电源电压；
    第七晶体管，其栅极耦接于所述第二时钟信号或是所述第二节点，源极耦接于所述第一时钟信号，漏极耦接于所述第二节点；
    第八晶体管，其栅极耦接于所述第二节点，源极耦接于所述输出端，漏极耦接于所述第一电源电压；
    第九晶体管，其栅极耦接于所述第二节点，源极耦接于所述第一节点，漏极耦接于所述第一电源电压；以及
    第十晶体管，其栅极耦接于所述第二节点，源极耦接于所述驱动信号端，漏极耦接于所述第二电源电压。
  3. 如权利要求1所述的栅极驱动器，其中所述第二下拉保持电路包含：
    第十一晶体管，其栅极耦接于所述每一移位缓存单元的下两个移位缓存单元的驱动信号端，源极耦接于所述第一节点，漏极耦接于所述第一电源电压。
  4. 如权利要求3所述的栅极驱动器，其中所述第二下拉保持电路另包含：
    第十二晶体管，其栅极耦接于所述每一移位缓存单元的下两个移位缓存单元的驱动信号端，源极耦接于所述输出端，漏极耦接于所述第一电源电压。
  5. 如权利要求1所述的栅极驱动器，其中所述下拉电路包含：
    第十三晶体管，其栅极耦接于所述每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于所述驱动信号端，漏极耦接于所述第二电源电压。
  6. 如权利要求5所述的栅极驱动器，其中所述下拉电路另包含：
    第十四晶体管，其栅极耦接于所述每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于所述输出端，漏极耦接于所述第一电源电压。
  7. 如权利要求6所述的栅极驱动器，其中所述下拉电路另包含：
    第十五晶体管，其栅极耦接于所述每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于所述第一节点，漏极耦接于所述第一电源电压。
  8. 如权利要求6所述的栅极驱动器，其中所述下拉电路另包含：
    第十五晶体管，其栅极耦接于所述每一移位缓存单元的下一个移位缓存单元的驱动信号端，源极耦接于所述第一节点；以及
    第十六晶体管，其栅极和源极皆耦接于所述第十五晶体管的漏极，漏极耦接于所述第一电源电压。
  9. 如权利要求1所述的栅极驱动器，其中所述上升电路是一电容。
  10. 如权利要求1所述的栅极驱动器，其中所述第一固定电压的电压大于所述第二固定电压。
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