[go: up one dir, main page]

WO2018120364A1 - Dispositif de commande de panneau d'affichage et procédé de commande - Google Patents

Dispositif de commande de panneau d'affichage et procédé de commande Download PDF

Info

Publication number
WO2018120364A1
WO2018120364A1 PCT/CN2017/073590 CN2017073590W WO2018120364A1 WO 2018120364 A1 WO2018120364 A1 WO 2018120364A1 CN 2017073590 W CN2017073590 W CN 2017073590W WO 2018120364 A1 WO2018120364 A1 WO 2018120364A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage signal
charging voltage
scan
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/073590
Other languages
English (en)
Chinese (zh)
Inventor
吴宇
王磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/519,538 priority Critical patent/US20180301108A1/en
Publication of WO2018120364A1 publication Critical patent/WO2018120364A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a driving device and a driving method for a display panel.
  • the data line driving circuit disposed in the display panel needs to extract a large current to fill the parasitic capacitance of the data line first.
  • the charging voltage is pulled down, so that the pixels of the first few rows of the positive polarity are not fully charged, and the brightness of the positive pixel points of the rows is dark.
  • the parasitic capacitance on the data line is full, the charging voltage output from the data line driving circuit is not pulled down so that the brightness of each pixel point remains normal.
  • FIG. 1 is a schematic diagram showing changes in charging voltage with time in an embodiment of the prior art
  • FIG. 2 is a schematic diagram showing luminance distribution of each pixel in an embodiment of the prior art.
  • the charging voltage V is pulled down, so that the first row, the second row, and the The luminance of the positive pixel points in the three rows of pixels is dark; in the charging cycle of the fourth row and subsequent rows of pixels, the charging voltage V is normal, and the brightness of each pixel in the fourth row and subsequent rows of pixels remains normal.
  • the technical problem to be solved by the present invention is to provide a driving device and a driving method for a display panel, which can improve the problem of uneven lighting of pixels in the display panel.
  • the present invention adopts a technical solution to provide a driving device for a display panel, the driving device comprising: a timing control circuit, configured to receive a current data frame and parse the current data frame to obtain a frame to be output.
  • the data line drive circuit is configured to: first charge the first charge voltage signal under the control of the precharge signal Outputting to each data line to pre-charge the parasitic capacitance of each data line, and outputting a second charging voltage signal to each data line to charge each pixel line line by line under the control of the scanning clock pulse signal; scan driving circuit And receiving a scan clock pulse signal to generate a line scan drive signal corresponding to each scan line and outputting to the scan line; wherein, the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse of the first charging voltage signal The width is greater than or equal to the pulse width of the second charging voltage signal.
  • the timing control circuit is further configured to parse the current data frame to obtain a pixel voltage signal corresponding to each pixel point; the data line driving circuit is configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line to perform a line scan.
  • the drive signal charges each pixel point by row and applies a corresponding pixel voltage.
  • the timing control circuit is further configured to generate a data clock pulse signal according to the frame open signal; the data line driving circuit is further configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • a driving device for a display panel comprising: a timing control circuit, configured to receive a current data frame and parse the current data frame to obtain a to-be-outputted a frame on signal, which generates a precharge signal and a scan clock pulse signal according to the frame enable signal, wherein the precharge signal is output before the scan clock pulse signal; and the data line drive circuit is configured to: first charge the first charge voltage under the control of the precharge signal The signal is output to each data line to precharge the parasitic capacitance of each data line, and then the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the driving device further comprises a scan driving circuit; the scan driving circuit is configured to receive the scan clock pulse signal to generate a line scan driving signal corresponding to each scan line and output to the scan line.
  • the timing control circuit is further configured to parse the current data frame to obtain a pixel voltage signal corresponding to each pixel point; the data line driving circuit is configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line to perform a line scan.
  • the drive signal charges each pixel point by row and applies a corresponding pixel voltage.
  • the timing control circuit is further configured to generate a data clock pulse signal according to the frame open signal; the data line driving circuit is further configured to sequentially output the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • a driving method of a display panel is provided.
  • the driving method is based on a timing control circuit, a scan driving circuit, and a data line driving circuit.
  • the driving method includes: receiving, by the timing control circuit, a current data frame and parsing the current data frame to obtain a frame to be output.
  • a signal a pre-charge signal and a scan clock pulse signal are generated by the timing control circuit according to the frame turn-on signal, wherein the pre-charge signal is output before the scan clock pulse signal; and the first charge voltage is controlled by the data line drive circuit under the control of the pre-charge signal
  • the signal is output to each data line to precharge the parasitic capacitance of each data line, and then the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the method further comprises: receiving, by the scan driving circuit, the scan clock pulse signal to generate a line scan drive signal corresponding to each scan line and outputting to the scan line.
  • the method further includes: parsing the current data frame by the timing control circuit to obtain a pixel voltage signal corresponding to each pixel; and outputting the second charging voltage signal to each data line by the data line driving circuit to control the scanning clock signal
  • the step of charging each pixel point row by row includes: sequentially outputting the second charging voltage signal and the pixel voltage signal to each data line by the data line driving circuit to charge each pixel point row by row by the line scanning driving signal Apply the corresponding pixel voltage.
  • the method further includes: generating, by the timing control circuit, the data clock pulse signal according to the frame open signal; and sequentially outputting, by the data line driving circuit, the second charging voltage signal and the pixel voltage signal to each data line, comprising: driving by the data line The circuit sequentially outputs the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • the invention has the beneficial effects that the driving device and the driving method of the display panel of the present invention are different from the prior art, and the first charging voltage signal is output to each data line under the control of the pre-charging signal to parasitize the data lines. After the capacitor is precharged, the second charging voltage signal is output to each data line to charge each pixel row by row under the control of the scanning clock pulse signal.
  • the present invention can improve the problem of uneven brightness of pixel points in the display panel due to the parasitic capacitance of the data lines.
  • FIG. 1 is a schematic diagram showing changes in charging voltage with time in an embodiment of the prior art
  • FIG. 2 is a schematic diagram of luminance distribution of each pixel in an embodiment of the prior art
  • FIG. 3 is a schematic structural view of a driving device of a display panel according to a first embodiment of the present invention
  • Figure 4 is a signal waveform diagram of the driving device shown in Figure 1 during operation
  • FIG. 5 is a schematic structural view of a driving device of a display panel according to a second embodiment of the present invention.
  • FIG. 6 is a flow chart showing a driving method of a display panel according to a first embodiment of the present invention.
  • Fig. 7 is a flow chart showing a driving method of a display panel according to a second embodiment of the present invention.
  • the driving device 100 includes a timing control circuit 10 and a data line driving circuit 11.
  • the timing control circuit 10 is configured to receive the current data frame and parse the current data frame to obtain a frame enable signal to be output, and generate a precharge signal and a scan clock pulse signal according to the frame open signal, wherein the precharge signal is output before the scan clock pulse signal .
  • the precharge signal is output prior to the frame enable signal, and the frame open signal is output prior to the scan clock pulse signal.
  • the precharge signal is valid, the frame turn-on signal is valid, and finally the scan clock pulse signal is valid.
  • the frame open signal may be output prior to the precharge signal, and the precharge signal is output prior to the scan clock pulse signal.
  • the data line driving circuit 11 is configured to output a first charging voltage signal to each data line under the control of the precharge signal to precharge the parasitic capacitance of each data line, and then output the second charging voltage signal to each data line.
  • Each pixel is charged line by line under the control of the scan clock signal.
  • FIG. 4 is a signal waveform diagram of the driving device shown in FIG. 3 during operation.
  • ST1 is a precharge signal
  • STV1 is a frame open signal
  • CKV1 is a scan clock pulse signal
  • TP is a signal applied to the data line, which includes a first charging voltage signal V1 and a second charging voltage signal V2. .
  • the precharge signal ST1 is output prior to the frame enable signal STV1, wherein after the precharge signal ST1 is asserted, the signal TP applied to each data line is the first charge voltage signal V1.
  • the first charging voltage signal V1 applied to the data line does not charge each pixel point, and directly charges the parasitic capacitance on the data line. .
  • the first charging voltage signal V1 is a single-pulse signal of a positive voltage, and the pulse width thereof corresponds to the magnitude of the parasitic capacitance on the data line. Specifically, when the parasitic capacitance is large, the positive voltage in the first charging voltage signal V1 lasts for a long time; when the parasitic capacitance is small, the positive voltage in the first charging voltage signal V1 lasts for a short time.
  • each data line is the second charge voltage signal V2 to row each pixel point under the control of the scan clock pulse signal CKV1. Charge it. That is, in each pulse period of the scan clock signal CKV1, each data line is correspondingly applied with a second charging voltage signal V2 to charge a pixel of a certain row.
  • the pulse width of the first charging voltage signal V1 is equal to the pulse width of the second charging voltage signal V2, and the time interval of the first charging voltage signal V1 and the adjacent second charging voltage signal V2 is equal to two adjacent ones.
  • the first charging voltage signal V1 is a signal extending forward of the repeatedly arranged second charging voltage V2.
  • the pulse width of the first charging voltage signal V1 may also be greater than the pulse width of the second charging voltage signal V2, and the time interval of the first charging voltage signal V1 and the adjacent second charging voltage signal V2 may also be based on The actual situation is set as long as it satisfies the parasitic capacitance that the first charging voltage signal V1 can fill the respective data lines.
  • Fig. 5 is a schematic structural view of a driving device of a display panel according to a second embodiment of the present invention.
  • each pixel 210 includes a pixel FET T and a capacitor unit A (or a pixel electrode); the pixel FET T has a gate (G), a source (S) and a drain (D);
  • the unit A includes a parallel liquid crystal capacitor Clc (or a pixel capacitor, a liquid crystal pixel) and a storage capacitor Cs, one end of which is connected to the drain (D), and the other end is connected to a common voltage (Vcom); and is disposed in the pixel 210 of the same row.
  • the gate (G) of the pixel FET T is connected to the scan line Xm of the row.
  • the source (S) of the pixel FET T is connected to the corresponding data line Ym in the pixel 210 of the same column. .
  • the driving device 300 includes a timing control circuit 30, a data line driving circuit 31, and a scan driving circuit 32.
  • the data line driving circuit 31 is connected to the plurality of columns of data lines Ym
  • the scanning driving circuit 32 is connected to the plurality of rows of scanning lines Xm.
  • the timing control circuit 30 is configured to receive the current data frame and parse the current data frame to obtain a frame open signal to be output and a pixel voltage signal corresponding to each pixel point, and generate a precharge signal ST2, a scan clock pulse signal CKV2, and data according to the frame open signal. Clock pulse signal CKL2.
  • the data line driving circuit 31 is connected to the timing control circuit 30 for outputting the first charging voltage signal to each data line Ym under the control of the precharge signal ST2 to precharge the parasitic capacitance of each data line Ym, in the data.
  • the second charging voltage signal and the pixel voltage signal are sequentially output to the respective data lines Ym under the control of the clock pulse signal CKL2 to row-by-row the drains of the respective pixel points by the row scanning driving signal Gm.
  • D or the capacitor unit A performs charging and applies a corresponding pixel voltage, thereby realizing display of the current data frame.
  • the precharge signal ST2 is output prior to the scan clock pulse signal CKV2. That is, when the precharge signal ST2 is valid, the scan clock pulse signal CKV2 is still in an inactive state. At this time, the gate (G) of each pixel is in a closed state, and the first charging voltage signal is output to each data line Ym. The parasitic capacitance of each data line Ym is charged.
  • the scan drive circuit 32 applies the level of the row scan drive signal Gm on a certain row of scan lines Xm such that the gate of the pixel point 210 of the row (G) Turning on or off, when turned on, receiving the second charging voltage signal and the pixel voltage signal applied on the data line Ym of the row of pixel points 210 by the data line driving circuit 31 under the control of the data clock pulse signal CKL, so as to make a drain pole (D) or the charging and receiving of the capacitor unit A needs to display the pixel voltage corresponding to the gray scale, so that the pixel point 210 of the row is driven by the voltage on the scanning line Xm and the data line Ym to display an image image corresponding to the gray scale,
  • the scan line Xm is turned on line by line, the normal display of the picture is realized by writing the second charging voltage through the data line Ym and the pixel voltage corresponding to the gray scale.
  • the first charging voltage signal and the second charging voltage signal are pulse signals, and a pulse width of the first charging voltage signal is greater than or equal to a pulse width of the second charging voltage signal. That is, each data line is charged with the first charging voltage signal for a time longer than or equal to the time at which the same row of pixels is charged with the second charging voltage signal.
  • the voltage values of the first charging voltage signal and the second charging voltage signal are the same. In other embodiments, the magnitudes of the voltage values of the first charging voltage signal and the second charging voltage signal may also be different.
  • Fig. 6 is a flow chart showing a driving method of the display panel according to the first embodiment of the present invention, which is based on the driving device shown in Fig. 3. It should be noted that the method of the present invention is not limited to the sequence of processes shown in FIG. 6 if substantially the same result is obtained. As shown in FIG. 6, the method includes the steps of:
  • Step S101 The current data frame is received by the timing control circuit and the current data frame is parsed to obtain a frame open signal to be output.
  • Step S102 The pre-charge signal and the scan clock pulse signal are generated by the timing control circuit according to the frame turn-on signal.
  • step S102 the precharge signal is output prior to the scan clock pulse signal.
  • Step S103 The data line driving circuit outputs the first charging voltage signal to each data line under the control of the pre-charging signal to pre-charge the parasitic capacitance of each data line, and then outputs the second charging voltage signal to each data line.
  • Each pixel point is charged line by line under the control of the scan clock pulse signal.
  • Fig. 7 is a flowchart of a driving method of a display panel according to a second embodiment of the present invention, which is based on the driving device shown in Fig. 5. It should be noted that the method of the present invention is not limited to the sequence of processes shown in FIG. 7 if substantially the same result is obtained. As shown in Figure 7, the method includes the steps of:
  • Step S201 The current data frame is received by the timing control circuit and the current data frame is parsed to obtain a frame open signal to be output and a pixel voltage signal corresponding to each pixel.
  • Step S202 The pre-charge signal, the scan clock pulse signal and the data clock pulse signal are generated by the timing control circuit according to the frame turn-on signal.
  • step S202 the precharge signal is output prior to the scan clock pulse signal. Specifically, the precharge signal is output prior to the frame enable signal, and the frame open signal is output prior to the scan clock pulse signal.
  • Step S203 The data line driving circuit outputs a first charging voltage signal to each data line under the control of the precharge signal to precharge the parasitic capacitance of each data line.
  • step S203 when the precharge signal is output before the scan clock pulse signal, so that each data line of the display panel is applied with the first charging voltage signal, the pixel FET in the pixel cannot be turned on because the scan clock pulse signal is invalid. Therefore, the first charging voltage signal does not charge each pixel point and directly charges the parasitic capacitance on the data line.
  • Step S204 The scan clock signal is received by the scan driving circuit to generate a line scan drive signal corresponding to each scan line and output to the scan line.
  • Step S205 The data line driving circuit sequentially outputs the second charging voltage signal and the pixel voltage signal to each data line under the control of the data clock pulse signal, so as to charge and apply corresponding pixels to each pixel row by row scanning driving signal.
  • the pixel voltage The pixel voltage.
  • step S205 the first charging voltage signal and the second charging voltage signal are pulse signals, and the pulse width of the first charging voltage signal is greater than or equal to the pulse width of the second charging voltage signal.
  • the invention has the beneficial effects that the driving device and the driving method of the display panel of the present invention are different from the prior art, and the first charging voltage signal is output to each data line under the control of the pre-charging signal before displaying the current data frame. Precharging the parasitic capacitance of each data line; in the process of displaying the current data frame, outputting the second charging voltage signal and the pixel voltage signal to each data line to row-by-row each pixel under the control of the scanning clock pulse signal The point is charged and the pixel voltage is applied.
  • the present invention can improve the problem of uneven brightness of pixel points in the display panel due to the parasitic capacitance of the data lines.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un dispositif de commande (100) de panneau d'affichage et un procédé de commande. Le dispositif de commande (100) comprend : un circuit de commande de temporisation (10), permettant de recevoir une trame de données en cours, d'analyser la trame de données en cours afin d'obtenir un signal d'activation de trame (STV1) à émettre et de générer un signal électrique de précharge (ST1) et un signal d'impulsion d'horloge de balayage (CKV1) en fonction du signal d'activation de trame (STV1), le signal électrique de précharge (ST1) étant émis avant le signal d'impulsion d'horloge de balayage (CKV1) ; et un circuit de commande de ligne de données (11), commandé par le signal électrique de précharge (ST1) permettant d'émettre en sortie un premier signal de tension de charge (V1) vers chaque ligne de données afin de précharger un condensateur parasite de chaque ligne de données, puis d'émettre en sortie un second signal de tension (V2) vers chaque ligne de données afin de charger, sous la commande du signal d'impulsion d'horloge de balayage (CKV1), chaque pixel ligne par ligne. Le dispositif de commande et le procédé de l'invention permettant d'atténuer le problème selon lequel des condensateurs parasites de lignes de données provoquent une irrégularité de luminosité des pixels d'un panneau d'affichage.
PCT/CN2017/073590 2016-12-28 2017-02-15 Dispositif de commande de panneau d'affichage et procédé de commande Ceased WO2018120364A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/519,538 US20180301108A1 (en) 2016-12-28 2017-02-15 Driving devices of display panels and driving method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611236662.4 2016-12-28
CN201611236662.4A CN106782381B (zh) 2016-12-28 2016-12-28 一种显示面板的驱动装置及驱动方法

Publications (1)

Publication Number Publication Date
WO2018120364A1 true WO2018120364A1 (fr) 2018-07-05

Family

ID=58924937

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/073590 Ceased WO2018120364A1 (fr) 2016-12-28 2017-02-15 Dispositif de commande de panneau d'affichage et procédé de commande

Country Status (3)

Country Link
US (1) US20180301108A1 (fr)
CN (1) CN106782381B (fr)
WO (1) WO2018120364A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109192176A (zh) * 2018-11-05 2019-01-11 重庆先进光电显示技术研究院 显示驱动方法以及驱动装置、显示装置
CN109410862A (zh) * 2018-11-26 2019-03-01 惠科股份有限公司 液晶像素的充电方法、显示面板及存储介质
CN110322827B (zh) * 2019-08-15 2022-05-10 成都辰显光电有限公司 一种显示面板的数字驱动方法和显示面板
CN111681582B (zh) * 2020-06-02 2021-08-24 Tcl华星光电技术有限公司 扫描驱动方法、扫描驱动装置、电子设备及存储介质
TWI746153B (zh) * 2020-06-18 2021-11-11 聯詠科技股份有限公司 發光二極體驅動器及其預充電方法
CN113450701A (zh) * 2020-07-22 2021-09-28 重庆康佳光电技术研究院有限公司 数据线控制方法及装置、数据线驱动装置、显示装置
CN117116196B (zh) * 2023-09-07 2024-07-19 重庆惠科金渝光电科技有限公司 显示补偿方法和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1372241A (zh) * 2001-02-26 2002-10-02 三星电子株式会社 液晶显示器及其驱动方法
CN1614672A (zh) * 2003-10-31 2005-05-11 三星Sdi株式会社 图像显示设备及其驱动方法
CN1693942A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 液晶显示器及其预充电方法
JP2005331983A (ja) * 1998-01-23 2005-12-02 Seiko Epson Corp 電気光学装置及び電子機器並びに電気光学装置の駆動方法
CN101051125A (zh) * 2006-04-07 2007-10-10 群康科技(深圳)有限公司 液晶显示面板及其驱动电路与驱动方法
CN102063878A (zh) * 2009-11-17 2011-05-18 群康科技(深圳)有限公司 液晶显示装置
CN105702213A (zh) * 2016-03-22 2016-06-22 北京大学深圳研究生院 显示装置及其显示驱动器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010030511A1 (en) * 2000-04-18 2001-10-18 Shunpei Yamazaki Display device
JP4385730B2 (ja) * 2003-11-13 2009-12-16 セイコーエプソン株式会社 電気光学装置の駆動方法、電気光学装置および電子機器
JP2008122747A (ja) * 2006-11-14 2008-05-29 Seiko Epson Corp 電気光学装置用駆動回路、電気光学装置の駆動方法、電気光学装置、及び電子機器
JP5151130B2 (ja) * 2006-12-07 2013-02-27 セイコーエプソン株式会社 電気光学装置、駆動方法および電子機器
JP5562695B2 (ja) * 2010-03-23 2014-07-30 株式会社ジャパンディスプレイ 液晶表示装置
CN202003648U (zh) * 2011-01-28 2011-10-05 深圳华映显示科技有限公司 一种具有预充功能的像素结构
JP6611494B2 (ja) * 2015-07-08 2019-11-27 キヤノン株式会社 画像表示装置及びその制御方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005331983A (ja) * 1998-01-23 2005-12-02 Seiko Epson Corp 電気光学装置及び電子機器並びに電気光学装置の駆動方法
CN1372241A (zh) * 2001-02-26 2002-10-02 三星电子株式会社 液晶显示器及其驱动方法
CN1614672A (zh) * 2003-10-31 2005-05-11 三星Sdi株式会社 图像显示设备及其驱动方法
CN1693942A (zh) * 2004-04-30 2005-11-09 Lg.菲利浦Lcd株式会社 液晶显示器及其预充电方法
CN101051125A (zh) * 2006-04-07 2007-10-10 群康科技(深圳)有限公司 液晶显示面板及其驱动电路与驱动方法
CN102063878A (zh) * 2009-11-17 2011-05-18 群康科技(深圳)有限公司 液晶显示装置
CN105702213A (zh) * 2016-03-22 2016-06-22 北京大学深圳研究生院 显示装置及其显示驱动器

Also Published As

Publication number Publication date
CN106782381A (zh) 2017-05-31
CN106782381B (zh) 2019-09-20
US20180301108A1 (en) 2018-10-18

Similar Documents

Publication Publication Date Title
WO2018120364A1 (fr) Dispositif de commande de panneau d'affichage et procédé de commande
US7817126B2 (en) Liquid crystal display device and method of driving the same
US10255840B2 (en) Display panel, driving method for display panel, and display device
WO2016108462A1 (fr) Dispositif d'affichage flexible pourvu d'un circuit de type « gate-in-panel »
WO2015165124A1 (fr) Circuit d'attaque de grille pour afficheur à cristaux liquides à cadre étroit
US20120019497A1 (en) Liquid crystal display and method of driving the same
WO2018218718A1 (fr) Unité de registre à décalage bidirectionnel, registre à décalage bidirectionnel et panneau d'affichage
WO2018035995A1 (fr) Circuit de commande de balayage
WO2017008499A1 (fr) Circuit de pilotage de grille, appareil d'affichage à commande tactile et procédé de pilotage de dispositif d'affichage à commande tactile
KR20080006037A (ko) 시프트 레지스터, 이를 포함하는 표시 장치, 시프트레지스터의 구동 방법 및 표시 장치의 구동 방법
WO2015021660A1 (fr) Substrat de réseau et dispositif d'affichage à cristaux liquides
WO2018072304A1 (fr) Circuit d'attaque goa et dispositif d'affichage à cristaux liquides
CN101587271A (zh) 液晶显示器设备
KR102104329B1 (ko) 게이트 구동 모듈, 이를 포함하는 표시 장치 및 이를 이용한 표시 패널의 구동 방법
WO2016011684A1 (fr) Circuit de commande d'affichage et procédé de commande d'affichage pour afficheur à cristaux liquides
WO2020119557A1 (fr) Procédé de commande d'affichage et dispositif d'affichage
CN110211547A (zh) 一种显示面板、其驱动方法及显示装置
WO2017054264A1 (fr) Circuit goa et dispositif d'affichage à cristaux liquides
WO2017080082A1 (fr) Dispositif d'affichage à cristaux liquides et circuit goa
WO2020093419A1 (fr) Procédé d'activation d'affichage, appareil d'activation d'affichage et appareil d'affichage
WO2019161682A1 (fr) Substrat de réseau et dispositif d'affichage
WO2018023859A1 (fr) Circuit d'excitation de balayage et appareil d'affichage à panneau plat muni dudit circuit
WO2017024622A1 (fr) Dispositif d'affichage à cristaux liquides et son procédé de commande
WO2017020333A1 (fr) Afficheur à cristaux liquides et procédé de commande associé
WO2017177491A1 (fr) Circuit de dispositif d'affichage à cristaux liquides et procédé de commande de dispositif d'affichage à cristaux liquides

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15519538

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17887158

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17887158

Country of ref document: EP

Kind code of ref document: A1