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WO2012115519A2 - Cellule solaire et procédé de fabrication d'une telle cellule solaire - Google Patents

Cellule solaire et procédé de fabrication d'une telle cellule solaire Download PDF

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Publication number
WO2012115519A2
WO2012115519A2 PCT/NL2012/050114 NL2012050114W WO2012115519A2 WO 2012115519 A2 WO2012115519 A2 WO 2012115519A2 NL 2012050114 W NL2012050114 W NL 2012050114W WO 2012115519 A2 WO2012115519 A2 WO 2012115519A2
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WIPO (PCT)
Prior art keywords
front surface
layer
conductivity type
textured
solar cell
Prior art date
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PCT/NL2012/050114
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WO2012115519A3 (fr
Inventor
Lambert Johan Geerligs
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Energy Research Centre of the Netherlands
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Energy Research Centre of the Netherlands
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Publication of WO2012115519A2 publication Critical patent/WO2012115519A2/fr
Publication of WO2012115519A3 publication Critical patent/WO2012115519A3/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • H10F77/703—Surface textures, e.g. pyramid structures of the semiconductor bodies, e.g. textured active layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/129—Passivating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H10F77/315—Coatings for devices having potential barriers for photovoltaic cells the coatings being antireflective or having enhancing optical properties
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell which comprises a semiconductor substrate, e.g. a silicon substrate. Also, the present invention relates to a method for manufacturing such a solar cell.
  • High efficiency silicon solar cells based on silicon wafers typically have a diffused emitter on the front side (the side turned towards the sun) or a diffused front surface field (FSF) layer on the front side, instead of an emitter and often also diffused back surface field (BSF) or an emitter on the back surface.
  • FSF diffused front surface field
  • BSF diffused back surface field
  • one side of the wafer can be nearly totally covered with emitter layer, and the other side nearly totally covered with a BSF layer.
  • the diffused emitter serves to define a p-n junction where the light-generated charge carriers are separated.
  • These BSF/FSF layers serve the purpose of providing good contact with electrodes on the surface and/or reduce the recombination of the charge carriers at the surface of the wafer (i.e., enhance the surface passivation).
  • the surfaces of high efficiency silicon solar cells based on silicon wafers are preferably passivated to reduce efficiency loss due to recombination of free charge carriers at these surfaces.
  • the FSF/BSF layers provide or enhance surface passivation.
  • a coating with dielectric layers, such as a silicon nitride provides for passivation.
  • dielectric coatings that can perform surface passivation on a diffused layer include silicon nitride, thermally grown oxide, a stack of deposited silicon oxide and silicon nitride, aluminum oxide, silicon carbide, a stack of a wet-chemically grown silicon oxide and silicon nitride.
  • Various passivation techniques are compared in an article by Altermatt et al. titled "The surface recombination velocity at Boron-doped emitters:
  • a silicon oxide layer was grown in dry 02 at 1100 °C for 30 min and then annealed in N2 at 1100 °C for 30 min and FG at 400 °C for 30 min. Rounding of the texture was used to facilitate measurements.
  • Chen investigated various possible explanations for the reduced passivation by measuring the effect of rounding the textured surface on recombination lifetime of an undiffused substrate. Rounding was used to reduce stress. A reduction of the open circuit voltage showed that that stress induced by silicon nitride on the textured surface played a role, but the exposure of the 111 crystal surface in the texture also played a role.
  • US 6,207,890 discloses use of a textured surface in a hetero-junction solar cell (i.e. a solar cell with a deposited emitter layer of a certain semiconductor, such as amorphous silicon, on the textured surface of the semi-conductor substrate of a different kind of semiconductor, such as crystalline silicon, rather than a diffused emitter layer in the semi-conductor substrate).
  • a certain rounding to a random pyramid texture particularly a slight rounding (increasing the radius of curvature) of the valleys between pyramids, enhances the passivation obtained by subsequent deposition of amorphous or microcrystalline silicon layers.
  • the improved passivation is explained as due to a more uniform coverage of the wafer by the thin film.
  • a similar teaching is found in WO 2010/023318, with as explanation that the benefit of rounding of the valleys between pyramids for the passivation by an amorphous silicon layer is due to the suppression of epitaxial growth of silicon.
  • WO2010/105703 similarly discloses the use of a plasma etching step that creates a texture, but that also results in surface damage due to ion
  • the document teaches removal of the plasma induced damage by a smoothing etch.
  • the document proposes various remedies to reduce this type of stress, including the use of an isotropic etch to increase the radius of curvature of the peaks and troughs.
  • the different remedies were evaluated on solar cells that were manufactured by texturing using an anisotropic etch, followed by deposition of a phosphorous oxide layer on the semiconductor surface from which phosphor doping was thermally diffused into the semiconductor surface to form p-n junctions. These junctions provide for passivation. After deposition of the phosphorous oxide layer the samples were subjected to oxidation cycles.
  • the effect of the isotropic etch was evaluated by a applying a rounding etch to the texture.
  • the document discloses that the diffusion based junctions increase passivation, the document does not disclose the use of an added passivation layer on the semiconductor surface after the diffusion step. In processes wherein a passivation layer is realized by deposition or wet- chemical processing no thick oxide and associated volume expansion is formed.
  • WO2009/120631 discloses a surface cleaning and texturing process for crystalline solar cells.
  • the document illustrates this using a process wherein amorphous and/or crystalline silicon layers are deposited on a textured surface, or a passivation layer.
  • the document mentions the possibility of using a post etch texture smoothing step to round or soften edges of the texture before deposition of one or more layers on the textured surface.
  • this step is used to prevent the cracking and other types of mechanical failure in the subsequently deposited layers , such as a passivation layer or junction forming layer, by smoothing the sharp edges and points of the formed texture. Epitaxial growth in the heterojunction layer could give rise to cracking and other types of mechanical failure.
  • WO 2010/023318 discloses a method of limiting epitaxial growth in a photoelectric device with heterojunctions.
  • the document discloses a process wherein first a texture is created followed by deposition of an amorphous doped semiconductor layer to form a semi-conductor junction between the deposited layer and the underlying substrate.
  • the document discloses that the deposited doped semiconductor layer may be insufficiently thick in the valleys of the texture, but that this can be addressed by using an isotropic etch to round off the valleys before one or more layers are deposited on the textured surface.
  • no heterojunction is formed.
  • a method according to claim 1 is provided.
  • the front surface of the semiconductor substrate is provided with a texture and partly smoothened before creation of the front emitter or a surface field layer of the solar cell by diffusion into the semi-conductor substrate and any other diffusion or application of material to provide for the contacts to the solar cell. Because diffusion is used, no heterojunction needs to be used.
  • the partly smoothened surface is covered by a passivating layer created by deposition or wet-chemical processing, so that no thick oxide need arise.
  • the partial smoothening is not performed as a side effect together with removal of parasitic doping from the textured front surface, because it takes place at a stage at which no parasitic doping is present, due to the fact that no diffusion is applied to the back surface before partial smoothening.
  • the textured front surface has planar facets at oblique angles to an average planar direction of the front surface, said partial smoothening comprising rounding valleys between pairs of adjacent facets, while preserving facet planes oriented parallel to the original facets.
  • the preservation of facets provides for less reflectivity. It has been found that rounding of the valleys improves passivation a least when combined diffusion of dopant into the front surface and application of a passivation layer. The net effect increases energy efficiency of the solar cell.
  • the textured front surface includes pyramidal shapes, said partly smoothening comprising broadening intermediate valleys between the pyramidal shapes without removing the pyramidal shapes altogether.
  • the partial smoothening process may substantially retain the texture of the textured front surface.
  • the partial smoothening is especially performed by a (light) polishing. This may reduce cost and process time, while at the same time being very effective in improving passivation.
  • the partial smoothening is preferably very light to avoid increasing reflectance by an unacceptable amount, e.g. by more than 2 or 3 percentage points at a wavelength of 1000 nm (relative to the non-smoothened textured surface), for instance from 11% reflectance to 13 % reflectance.
  • the creation of texture comprises creation of a pyramid texture, for instance a random pyramid structure or an inverted pyramid texture.
  • an isotropic texture may be created.
  • the creation of texture comprises creation of random pyramid texture by etching in an alkaline solution.
  • texturing the front surface may include creating a pyramidal shapes containing front surface.
  • the pyramidal shapes may include a pyramid structure, such as a random pyramid structure.
  • the average height of the texture feature on the textured front surface is at least about 2 micron.
  • the partial smoothening includes broadening intermediate valleys between pyramidal shapes to provide valleys with widths selected from the range of 50-2000 nm. In an embodiment the partial smoothening includes rounding intermediate valleys between pyramidal shapes to provide valleys with curvatures having radii of curvature within the range of 50-1000 nm. Valley curvature in this range improves passivation compared to "natural" angles between facets after texturing without smoothening.
  • Partial smoothening may be performed by etching with an oxidator and a dissolving agent containing liquid.
  • An example for an oxidizing agent is nitric acid and for the dissolving aqueous HF can be used.
  • the partial smoothening may for instance result in removing away a layer of average thickness of about 50 nm - 2 pm. This average thickness removed may for instance be
  • the etching process adapted for retaining texture of the textured front surface is performed by a dry etching method.
  • the etching agent comprises a component for texturing a semiconductor surface.
  • the etching agent further comprises a component for polishing the semiconductor surface.
  • the emitter is created in the semi-conductor substrate adjacent the partly smoothened textured surface before application of the passivating layer to that surface.
  • the method as described above comprises creating the layer of the first conductivity type on the textured front surface by diffusion of dopant of the first conductivity type, which comprises exposing the textured front surface to a precursor of the first conductivity type at elevated temperature.
  • the precursor of the first conductivity type is a gaseous precursor, the gaseous precursor containing the dopant of the first conductivity type.
  • the first conductivity type may be n-type or p-type.
  • a passivation layer such as selected from the group consisting of silicon nitride, silicon oxide (not a thermally grown silicon oxide), silicon carbide, and aluminum oxide, and optionally other materials, on one or both doped layers.
  • the passivation layer is created by one or more of the following techniques plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, sputtering, atomic layer deposition, wet chemical oxidation.
  • the improved surface passivation may especially be obtained with a dielectric coating, for example silicon nitride deposited by PECVD (plasma enhanced chemical vapor deposition), or a stack of wet chemically grown silicon oxide with (PECVD) silicon nitride, or aluminum oxide, stacks of these or other deposited dielectrics, etc.
  • PECVD plasma enhanced chemical vapor deposition
  • PECVD wet chemically grown silicon oxide with
  • the method may comprise creating emitter and base contacts on the back surface, or alternatively, an emitter on the back surface and base contacts on the front surface.
  • a passivation layer may be applied to the back surface, openings may be formed selectively in the passivation layer, for diffusing doping material into the substrate through the openings.
  • a doped glass may be applied to the back surface to act as a source of doping material through the openings.
  • Different sets of openings may be created successively and doped glass of mutually opposite conductivity types may be applied through the different sets of openings, using temporary dope galss layers of mutually opposite conductivity types.
  • diffused regions of the first as well as second conductivity type may be created selectively in the semi-conductor substrate adjacent the back surface before the application of electrodes.
  • electrodes may be created by applying e.g. by screen printing an Al-layer or Al-pattern on the back surface, drying and "firing" (a high temperature annealing step).
  • the doped surface is coated by deposition of a dielectric coating such as silicon nitride, silicon carbide, silicon oxide (not a thermally grown silicon oxide), aluminum oxide, etc. by plasma enhanced chemical vapor deposition, sputtering, atomic layer deposition, etc., or a stack of such layers, optionally in combination with first growing a thin silicon oxide by wet-chemical means.
  • a dielectric coating such as silicon nitride, silicon carbide, silicon oxide (not a thermally grown silicon oxide), aluminum oxide, etc.
  • plasma enhanced chemical vapor deposition, sputtering, atomic layer deposition, etc., or a stack of such layers optionally in combination with first growing a thin silicon oxide by wet-chemical means.
  • Such coating may especially improve passivation, especially in combination with the partly smoothened texture.
  • the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, even more especially 99.5% or higher, including 100%.
  • the term “comprise” includes also embodiments wherein the term “comprises” means "consists of .
  • Figure 1 shows a flow diagram for a method for manufacturing a solar cell in accordance with a first aspect
  • Figure 2 shows a flow diagram for a method for manufacturing a solar cell in accordance with a second aspect
  • Figure 3 shows a flow diagram for a method for manufacturing a solar cell in accordance with a third aspect
  • Figure 4 shows a cross-section of a semiconductor substrate for manufacturing the solar cell
  • Figure 5 show a cross-section of the solar cell after front surface texturing
  • Figure 6 shows a cross-section of the solar cell after partial smoothening
  • Figure 7 shows a cross-section of the solar cell after front diffusion
  • Figure 8 shows a cross-section of the solar cell after front surface passivation
  • Figure 9-10 show cross-sections of the solar cell after printing back surface contacts
  • Figure 10a illustrates the result of annealing
  • Figure 11 shows a cross-section of the solar cell after back surface passivation
  • Figure 12 shows a cross-section of the solar cell after back surface diffusion
  • Figure 13a shows in a surface texture in some detail
  • Figure 13b shows interpretation of valley width and curvature
  • Figures 14a- 14d show SEM figures o f non-smoothened (14a- 14b) and smoothened (14c- 14d) pyramidal textures.
  • the surfaces of the semi-conductor substrate of a solar cell are mutually parallel surfaces, including a surface that will face the sun, or other light source from which energy is collected.
  • a textured surface is a surface is a substantially planar surface that defines an average main surface plane, textured surface having local height variations in a direction perpendicular to the main plane, so that the surface has facets directed in mutually different directions at an angle to the main plane (i.e. an angle greater than zero and less than a perpendicular angle, for example in a range from 10-80 degrees, the area of each facet being much smaller than the overall area of the planar surface (e.g. less than 0.01 of the area of the planar surface).
  • regions and/or layers of the semic-conductor substrate adjacent a surface are regions and/or layers that extend over part of the height of the semi-conductor substrate between the surfaces and end at or nearly at the surface to which they are adjacent, and at least end closer to that surface than to the other surface.
  • smoothening, smoothing and polishing of the texture means that substantially the entire surface is processed with the effect that at least part of the connections between the facets are rounded, i.e. that the surface normal is made to vary more slowly at the transition from one facet to another.
  • partly (or partial) smoothening, smoothing and polishing of the texture means that the process of smoothening, smoothing or polishing is not performed to such a degree that the surface becomes planar, and/or that the original facets cannot be distinguished any more.
  • Smoothening, smoothing and polishing of the texture are termed partly (or partial) smoothening, smoothing and polishing in thuis sense also if the entire surface is smoothened or polished.
  • FIG. 1 shows a flow diagram for a method for manufacturing a solar cell in accordance with a first aspect.
  • the method comprises a sequence 100 of processes to manufacture a solar cell with either p- or n-type base.
  • the sequence 100 is illustrated for a solar cell with p- type base.
  • the silicon substrate is doped to have a conductivity of n-type.
  • Figure 4 shows a cross-section of a single crystal semiconductor substrate i.e., a silicon substrate 1 with p-type conductivity is provided as precursor for the solar cell.
  • the silicon substrate has a front surface 2 and a back surface 3.
  • the front surface will be the surface for receiving light during use of the solar cell.
  • the description of the method focuses on processes that affect the front surface of the solar cell. For the sake of clarity effects on the back surface will not be shown.
  • the back surface need not be affected by processing of the front surface.
  • one or more of the processes for processing of the front surface may be performed in a double sided manner, affecting the back surface, and provide similar benefits.
  • the method provides texturing of at least the front surfaces 2 of the silicon substrate 1 by exposing the surface(s) to be textured to a texture etching agent.
  • the front surface 2 is textured to create a surface topography (also referred to as texture features) resulting in a low reflectivity of the surface.
  • the texturing recipe can be tuned to obtain as texture features large pyramids on the surface (e.g. an average pyramid height of about 2 microns or more).
  • the texturing process may be adjusted to maintain a low reflectivity after a later removal step of a doped surface layer.
  • the back surface 3 may also be textured to create a surface topography (also referred to as texture features) resulting in a low reflectivity of the surface or polished to create a surface topography resulting in a high reflectivity.
  • the textured surface of the back surface 3 does not have to be identical to the textured front surface 2.
  • the back surface 3 may be polished in a single side polishing etching step to remove the texture, and to improve optical and passivation properties.
  • the texturing may be combined with an etching process for saw damage removal. Combining saw damage removal and texturing may be advantageous for silicon substrates that have not been pre- polished after slicing from a silicon ingot. Alternatively, the texturing process 102 may also be preceded by such an etching process for saw damage removal. After texturing process 102, a partial polishing process 102a is performed. Figure 5 shows a cross-section of the solar cell after creation of texture.
  • the texture is created by exposing the surface(s) to be textured to a texture etching agent.
  • a texturing agent may be an alkaline or acid solution, but it could also be a plasma for dry etching.
  • Figure 5 shows a cross-section of the solar cell after creation of texture on the front surface 2 (although not shown the back surface may be textured as well).
  • Figure 6 shows an embodiment after a process 102a, i.e. a partial
  • an etching of the front surface 2 may be performed.
  • the etching agent is arranged to retain a texture of the front surface so as to maintain a low reflectivity of the textured front surface.
  • a polishing component of an acidic etching agent comprises an oxidizing component for creating an oxidized surface layer and an oxide etchant for etching the oxidized surface layer.
  • the oxidizing component is nitric acid (HN03) and the oxide etchant is fluoric acid (HF).
  • the oxidizing component also comprises additives like water or acetic acid. A partial smoothening may for instance be performed by exposing the textured surface to such polishing component for 0.5-5 minutes.
  • the ratio between HN03 and HF components may for example be in the range of 50: 1 to 3: 1.
  • the etching may be performed as a single- side etch, that is, an etching process wherein the etching liquid is brought in contact with one of the front or back surface, but not the other surface or only a very minor edge region of the other surface.
  • Alternative forms of smoothening may involve replacing the oxidising agent HN03, by another oxidizing agent, such as for example H202, Cr207,
  • KMn207, etcetera Alternative forms of smoothening may involve replacing the oxide etchant HF by another oxide etchant, for example, NH4F, buffered HF, etc.
  • oxide etchant HF by another oxide etchant
  • HN03/HF-type chemistries are alkaline chemistries, such as for example KOH, NaOH, Na2C03, Na3P04, TMAH, organic alkaline agents, etc.
  • TMAH TMAH
  • organic alkaline agents etc.
  • etching can be done by a dry plasma etching step, comprising for example CF4 or SF6. Experimentally it is verified by
  • the method provides the creation of an n-type (emitter) layer 6 in the silicon substrate adjacent the textured front surface, after partial smoothing.
  • Figure 7 shows a cross-section of the solar cell after process 106.
  • the textured front surface is exposed at elevated temperature to an n-type dopant.
  • the n-type dopant is for example phospor.
  • the n-type dopant may be a gaseous n-type precursor, for example a phosphor containing gas.
  • the elevated temperature may be any suitable elevated temperature suitable for the specific diffusion process being applied for instance depending on the materials that are used.
  • the elevated temperature may also depend on the time during which the elevated temperature is applied. In general the elevated temperature may be between about 700 and about 1200 °C, or between about 780 - 1100 °C.
  • a dopant containing glassy layer is formed on the textured front surface.
  • the method provides the creation of an n- type (emitter) layer by diffusion in the textured front surface.
  • the textured front surface is exposed to an n-type dopant, for example phosphor.
  • the n-type dopant may be supplied in a dopant containing gas.
  • a dopant containing glassy layer is formed on the textured front surface.
  • the layer may also be formed on the back surface
  • the creation of the p-type layer 6 may be done by various diffusion methods, e.g. tube or belt furnace, and diffusion sources, e.g. boric acid containing liquids, applied by spray, vapor, spinning, printing, chemical vapur deposition, etc., or implantation.
  • the method provides a silicon substrate which comprises a p- type emitter layer 6 on the textured front surface.
  • Figure 7 shows a cross-section of the solar cell after process 106.
  • the solar cell in this stage comprises the silicon substrate 1 and an n-type emitter layer 6 on the textured front surface of the substrate.
  • a passivation process 110 is applied after the creation of the emitter (although this step is shown immediately after the creation of the emitter, it should be noted that intervening steps may be used).
  • a passivation layer is applied on the emitter layer.
  • Figure 8 shows a cross-section of the solar cell after passivation process 110.
  • the solar cell manufacturing process may be completed with methods known in the art, such as antireflective coating, screen printing of metallization patterns, firing-through, junction isolation, etc.
  • FIG. 2 shows a flow diagram for a method for manufacturing a solar cell in accordance with a second aspect.
  • entities with the same reference number as shown in the preceding figures refer to corresponding entities.
  • processing of the back surface 3 is described.
  • a process 201 an Al-containing layer is applied to the back surface and dried. Screen printing may be used to apply the Al layer, and the Al layer may cover the entire back surface, except optionally an edge around the perimeter of the solar cell, to avoid short circuits with the front surface.
  • an annealing process 202 is performed at a sufficiently high temperature to cause annealing, for example at 850 degrees centigrade. This is called a firing step. Annealing causes aluminum from the layer to alloy with the underlying silicon to create a back side field (BSF).
  • BSF back side field
  • Figure 9 shows a cross-section of the solar cell after
  • FIG 10 shows a cross-section of the solar cell according to an alternative embodiment.
  • a passivating coating 10 is applied to the back surface as a masking layer, before a patterned Al- containing layer 10a is applied to the back surface.
  • a firing step is executed, which causes the patterned Al- containing layer 10a to dissolve the passivation layer 10, and the Al to alloy with the silicon substrate under the passivation layer.
  • Figure 10a shows the result of the firing step, with Al diffused through the passivation layer into the semiconductor substrate.
  • Similar steps may be performed to apply and anneal a patterned metal containing layer on the passivation layer on the textured front surface.
  • the metal layers on the front surface and the back surface may be annealed in the same step or in separate steps. It should be noted that the application of the Al layers is performed in such a way that the front surface is not affected before the partial smoothening process.
  • An alternative embodiment deposits an Al-containing layer on a larger area of the rear surface (e.g. nearly the complete surface), followed by local heating of that layer (e.g. by laser) which causes the Al to alloy and form contact with the Si below the passivation layer.
  • An alternative embodiment forms openings in the passivation layer, followed by deposition of an Al-containing layer on at least those openings, followed by annealing.
  • the solar cell manufacturing process may be completed by application of electrodes on the Al covered regions and other finishing methods known in the art.
  • Figure 3 shows a flow diagram for a method for manufacturing a solar cell in accordance with a second aspect, wherein diffusion areas are created on the back surface.
  • a passivating layer 11 is applied to the back surface of the solar cell. More generally any diffusion barrier layer may be used.
  • Figure 11 shows a cross-section of the solar cell after application of this layer.
  • a pattern of openings is defined in this passivating layer, for example by screen printing a mask and etching. Alternatively screen printing of the passivating layer 11 may be used.
  • p-type or n-type doped glass e.g. Boron or Phosphor doped
  • the solar cell is heated to create diffused regions of respective different conductivity type in the silicon substrate adjacent the back surface, by diffusion from the doped glass. Subsequently the glass is removed.
  • the steps of defining a pattern of openings, applying doped glass and heating may be repeated after removal of the glass of process 302, using a different pattern of openings and a glass with a different type of doping.
  • diffusions of mutually different conductivity type may be created.
  • a first glass with phosphor doping and a second glass with boron doping may be used for example.
  • openings may be defined in the glass of process 302 and a glass with a different type of doping may be applied over the glass of process 302.
  • a single heating process 303 may subsequently be used.
  • Figure 12 shows a cross-section of the solar cell removal of the glass and prior diffusion into first conductivity type diffused regions 12a and second
  • conductivity type diffused regions 12b (only one shown). Subsequently a patterned conductor layer or layers (e.g. metal layer) may be applied to the back surface, to contact the diffused regions 12a, b. In this embodiment no front surface electrodes are needed, since the output voltage of the solar cell arises between the first conductivity type diffused regions 12a and second conductivity type diffused regions 12b.
  • the solar cell manufacturing process may be finished with methods known in the art.
  • only one conductivity type diffused regions may be created locally in the back surface. In this case front diffused region conductivity type should be opposite to rear diffused regions conductivity type, and front and back surface electrodes may be used to produce the output voltage.
  • the passivating layer 11 on the back surface may be deposited together with the passivating layer on the front surface, or they may be deposited separately. It should be noted that the diffusion process 303 is applied selectively to the back surface, preferably after the partial smoothening process, without affecting the front surface prior to partial smoothening process.
  • Figure 13a schematically depicts in more detail an embodiment of a front textured surface after partial smoothening.
  • the valleys between the texture features e.g. pyramid facets
  • the valleys having radii of curvature of less than 25 nm in cross-section with virtual planes perpendicular to the length direction of the valleys.
  • 2a After partial polishing at least some valleys 20, 2a are rounded, and may have increased radii of curvature in said cross section within the range of about 25-250 nm.
  • the radii may be selected from the range of about 250- lOOOnm, which however may require longer processing time for the partial polishing step.
  • the textured surface after partial smoothening is schematically displayed.
  • Figure 13b in some more detail depicts the
  • valley width W and radius r may meet in a valley v.
  • the valley v at the bottom will be very narrow, i.e. w is small, such as ⁇ 50 nm.
  • the valley v may be a bit rounded, leading to a broader valley, with a width w for instance in the range of about 50-2000 nm.
  • At least part of the valley v, after smoothening, may be curved, having a radius r in for instance in the range of about 25-250 nm.
  • the valley width W for the textured front face is in the range of 50- 1000 nm, especially 50-500 nm.
  • the valley radii for the textured front face is in the range of about 25-500 nm, especially 25-250 nm.
  • the preferred valley width of the textured front surface is in the range of 50-1000 nm, especially 50-500 nm, and the preferred valley radii of the textured front surface is the range of about 25-500 nm, especially 25-250 nm.
  • Voc Uo (reference Uo + 5 mV ⁇ 0.5 Uo + 5 mV ⁇ 0.5 mV
  • Figures 14a- 14d shows the SEM images before (14a- 14b) and after (14c- 14d) the partial smoothening on a random pyramid textured wafer surface.
  • the width of the valleys is ⁇ 50 nm
  • after partial smoothening in this example the width is -200 nm.
  • textures may be applied to both surfaces, for example in the same process or in different steps and both textured surfaces may be partly smoothened. If a texture is desired only on a first one of the front and back surfaces, a protective layer may be applied (e.g.
  • the first one of the front and back surfaces may be exposed selectively to texturing and polishing agents, or the second one of the front and back surface may be completely smoothened to remove is texture.
  • the back surface may be provided with partly smoothened texture in such a way. This may also give rise to increased efficiency, for example for the cells of Figures. 10, 11, 12. In such an
  • a method of manufacturing a solar cell from a semiconductor substrate having a first and second surface is provided, the method

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une cellule solaire à partir d'un substrat semi-conducteur, le substrat semi-conducteur ayant une surface avant et une surface arrière, le procédé consistant : - à texturer la surface avant pour créer une surface avant texturée : - à lisser partiellement la surface avant texturée ; - à créer une couche d'un premier type de conductivité dans le substrat semi-conducteur adjacent à la surface avant texturée et lissée, par diffusion d'un dopant du premier type de conductivité dans la surface avant texturée ; - à créer une couche de passivation sur la surface avant par dépôt ou traitement chimique en phase humide après avoir créé ladite couche du premier type de conductivité ; - à déposer un système d'électrodes sur la surface arrière sans diffusion préalable d'une couche d'un second type de conductivité dans le substrat semi-conducteur adjacent à la surface arrière ou au plus avec diffusion d'une telle couche du second type de conductivité sélectivement sur le côté arrière seulement.
PCT/NL2012/050114 2011-02-24 2012-02-24 Cellule solaire et procédé de fabrication d'une telle cellule solaire Ceased WO2012115519A2 (fr)

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CN103887354A (zh) * 2012-12-19 2014-06-25 茂迪股份有限公司 太阳能电池及其制造方法与太阳能电池模块
CN104078567A (zh) * 2014-07-16 2014-10-01 中国科学院物理研究所 混合太阳能电池及其制备方法、空穴输运层形成方法
CN104091857A (zh) * 2014-06-30 2014-10-08 欧贝黎新能源科技股份有限公司 一种纳米绒面多晶硅太阳能电池低压变温扩散方法
JP2017208520A (ja) * 2016-05-20 2017-11-24 ▲ゆ▼晶能源科技股▲分▼有限公司Ｇｉｎｔｅｃｈ Ｅｎｅｒｇｙ Ｃｏｒｐｏｒａｔｉｏｎ 太陽電池及びその製造方法
JP2018026388A (ja) * 2016-08-08 2018-02-15 パナソニックＩｐマネジメント株式会社 太陽電池及び太陽電池の製造方法
CN111081797A (zh) * 2019-12-31 2020-04-28 北京北方华创真空技术有限公司 一种单晶硅片的处理方法及其单晶硅片和太阳能电池
WO2022144214A1 (fr) * 2020-12-30 2022-07-07 Rec Solar Pte. Ltd. Cellule solaire
CN115274914A (zh) * 2021-04-30 2022-11-01 泰州中来光电科技有限公司 一种正面局域钝化接触电池的制备工艺及电池、组件和系统
US20230420581A1 (en) * 2016-10-25 2023-12-28 Shin-Etsu Chemical Co., Ltd. Solar cell with high photoelectric conversion efficiency and method for manufacturing solar cell with high photoelectric conversion efficiency

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103887354A (zh) * 2012-12-19 2014-06-25 茂迪股份有限公司 太阳能电池及其制造方法与太阳能电池模块
CN104091857A (zh) * 2014-06-30 2014-10-08 欧贝黎新能源科技股份有限公司 一种纳米绒面多晶硅太阳能电池低压变温扩散方法
CN104078567A (zh) * 2014-07-16 2014-10-01 中国科学院物理研究所 混合太阳能电池及其制备方法、空穴输运层形成方法
JP2017208520A (ja) * 2016-05-20 2017-11-24 ▲ゆ▼晶能源科技股▲分▼有限公司Ｇｉｎｔｅｃｈ Ｅｎｅｒｇｙ Ｃｏｒｐｏｒａｔｉｏｎ 太陽電池及びその製造方法
JP2018026388A (ja) * 2016-08-08 2018-02-15 パナソニックＩｐマネジメント株式会社 太陽電池及び太陽電池の製造方法
US20230420581A1 (en) * 2016-10-25 2023-12-28 Shin-Etsu Chemical Co., Ltd. Solar cell with high photoelectric conversion efficiency and method for manufacturing solar cell with high photoelectric conversion efficiency
CN111081797A (zh) * 2019-12-31 2020-04-28 北京北方华创真空技术有限公司 一种单晶硅片的处理方法及其单晶硅片和太阳能电池
CN111081797B (zh) * 2019-12-31 2021-04-27 北京北方华创真空技术有限公司 一种单晶硅片的处理方法及其单晶硅片和太阳能电池
WO2022144214A1 (fr) * 2020-12-30 2022-07-07 Rec Solar Pte. Ltd. Cellule solaire
CN115274914A (zh) * 2021-04-30 2022-11-01 泰州中来光电科技有限公司 一种正面局域钝化接触电池的制备工艺及电池、组件和系统

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