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WO2012039364A1 - Procédé et système pour la fabrication d'un dispositif semi-conducteur - Google Patents

Procédé et système pour la fabrication d'un dispositif semi-conducteur Download PDF

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Publication number
WO2012039364A1
WO2012039364A1 PCT/JP2011/071275 JP2011071275W WO2012039364A1 WO 2012039364 A1 WO2012039364 A1 WO 2012039364A1 JP 2011071275 W JP2011071275 W JP 2011071275W WO 2012039364 A1 WO2012039364 A1 WO 2012039364A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor device
cleaning
manufacturing
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/071275
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English (en)
Japanese (ja)
Inventor
剛直 根本
員力 谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tohoku University NUC
Tokyo Electron Ltd
Original Assignee
Tohoku University NUC
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tohoku University NUC, Tokyo Electron Ltd filed Critical Tohoku University NUC
Publication of WO2012039364A1 publication Critical patent/WO2012039364A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention relates to a substrate processing system.
  • the present invention has been made in view of such a point, and in a semiconductor device having a damascene wiring structure, corrosion of the Cu wiring generated due to processing of the Cu wiring by the CMP method is prevented, and wiring resistance is prevented.
  • An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing system in which the rise of the semiconductor device is suppressed and reliability is ensured.
  • the neutralization may be performed by ionizer, soft X-ray irradiation or ultraviolet irradiation.
  • the ionizer is preferably disposed within 100 mm above the substrate. More preferably, the ionizer is preferably disposed within 30 mm above the substrate.
  • the barrier metal may be Ti, TiN, an alloy of Ti and TiN, and the interlayer insulating film may be a CF film (CF-based film).
  • the barrier metal may be Ta, TaN, or an alloy thereof.
  • a manufacturing system for manufacturing a semiconductor device having a damascene wiring structure formed on a substrate, wherein a Cu film formed on the substrate is removed on the substrate transport path.
  • Cu removing device for removing barrier metal removing device for removing the barrier metal deposited on the substrate, neutralizing device for removing static electricity after removing the barrier metal, and a cleaning device for washing slurry and residue remaining on the substrate in order
  • An arranged manufacturing system is provided.
  • FIG. 1 is a schematic explanatory view of a manufacturing system S for manufacturing a semiconductor device A according to an embodiment of the present invention as seen in a plan view.
  • the manufacturing system S is provided with a transport path L for transporting the substrate W.
  • the transfer path L is a substrate transfer path from the carry-in port 7 (upstream) where the substrate W is carried into the manufacturing system S to the carry-out port 8 (downstream) where the substrate W is carried out from the production system S, and is not shown.
  • the substrate W is transported along the transport path L by the arm.
  • a Cu removing device 10 that polishes the substrate W by the CMP method from upstream to downstream, and a barrier metal (hereinafter also referred to as BM) removing device that polishes the substrate W by the CMP method.
  • BM barrier metal
  • a holding member 15 having a packing film made of, for example, a porous resin for holding the substrate W on the substantially disk-shaped lower surface is installed above the turntable 11.
  • the substrate W is held by allowing water to penetrate and adsorbing the substrate W.
  • the holding member 15 is connected to a pressing mechanism 17 that applies a pressing force so as to press the holding member 15 against the turntable 11.
  • the turntable 11 When the substrate W is transferred to the Cu removing apparatus 10 configured as shown in FIG. 2, the turntable 11 is rotated by the operation of the pressing mechanism 17 while the substrate W is held by the rotating holding member 15. The pad is pressed against the pad 14 with the polishing surface facing downward. At this time, a predetermined amount of abrasive (slurry) is supplied to the upper surface of the turntable 11 (upper surface of the pad 14) from an unillustrated abrasive (slurry) supply mechanism. The substrate W held on the lower surface of the rotating holding member 15 is pressed against the rotating pad 14, whereby the substrate W is polished.
  • abrasive slurry
  • FIG. 3 is a schematic explanatory view of the static eliminator 30 that is an ionizer
  • FIG. 3A is a side view of the static eliminator 30
  • FIG. 3B is a plan view of the static eliminator 30.
  • the static eliminator 30 is arranged by disposing the counter electrodes 32 on both sides of the rod-like support member 31 and attaching a plurality of needle-like electrodes 33 to both sides of the support member 31 at a predetermined interval. It is configured.
  • Circular holes 34 are formed in the counter electrode 32 at predetermined intervals, and the needle-like electrodes 33 are located at the centers of the circular holes 34.
  • the static eliminator 30 configured as shown in FIG. 3, by applying a voltage higher than the dielectric breakdown strength of air between the counter electrode 32 and the needle electrode 33, + ions and ⁇ ions in the vicinity of the static eliminator 30. Can be generated. In this manner, the substrate W is neutralized by bringing the charged substrate W close (interfering) in a state where + ions and ⁇ ions are generated in the vicinity of the neutralization device 30.
  • FIG. 4 is an explanatory diagram of a cleaning device 40 that cleans the substrate W after polishing.
  • support members 41 that support three peripheral edge portions of the substrate W that has been carried in are provided at three locations.
  • the support member 41 includes a substantially disc-shaped support portion 41a and a column portion 41b that supports the support portion 41a.
  • the substantially disc-shaped support portion 41a is configured to be rotatable by a drive mechanism (not shown).
  • the substrate W transported to the cleaning device 40 is supported such that the three peripheral edge portions thereof are in contact with the peripheral edge portions of the three support portions 41a.
  • the substrate W supported by the rotation of the support portion 41a is also rotated by the rotation of the support portion 41a.
  • a pair of roll-shaped cleaning brushes 43 (upper brush 43a and lower brush 43b) supported by a roll shaft (not shown) are provided.
  • the pair 43 can be brought into contact with the upper and lower surfaces of the substrate W as appropriate.
  • the cleaning brush pair 43 is rotatable by rotation of a roll shaft (not shown), and further, the roll shaft (not shown) is configured to be movable.
  • 43a is configured such that the lower brush 43b can contact the entire lower surface.
  • a predetermined amount of cleaning liquid is appropriately supplied from the cleaning liquid supply mechanism to the substrate W during cleaning.
  • the cleaning liquid may be pure water or the like, but is more preferably a cleaning liquid containing an acid such as citric acid or oxalic acid.
  • the substrate W When the substrate W is transported to the cleaning device 40 shown in FIG. 4, the substrate W is supported by the support member 41 and rotates as the support portion 41a rotates. Further, a rotating cleaning brush pair 43 is brought into contact with the upper and lower surfaces of the substrate W, and the substrate W is cleaned in a state where the cleaning liquid is supplied.
  • the Cu residue, the BM residue, and the abrasive (slurry) that are removed by the CMP method in the Cu removing device 10 and the BM removing device 20 and remain on the substrate W are washed, and the cleaned substrate W is washed. It is carried out from.
  • the manufacturing system S according to the embodiment of the present invention and the device configuration of each device constituting the manufacturing system S have been described above with reference to FIGS. 1 to 4.
  • the manufacturing system S and its pre-processing will be described.
  • a process (a process performed on the substrate W before being carried into the manufacturing system S) and a substrate process performed in the manufacturing system S will be described with reference to FIGS.
  • FIG. 5 to FIG. 9 are explanatory views showing manufacturing steps of the semiconductor device A according to the embodiment of the present invention. That is, a process of forming a Cu wiring on the upper surface of the substrate body 100 in the semiconductor substrate W made of Si or the like is illustrated.
  • a wiring pattern groove 104 is formed on the surface of an interlayer insulating film 102 made of, for example, a CF film formed on the substrate body 100. Subsequently, a wiring pattern is formed on a mask material (not shown) formed on the interlayer insulating film 102 by photolithography. Furthermore, the wiring pattern groove 104 is formed on the surface of the interlayer insulating film 102 by reactive ion etching (RIE), and the mask material is removed.
  • RIE reactive ion etching
  • a Cu conductive layer 110 is formed on the entire surface of the substrate W so as to fill the wiring pattern groove 104 from above the Cu plating seed layer 107.
  • the Cu conductive layer 110 is not limited to pure Cu but may be a Cu alloy, and is formed by alloy Cu plating, sputtering, or the like.
  • the Cu plating seed layer 107 is integrated with the Cu conductive layer 110 by forming the Cu conductive layer 110.
  • the surface of the Cu conductive layer 110 that is, the Cu conductive layer 110 excluding the Cu conductive layer 110 inside the wiring pattern groove 104 is removed by the CMP method.
  • the Cu conductive layer 110 is left inside the wiring groove 104, and the substrate surface other than the wiring groove 104 is covered with the BM layer 105.
  • the BM layer 105 is removed from above the interlayer insulating film 102 by the CMP method, leaving the portions of the Cu conductive layer 110 and the BM layer 105 inside the wiring pattern groove 104.
  • the Cu wiring 115 is formed in the wiring pattern groove 104 surrounded by the BM layer 105, and the semiconductor device A having the damascene wiring structure is manufactured.
  • the removal of the Cu conductive layer 110 and the BM layer 105 shown in FIGS. 8 and 9 by the CMP method is performed by the manufacturing system S including the Cu removal device 10 and the BM removal device 20 shown in FIG.
  • the manufacturing system S including the Cu removal device 10 and the BM removal device 20 shown in FIG.
  • a process for the substrate W (removal of the Cu conductive layer 110 and the BM layer 105 shown in FIG. 9) performed in the manufacturing system S will be described with reference to the drawings.
  • the substrate W on which the entire surface of the Cu conductive layer 110 manufactured by the steps described in FIGS. 5 to 7 is formed is carried in from the carry-in entrance 7.
  • the substrate W carried in from the carry-in entrance 7 is carried along the carrying path L, and first, Cu is removed by the CMP method in the Cu removing apparatus 10. That is, the Cu conductive layer 110 deposited on the substrate W in the state shown in FIG. 7 is polished, and the Cu deposited in addition to the wiring pattern groove 104 is removed as shown in FIG.
  • the Cu conductive layer 110 remains inside, and the BM layer 105 is deposited on the substrate surface other than the wiring pattern groove 104.
  • the Cu conductive layer 110 and the BM layer 105 are formed adjacent to each other in the substrate W as shown in FIG.
  • the ionization tendency between the two metals is different, so that the movement of electrons occurs between the two, so-called battery.
  • the Cu wiring 115 is corroded.
  • the substrate W when the substrate W is polished using the electricity generated on the substrate W during the manufacturing process or using the CMP method, the substrate W is charged by friction during polishing.
  • the substrate W polished in the Cu removing device 10 and the BM removing device 20 is transferred to the charge removing device 30 which is, for example, an ionizer shown in FIG. 3, and the charged substrate W is transferred to the charge removing device 30. Makes the substrate W neutralize.
  • position the static elimination apparatus 30 it is preferable to arrange
  • an ionizer is illustrated as an example of the charge removal device 30 in FIG. 3, but the present invention is not limited to this, and any device that can remove the substrate W may be used.
  • the other types of static eliminating devices 30 include a soft X-ray irradiation device and an ultraviolet irradiation device.
  • a Cu removing device 10 that polishes the substrate W from the upstream toward the downstream by the CMP method, and a Cu finishing device that performs the finish polishing by the CMP method.
  • 50 for example, a static elimination device 60 that is an ionizer, a Cu cleaning device 70 that cleans Cu residues generated by polishing by the CMP method, a BM removal device 20 that performs polishing by the CMP method, a static elimination device 30, and the polishing by the CMP method
  • the cleaning device 40 for cleaning the BM residue and the like is provided in this order.
  • the Cu finishing process by the Cu finishing apparatus 50 and the static elimination by the static eliminating apparatus 60 are performed between the Cu removing process by the Cu removing apparatus 10 and the BM removing process by the BM removing apparatus 20 described in the above embodiment.
  • the process and the Cu cleaning process by the Cu cleaning apparatus 70 are added. Therefore, hereinafter, a Cu finishing process, a Cu cleaning process, and a static elimination process performed between the Cu finishing process and the Cu cleaning process, which are not described in the description of the above embodiment, will be described.
  • the apparatus configuration of the Cu finishing apparatus 50 that performs the Cu finishing process is the same as that of the Cu removing apparatus described with reference to FIG. 2 (a polishing apparatus using the CMP method), and the Cu cleaning process that performs the Cu cleaning process.
  • the apparatus configuration of the apparatus 70 is the same as that of the cleaning apparatus 40 described with reference to FIG. 4, and the apparatus configuration of the static elimination apparatus 60 is the same as that of the static elimination apparatus 30 described with reference to FIG. Therefore, description of the device configuration is omitted here.
  • the substrate W polished by the Cu finishing device 50 is transported to a static eliminator 60 that is, for example, an ionizer.
  • the CMP method used in the Cu removing apparatus 10 and the Cu finishing apparatus 50 is the polishing with the substrate W fixed by the holding member 15 and the substrate W fixed to the holding member 15 as described above with reference to FIG.
  • polishing is performed by supplying an agent (slurry) and rotating the substrate W while pressing it against the pad 14.
  • the substrate W is charged with static electricity generated by the friction. Therefore, the substrate W polished in the Cu finishing device 50 is transported to the static eliminator 60, and the charged substrate W is caused to interfere with the static eliminator 60, so that the substrate W is neutralized.
  • the substrate W that has been neutralized in the static eliminator 60 is transferred to the Cu cleaning device 70.
  • Cu removed (polished) in the Cu removing device 10 and the Cu finishing device 50 is attached to the substrate W as a slurry residue. Therefore, in the Cu cleaning apparatus 70, for example, the slurry-like residue and the polishing agent (slurry) remaining after polishing are cleaned using a cleaning liquid containing an acid such as citric acid or oxalic acid, and the substrate W is cleaned.
  • a cleaning liquid containing an acid such as citric acid or oxalic acid
  • the Cu finishing process is performed after the Cu removing process, so that the Cu remaining inside the wiring trench 104 (that is, Removal of the Cu conductive layer 110 other than the Cu wiring 115) is performed with extremely high accuracy.
  • the static elimination process and the cleaning process of the substrate W are performed after the Cu removal process and the Cu finishing process, and the static elimination process and the cleaning process of the substrate W are performed after the BM removal process.
  • the Cu wiring 115 is effectively prevented from being corroded due to the charging of the metal and the adhesion of the acid used for cleaning the charged substrate W. As a result, an increase in wiring resistance is suppressed, and a semiconductor device with guaranteed reliability can be obtained.
  • a Cu (Cu conductive layer) removing step by a CMP method, a Ti (BM layer) removing step, and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface.
  • SEM electron microscope
  • FIG. 11 shows a case where a Cu (Cu conductive layer) removing step, a Ti (BM layer) removing step and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface.
  • FIG. 12 shows a static electricity removal after a Cu (Cu conductive layer) removing step, a pure water cleaning step, a Ti (BM layer) removing step, and a Ti removing step by a CMP method on a substrate having a Cu conductive layer formed on the entire surface.
  • Cu wiring Example
  • the static elimination step was performed using an ionizer, and the ionizer was disposed at a position 30 mm above the substrate.
  • the present invention is useful for a semiconductor device manufacturing method and a semiconductor device manufacturing system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

L'invention concerne un procédé et un système pour la fabrication d'un dispositif semi-conducteur qui permettent d'empêcher la corrosion d'une ligne de câblage en cuivre généralement provoquée par le traitement de ladite ligne par un procédé de polissage mécanochimique, qui permettent également d'empêcher l'augmentation de la résistance de câblage dans un dispositif semi-conducteur ayant une structure de câblage à damasquinage, et qui permettent de fabriquer un dispositif semi-conducteur avec une fiabilité garantie. Ledit procédé de fabrication d'un dispositif semi-conducteur ayant une structure de câblage à damasquinage comprend les étapes consistant à : former un film barrière métallique et un film de cuivre dans un sillon d'un motif de câblage formé sur un film isolant intercalaire sur un substrat, et retirer le cuivre qui s'est accumulé à l'extérieur du sillon du motif de câblage sur le film isolant intercalaire par polissage mécanochimique ; retirer le métal barrière qui s'est accumulé à l'extérieur du sillon du motif de câblage sur le film isolant intercalaire par polissage mécanochimique ; puis neutraliser le produit résultant ; et éliminer par lavage la pâte et les résidus restant sur le substrat.
PCT/JP2011/071275 2010-09-21 2011-09-16 Procédé et système pour la fabrication d'un dispositif semi-conducteur Ceased WO2012039364A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010210445A JP2012069550A (ja) 2010-09-21 2010-09-21 半導体装置の製造方法および半導体装置の製造システム
JP2010-210445 2010-09-21

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WO2012039364A1 true WO2012039364A1 (fr) 2012-03-29

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Publication number Priority date Publication date Assignee Title
WO2023037979A1 (fr) 2021-09-07 2023-03-16 日産化学株式会社 Composition de formation de film de sous-couche de réserve contenant du silicium, corps multicouche employant ladite composition et procédé de production d'élément semi-conducteur
JP2024066669A (ja) 2022-11-02 2024-05-16 株式会社荏原製作所 基板洗浄装置、基板乾燥装置、基板搬送装置、基板載置装置、基板処理装置、帯電量制御方法および帯電量制御プログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141312A (ja) * 2000-11-02 2002-05-17 Nec Corp Ｃｍｐ方法および装置、回路形成方法およびシステム、集積回路装置
JP2005307311A (ja) * 2004-04-23 2005-11-04 Ebara Corp 基板処理装置及び基板処理方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141312A (ja) * 2000-11-02 2002-05-17 Nec Corp Ｃｍｐ方法および装置、回路形成方法およびシステム、集積回路装置
JP2005307311A (ja) * 2004-04-23 2005-11-04 Ebara Corp 基板処理装置及び基板処理方法

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