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WO2012039364A1 - Semiconductor device production process and semiconductor device production system - Google Patents

Semiconductor device production process and semiconductor device production system Download PDF

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Publication number
WO2012039364A1
WO2012039364A1 PCT/JP2011/071275 JP2011071275W WO2012039364A1 WO 2012039364 A1 WO2012039364 A1 WO 2012039364A1 JP 2011071275 W JP2011071275 W JP 2011071275W WO 2012039364 A1 WO2012039364 A1 WO 2012039364A1
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WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor device
cleaning
manufacturing
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/071275
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French (fr)
Japanese (ja)
Inventor
剛直 根本
員力 谷
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Tohoku University NUC
Tokyo Electron Ltd
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Tohoku University NUC
Tokyo Electron Ltd
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Application filed by Tohoku University NUC, Tokyo Electron Ltd filed Critical Tohoku University NUC
Publication of WO2012039364A1 publication Critical patent/WO2012039364A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67046—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly scrubbing means, e.g. brushes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Definitions

  • the present invention relates to a substrate processing system.
  • the present invention has been made in view of such a point, and in a semiconductor device having a damascene wiring structure, corrosion of the Cu wiring generated due to processing of the Cu wiring by the CMP method is prevented, and wiring resistance is prevented.
  • An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing system in which the rise of the semiconductor device is suppressed and reliability is ensured.
  • the neutralization may be performed by ionizer, soft X-ray irradiation or ultraviolet irradiation.
  • the ionizer is preferably disposed within 100 mm above the substrate. More preferably, the ionizer is preferably disposed within 30 mm above the substrate.
  • the barrier metal may be Ti, TiN, an alloy of Ti and TiN, and the interlayer insulating film may be a CF film (CF-based film).
  • the barrier metal may be Ta, TaN, or an alloy thereof.
  • a manufacturing system for manufacturing a semiconductor device having a damascene wiring structure formed on a substrate, wherein a Cu film formed on the substrate is removed on the substrate transport path.
  • Cu removing device for removing barrier metal removing device for removing the barrier metal deposited on the substrate, neutralizing device for removing static electricity after removing the barrier metal, and a cleaning device for washing slurry and residue remaining on the substrate in order
  • An arranged manufacturing system is provided.
  • FIG. 1 is a schematic explanatory view of a manufacturing system S for manufacturing a semiconductor device A according to an embodiment of the present invention as seen in a plan view.
  • the manufacturing system S is provided with a transport path L for transporting the substrate W.
  • the transfer path L is a substrate transfer path from the carry-in port 7 (upstream) where the substrate W is carried into the manufacturing system S to the carry-out port 8 (downstream) where the substrate W is carried out from the production system S, and is not shown.
  • the substrate W is transported along the transport path L by the arm.
  • a Cu removing device 10 that polishes the substrate W by the CMP method from upstream to downstream, and a barrier metal (hereinafter also referred to as BM) removing device that polishes the substrate W by the CMP method.
  • BM barrier metal
  • a holding member 15 having a packing film made of, for example, a porous resin for holding the substrate W on the substantially disk-shaped lower surface is installed above the turntable 11.
  • the substrate W is held by allowing water to penetrate and adsorbing the substrate W.
  • the holding member 15 is connected to a pressing mechanism 17 that applies a pressing force so as to press the holding member 15 against the turntable 11.
  • the turntable 11 When the substrate W is transferred to the Cu removing apparatus 10 configured as shown in FIG. 2, the turntable 11 is rotated by the operation of the pressing mechanism 17 while the substrate W is held by the rotating holding member 15. The pad is pressed against the pad 14 with the polishing surface facing downward. At this time, a predetermined amount of abrasive (slurry) is supplied to the upper surface of the turntable 11 (upper surface of the pad 14) from an unillustrated abrasive (slurry) supply mechanism. The substrate W held on the lower surface of the rotating holding member 15 is pressed against the rotating pad 14, whereby the substrate W is polished.
  • abrasive slurry
  • FIG. 3 is a schematic explanatory view of the static eliminator 30 that is an ionizer
  • FIG. 3A is a side view of the static eliminator 30
  • FIG. 3B is a plan view of the static eliminator 30.
  • the static eliminator 30 is arranged by disposing the counter electrodes 32 on both sides of the rod-like support member 31 and attaching a plurality of needle-like electrodes 33 to both sides of the support member 31 at a predetermined interval. It is configured.
  • Circular holes 34 are formed in the counter electrode 32 at predetermined intervals, and the needle-like electrodes 33 are located at the centers of the circular holes 34.
  • the static eliminator 30 configured as shown in FIG. 3, by applying a voltage higher than the dielectric breakdown strength of air between the counter electrode 32 and the needle electrode 33, + ions and ⁇ ions in the vicinity of the static eliminator 30. Can be generated. In this manner, the substrate W is neutralized by bringing the charged substrate W close (interfering) in a state where + ions and ⁇ ions are generated in the vicinity of the neutralization device 30.
  • FIG. 4 is an explanatory diagram of a cleaning device 40 that cleans the substrate W after polishing.
  • support members 41 that support three peripheral edge portions of the substrate W that has been carried in are provided at three locations.
  • the support member 41 includes a substantially disc-shaped support portion 41a and a column portion 41b that supports the support portion 41a.
  • the substantially disc-shaped support portion 41a is configured to be rotatable by a drive mechanism (not shown).
  • the substrate W transported to the cleaning device 40 is supported such that the three peripheral edge portions thereof are in contact with the peripheral edge portions of the three support portions 41a.
  • the substrate W supported by the rotation of the support portion 41a is also rotated by the rotation of the support portion 41a.
  • a pair of roll-shaped cleaning brushes 43 (upper brush 43a and lower brush 43b) supported by a roll shaft (not shown) are provided.
  • the pair 43 can be brought into contact with the upper and lower surfaces of the substrate W as appropriate.
  • the cleaning brush pair 43 is rotatable by rotation of a roll shaft (not shown), and further, the roll shaft (not shown) is configured to be movable.
  • 43a is configured such that the lower brush 43b can contact the entire lower surface.
  • a predetermined amount of cleaning liquid is appropriately supplied from the cleaning liquid supply mechanism to the substrate W during cleaning.
  • the cleaning liquid may be pure water or the like, but is more preferably a cleaning liquid containing an acid such as citric acid or oxalic acid.
  • the substrate W When the substrate W is transported to the cleaning device 40 shown in FIG. 4, the substrate W is supported by the support member 41 and rotates as the support portion 41a rotates. Further, a rotating cleaning brush pair 43 is brought into contact with the upper and lower surfaces of the substrate W, and the substrate W is cleaned in a state where the cleaning liquid is supplied.
  • the Cu residue, the BM residue, and the abrasive (slurry) that are removed by the CMP method in the Cu removing device 10 and the BM removing device 20 and remain on the substrate W are washed, and the cleaned substrate W is washed. It is carried out from.
  • the manufacturing system S according to the embodiment of the present invention and the device configuration of each device constituting the manufacturing system S have been described above with reference to FIGS. 1 to 4.
  • the manufacturing system S and its pre-processing will be described.
  • a process (a process performed on the substrate W before being carried into the manufacturing system S) and a substrate process performed in the manufacturing system S will be described with reference to FIGS.
  • FIG. 5 to FIG. 9 are explanatory views showing manufacturing steps of the semiconductor device A according to the embodiment of the present invention. That is, a process of forming a Cu wiring on the upper surface of the substrate body 100 in the semiconductor substrate W made of Si or the like is illustrated.
  • a wiring pattern groove 104 is formed on the surface of an interlayer insulating film 102 made of, for example, a CF film formed on the substrate body 100. Subsequently, a wiring pattern is formed on a mask material (not shown) formed on the interlayer insulating film 102 by photolithography. Furthermore, the wiring pattern groove 104 is formed on the surface of the interlayer insulating film 102 by reactive ion etching (RIE), and the mask material is removed.
  • RIE reactive ion etching
  • a Cu conductive layer 110 is formed on the entire surface of the substrate W so as to fill the wiring pattern groove 104 from above the Cu plating seed layer 107.
  • the Cu conductive layer 110 is not limited to pure Cu but may be a Cu alloy, and is formed by alloy Cu plating, sputtering, or the like.
  • the Cu plating seed layer 107 is integrated with the Cu conductive layer 110 by forming the Cu conductive layer 110.
  • the surface of the Cu conductive layer 110 that is, the Cu conductive layer 110 excluding the Cu conductive layer 110 inside the wiring pattern groove 104 is removed by the CMP method.
  • the Cu conductive layer 110 is left inside the wiring groove 104, and the substrate surface other than the wiring groove 104 is covered with the BM layer 105.
  • the BM layer 105 is removed from above the interlayer insulating film 102 by the CMP method, leaving the portions of the Cu conductive layer 110 and the BM layer 105 inside the wiring pattern groove 104.
  • the Cu wiring 115 is formed in the wiring pattern groove 104 surrounded by the BM layer 105, and the semiconductor device A having the damascene wiring structure is manufactured.
  • the removal of the Cu conductive layer 110 and the BM layer 105 shown in FIGS. 8 and 9 by the CMP method is performed by the manufacturing system S including the Cu removal device 10 and the BM removal device 20 shown in FIG.
  • the manufacturing system S including the Cu removal device 10 and the BM removal device 20 shown in FIG.
  • a process for the substrate W (removal of the Cu conductive layer 110 and the BM layer 105 shown in FIG. 9) performed in the manufacturing system S will be described with reference to the drawings.
  • the substrate W on which the entire surface of the Cu conductive layer 110 manufactured by the steps described in FIGS. 5 to 7 is formed is carried in from the carry-in entrance 7.
  • the substrate W carried in from the carry-in entrance 7 is carried along the carrying path L, and first, Cu is removed by the CMP method in the Cu removing apparatus 10. That is, the Cu conductive layer 110 deposited on the substrate W in the state shown in FIG. 7 is polished, and the Cu deposited in addition to the wiring pattern groove 104 is removed as shown in FIG.
  • the Cu conductive layer 110 remains inside, and the BM layer 105 is deposited on the substrate surface other than the wiring pattern groove 104.
  • the Cu conductive layer 110 and the BM layer 105 are formed adjacent to each other in the substrate W as shown in FIG.
  • the ionization tendency between the two metals is different, so that the movement of electrons occurs between the two, so-called battery.
  • the Cu wiring 115 is corroded.
  • the substrate W when the substrate W is polished using the electricity generated on the substrate W during the manufacturing process or using the CMP method, the substrate W is charged by friction during polishing.
  • the substrate W polished in the Cu removing device 10 and the BM removing device 20 is transferred to the charge removing device 30 which is, for example, an ionizer shown in FIG. 3, and the charged substrate W is transferred to the charge removing device 30. Makes the substrate W neutralize.
  • position the static elimination apparatus 30 it is preferable to arrange
  • an ionizer is illustrated as an example of the charge removal device 30 in FIG. 3, but the present invention is not limited to this, and any device that can remove the substrate W may be used.
  • the other types of static eliminating devices 30 include a soft X-ray irradiation device and an ultraviolet irradiation device.
  • a Cu removing device 10 that polishes the substrate W from the upstream toward the downstream by the CMP method, and a Cu finishing device that performs the finish polishing by the CMP method.
  • 50 for example, a static elimination device 60 that is an ionizer, a Cu cleaning device 70 that cleans Cu residues generated by polishing by the CMP method, a BM removal device 20 that performs polishing by the CMP method, a static elimination device 30, and the polishing by the CMP method
  • the cleaning device 40 for cleaning the BM residue and the like is provided in this order.
  • the Cu finishing process by the Cu finishing apparatus 50 and the static elimination by the static eliminating apparatus 60 are performed between the Cu removing process by the Cu removing apparatus 10 and the BM removing process by the BM removing apparatus 20 described in the above embodiment.
  • the process and the Cu cleaning process by the Cu cleaning apparatus 70 are added. Therefore, hereinafter, a Cu finishing process, a Cu cleaning process, and a static elimination process performed between the Cu finishing process and the Cu cleaning process, which are not described in the description of the above embodiment, will be described.
  • the apparatus configuration of the Cu finishing apparatus 50 that performs the Cu finishing process is the same as that of the Cu removing apparatus described with reference to FIG. 2 (a polishing apparatus using the CMP method), and the Cu cleaning process that performs the Cu cleaning process.
  • the apparatus configuration of the apparatus 70 is the same as that of the cleaning apparatus 40 described with reference to FIG. 4, and the apparatus configuration of the static elimination apparatus 60 is the same as that of the static elimination apparatus 30 described with reference to FIG. Therefore, description of the device configuration is omitted here.
  • the substrate W polished by the Cu finishing device 50 is transported to a static eliminator 60 that is, for example, an ionizer.
  • the CMP method used in the Cu removing apparatus 10 and the Cu finishing apparatus 50 is the polishing with the substrate W fixed by the holding member 15 and the substrate W fixed to the holding member 15 as described above with reference to FIG.
  • polishing is performed by supplying an agent (slurry) and rotating the substrate W while pressing it against the pad 14.
  • the substrate W is charged with static electricity generated by the friction. Therefore, the substrate W polished in the Cu finishing device 50 is transported to the static eliminator 60, and the charged substrate W is caused to interfere with the static eliminator 60, so that the substrate W is neutralized.
  • the substrate W that has been neutralized in the static eliminator 60 is transferred to the Cu cleaning device 70.
  • Cu removed (polished) in the Cu removing device 10 and the Cu finishing device 50 is attached to the substrate W as a slurry residue. Therefore, in the Cu cleaning apparatus 70, for example, the slurry-like residue and the polishing agent (slurry) remaining after polishing are cleaned using a cleaning liquid containing an acid such as citric acid or oxalic acid, and the substrate W is cleaned.
  • a cleaning liquid containing an acid such as citric acid or oxalic acid
  • the Cu finishing process is performed after the Cu removing process, so that the Cu remaining inside the wiring trench 104 (that is, Removal of the Cu conductive layer 110 other than the Cu wiring 115) is performed with extremely high accuracy.
  • the static elimination process and the cleaning process of the substrate W are performed after the Cu removal process and the Cu finishing process, and the static elimination process and the cleaning process of the substrate W are performed after the BM removal process.
  • the Cu wiring 115 is effectively prevented from being corroded due to the charging of the metal and the adhesion of the acid used for cleaning the charged substrate W. As a result, an increase in wiring resistance is suppressed, and a semiconductor device with guaranteed reliability can be obtained.
  • a Cu (Cu conductive layer) removing step by a CMP method, a Ti (BM layer) removing step, and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface.
  • SEM electron microscope
  • FIG. 11 shows a case where a Cu (Cu conductive layer) removing step, a Ti (BM layer) removing step and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface.
  • FIG. 12 shows a static electricity removal after a Cu (Cu conductive layer) removing step, a pure water cleaning step, a Ti (BM layer) removing step, and a Ti removing step by a CMP method on a substrate having a Cu conductive layer formed on the entire surface.
  • Cu wiring Example
  • the static elimination step was performed using an ionizer, and the ionizer was disposed at a position 30 mm above the substrate.
  • the present invention is useful for a semiconductor device manufacturing method and a semiconductor device manufacturing system.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

[Problem] To provide a semiconductor device production process and a semiconductor device production system, both of which enable the prevention of the occurrence of corrosion in a Cu wiring line which is usually caused by the treatment of the Cu wiring line by a CMP method and also enable the prevention of increase in wiring resistance in a semiconductor device having a damascene wiring structure, and which can produce the semiconductor device having ensured reliability. [Solution] Provided is a process for producing a semiconductor device having a damascene wiring structure, which comprises the steps of: forming a barrier metal film and a Cu film in a wiring pattern groove formed on an interlayer insulating film on a substrate and removing Cu that is accumulated in a part other than the wiring pattern groove on the interlayer insulating film by chemical mechanical polishing; removing a barrier metal that is accumulated on a part other than the wiring pattern groove on the interlayer insulating film by chemical mechanical polishing; and, subsequent to the step of removing the barrier metal, neutralizing the resulting product; and washing off a slurry and a residue remaining on the substrate.

Description

半導体装置の製造方法および半導体装置の製造システムSemiconductor device manufacturing method and semiconductor device manufacturing system

　本発明は、基板処理システムに関する。 The present invention relates to a substrate processing system.

　近年、半導体装置の配線は、低抵抗化および高信頼性化を目的として、従来のＡｌ配線からＣｕ配線へと移行しつつある。Ｃｕ配線は、ドライエッチングによる形成が困難なため、配線を多層に形成したダマシン配線構造を有する。ダマシン配線構造は、層間絶縁膜上に形成された配線パターンの溝にＣｕ膜を堆積させ、その後、配線パターン溝以外に堆積させたＣｕをケミカルメカニカルポリッシング（以下ＣＭＰ法とも呼称する）によって除去する方法で作られる。 In recent years, wiring of semiconductor devices is shifting from conventional Al wiring to Cu wiring for the purpose of reducing resistance and increasing reliability. Since Cu wiring is difficult to form by dry etching, it has a damascene wiring structure in which wiring is formed in multiple layers. In the damascene wiring structure, a Cu film is deposited in a groove of a wiring pattern formed on an interlayer insulating film, and thereafter, Cu deposited in a portion other than the wiring pattern groove is removed by chemical mechanical polishing (hereinafter also referred to as CMP method). Made in the way.

　しかしながら、ＣＭＰ法により配線パターン溝以外に堆積させたＣｕ層を除去する場合に、層間絶縁膜の溝に形成されたＣｕ配線と層間絶縁膜の溝との間に設けられた例えばＴａ膜、Ｔａ化合物、Ｔｉ膜、ＴｉＮ（Ｔｉナイトライド）膜等のバリアメタル膜が表面に露出した状態になる。その状態では、両者のイオン化傾向が異なることにより、特にその界面近傍においてＣｕ配線の腐食（コロージョン）が起きてしまう。 However, when the Cu layer deposited other than the wiring pattern groove is removed by the CMP method, for example, a Ta film or Ta film provided between the Cu wiring formed in the groove of the interlayer insulating film and the groove of the interlayer insulating film A barrier metal film such as a compound, a Ti film, or a TiN (Ti nitride) film is exposed on the surface. In this state, the ionization tendency of the two is different, and corrosion (corrosion) of the Cu wiring occurs particularly near the interface.

そこで、例えば特許文献１、２には、Ｃｕ配線回路をＣＭＰ法およびその後の薬液洗浄を用いて、Ｃｕ表面を荒らすことなく（Ｃｕ汚染を防止して）形成する技術が開示されている。また、特許文献３には、配線の形成時にＣｕ配線およびバリアメタル露出面を水素ガスおよび酸素ガスが溶解された溶液でもって洗浄し、配線に生じる腐食（コロージョン）を防止する技術が開示されている。 Thus, for example, Patent Documents 1 and 2 disclose a technique for forming a Cu wiring circuit using the CMP method and subsequent chemical cleaning without roughening the Cu surface (preventing Cu contamination). Further, Patent Document 3 discloses a technique for preventing corrosion (corrosion) generated in a wiring by cleaning a Cu wiring and a barrier metal exposed surface with a solution in which hydrogen gas and oxygen gas are dissolved when the wiring is formed. Yes.

特開２００１－２１０６３０号公報Japanese Patent Laid-Open No. 2001-210630 特開２００９－４８０７号公報JP 2009-4807 A 特開２００３－３３８４６４号公報JP 2003-338464 A

　しかしながら、ＣＭＰ法により基板の研磨が行われると、基板と研磨パッドおよび研磨剤（スラリー）との摩擦により静電気が発生し、基板上の配線パターンの表面が帯電して、Ｃｕ配線の腐食が促進されてしまう恐れがある。そして、Ｃｕ配線の腐食が促進されると、配線抵抗が上昇してしまうという問題や、配線の断線等が発生してしまう恐れがあるため半導体装置の信頼性が低下してしまうといった問題が懸念される。さらには、ＣＭＰ法による研磨後のスラリーを洗浄する洗浄工程には、通常クエン酸、シュウ酸等の酸が用いられるが、これらの酸によって配線の腐食がより進行してしまうといった懸念もある。上記特許文献１～３に記載の発明においては、ＣＭＰ法を用いて配線形成を行う場合が記載されているが、ＣＭＰ法を実施する際に配線パターンの表面に静電気が生じてしまい、ＣＭＰの工程やその後の洗浄工程等によりＣｕ配線の腐食が促進されてしまうとの問題は想起されていない。 However, when the substrate is polished by the CMP method, static electricity is generated due to friction between the substrate, the polishing pad, and the abrasive (slurry), and the surface of the wiring pattern on the substrate is charged to accelerate corrosion of the Cu wiring. There is a risk of being. Further, if corrosion of Cu wiring is promoted, there is a concern that the wiring resistance may increase, or that the reliability of the semiconductor device may be reduced because there is a risk of disconnection of the wiring. Is done. Furthermore, although an acid such as citric acid or oxalic acid is usually used in the cleaning step for cleaning the slurry after polishing by the CMP method, there is a concern that the corrosion of the wiring is further promoted by these acids. In the inventions described in Patent Documents 1 to 3, a case is described in which wiring formation is performed using the CMP method. However, when the CMP method is performed, static electricity is generated on the surface of the wiring pattern, and the CMP process is performed. No problem has been recalled that the corrosion of the Cu wiring is promoted by the process or the subsequent cleaning process.

　本発明は、かかる点に鑑みてなされたものであり、ダマシン配線構造を有する半導体装置において、ＣＭＰ法によるＣｕ配線への処理により発生するＣｕ配線の腐食（コロージョン）の発生を防止し、配線抵抗の上昇を抑制し、信頼性の担保された半導体装置の製造方法および半導体装置の製造システムを提供することを目的とする。 The present invention has been made in view of such a point, and in a semiconductor device having a damascene wiring structure, corrosion of the Cu wiring generated due to processing of the Cu wiring by the CMP method is prevented, and wiring resistance is prevented. An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device manufacturing system in which the rise of the semiconductor device is suppressed and reliability is ensured.

　前記の目的を達成するため、本発明によれば、ダマシン配線構造を有する半導体装置の製造方法であって、基板上の層間絶縁膜に形成される配線パターン溝にバリアメタル膜およびＣｕ膜が形成された状態で、ケミカルメカニカルポリッシングによって配線パターン溝以外に堆積したＣｕを除去する工程と、配線パターン溝以外に堆積したバリアメタルをケミカルメカニカルポリッシングによって除去する工程と、前記バリアメタルを除去する工程後、除電する工程と、基板上に残るスラリーおよび残渣物を洗浄する工程と、を有する半導体装置の製造方法が提供される。 To achieve the above object, according to the present invention, there is provided a method for manufacturing a semiconductor device having a damascene wiring structure, wherein a barrier metal film and a Cu film are formed in a wiring pattern groove formed in an interlayer insulating film on a substrate. After the step of removing Cu deposited other than the wiring pattern groove by chemical mechanical polishing, the step of removing the barrier metal deposited other than the wiring pattern groove by chemical mechanical polishing, and the step of removing the barrier metal There is provided a method for manufacturing a semiconductor device, comprising a step of removing electricity and a step of cleaning slurry and residue remaining on a substrate.

　上記半導体装置の製造方法において、前記Ｃｕを除去する工程後、前記Ｃｕ洗浄工程前に除電する工程と、前記Ｃｕを除去する工程後に基板上に残るスラリーおよび残渣物を洗浄するＣｕ洗浄工程と、を有していてもよい。また、前記Ｃｕを除去する工程後、Ｃｕの仕上研磨を行う仕上工程を有していてもよい。 In the manufacturing method of the semiconductor device, after the step of removing the Cu, a step of removing electricity before the Cu cleaning step, a Cu cleaning step of cleaning slurry and residue remaining on the substrate after the step of removing Cu, You may have. Moreover, you may have a finishing process which performs the finishing polishing of Cu after the process of removing said Cu.

　前記除電はイオナイザー、軟Ｘ線の照射または紫外線の照射によって行われてもよい。ここで、除電において前記イオナイザーは基板の上方１００ｍｍ以内に配置されることが好ましい。さらに好適には前記イオナイザーは基板の上方３０ｍｍ以内に配置されることが好ましい。 The neutralization may be performed by ionizer, soft X-ray irradiation or ultraviolet irradiation. Here, in the charge removal, the ionizer is preferably disposed within 100 mm above the substrate. More preferably, the ionizer is preferably disposed within 30 mm above the substrate.

　また、上記半導体装置の製造方法において、前記バリアメタルはＴｉ、ＴｉＮ、ＴｉとＴｉＮの合金のいずれかであってもよく、前記層間絶縁膜はＣＦ膜（ＣＦ系の膜）であってもよい。また、前記バリアメタルはＴａ、ＴａＮおよびその合金であってもよい。 In the method of manufacturing a semiconductor device, the barrier metal may be Ti, TiN, an alloy of Ti and TiN, and the interlayer insulating film may be a CF film (CF-based film). . The barrier metal may be Ta, TaN, or an alloy thereof.

　また、別の観点からの本発明によれば、基板上にダマシン配線構造が形成された半導体装置を製造する製造システムであって、基板搬送経路上に、基板上に形成されたＣｕ膜を除去するＣｕ除去装置と、基板上に堆積したバリアメタルを除去するバリアメタル除去装置と、バリアメタル除去後に除電を行う除電装置と、基板上に残るスラリーおよび残渣物を洗浄する洗浄装置と、を順に配置した製造システムが提供される。 According to another aspect of the present invention, there is provided a manufacturing system for manufacturing a semiconductor device having a damascene wiring structure formed on a substrate, wherein a Cu film formed on the substrate is removed on the substrate transport path. Cu removing device for removing, barrier metal removing device for removing the barrier metal deposited on the substrate, neutralizing device for removing static electricity after removing the barrier metal, and a cleaning device for washing slurry and residue remaining on the substrate in order An arranged manufacturing system is provided.

　上記製造システムは、Ｃｕ除去後、Ｃｕ洗浄前に除電を行う除電装置と、Ｃｕ除去後に残るスラリーおよび残渣物を洗浄するＣｕ洗浄装置と、を備えていてもよい。 The manufacturing system may include a static eliminator that performs static elimination after Cu removal and before Cu cleaning, and a Cu cleaning apparatus that cleans slurry and residue remaining after Cu removal.

　また、上記製造システムは、Ｃｕ除去後に配線パターン溝以外に堆積されたＣｕの仕上研磨を行うＣｕ仕上装置を備えていてもよい。 Moreover, the manufacturing system may include a Cu finishing device that performs finish polishing of Cu deposited other than the wiring pattern groove after Cu removal.

　また、上記製造システムにおいて、前記除電装置は、イオナイザー、軟Ｘ線照射装置、紫外線照射装置のいずれかであってもよい。また、前記イオナイザーは基板搬送経路の上方１００ｍｍ以内に配置されてもよく、より好ましくは基板搬送経路の上方３０ｍｍ以内に配置されてもよい。 In the manufacturing system, the static eliminator may be an ionizer, a soft X-ray irradiator, or an ultraviolet irradiator. The ionizer may be disposed within 100 mm above the substrate transport path, and more preferably within 30 mm above the substrate transport path.

　上記製造システムにおいて、前記バリアメタルはＴｉ、ＴｉＮ、ＴｉとＴｉＮの合金のいずれかであってもよい。また、前記バリアメタルはＴａ、ＴａＮおよびその合金であってもよい。 In the manufacturing system, the barrier metal may be Ti, TiN, or an alloy of Ti and TiN. The barrier metal may be Ta, TaN, or an alloy thereof.

　本発明によれば、ダマシン配線構造を有する半導体装置において、ＣＭＰ法によるＣｕ配線への処理により発生するＣｕ配線の腐食（コロージョン）の発生を防止し、配線抵抗の上昇を抑制し、信頼性の担保された半導体装置の製造方法および半導体装置の製造システムが提供される。 According to the present invention, in a semiconductor device having a damascene wiring structure, it is possible to prevent occurrence of corrosion (corrosion) of Cu wiring caused by processing of Cu wiring by CMP, and to suppress an increase in wiring resistance, thereby improving reliability. A secured semiconductor device manufacturing method and a semiconductor device manufacturing system are provided.

本発明の実施の形態にかかる半導体装置を製造する製造システムを平面視で見た概略説明図である。It is the schematic explanatory drawing which looked at the manufacturing system which manufactures the semiconductor device concerning embodiment of this invention in planar view. Ｃｕ除去装置の説明図である。It is explanatory drawing of Cu removal apparatus. 除電装置の概略説明図であり、（ａ）は除電装置の側面図、（ｂ）は除電装置の平面図である。It is a schematic explanatory drawing of a static elimination apparatus, (a) is a side view of a static elimination apparatus, (b) is a top view of a static elimination apparatus. 洗浄装置の説明図である。It is explanatory drawing of a washing | cleaning apparatus. 本発明の実施の形態にかかる半導体装置の製造工程を説明するための基板の断面図であり、層間絶縁膜の表面に配線パターン溝が形成された状態を示している。It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state by which the wiring pattern groove | channel was formed in the surface of an interlayer insulation film. 本発明の実施の形態にかかる半導体装置の製造工程を説明するための基板の断面図であり、バリアメタル層とＣｕめっきシード層が層間絶縁膜上に連続して形成された状態を示している。It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state by which the barrier metal layer and Cu plating seed layer were continuously formed on the interlayer insulation film . 本発明の実施の形態にかかる半導体装置の製造工程を説明するための基板の断面図であり、Ｃｕ導電層が基板の表面全体に形成された状態を示している。It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state in which Cu conductive layer was formed in the whole surface of a board | substrate. 本発明の実施の形態にかかる半導体装置の製造工程を説明するための基板の断面図であり、層間絶縁膜の上方から配線パターン溝以外に堆積したＣｕ導電層が除去された状態を示している。It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state from which Cu conductive layer deposited other than the wiring pattern groove | channel was removed from the upper direction of an interlayer insulation film . 本発明の実施の形態にかかる半導体装置の製造工程を説明するための基板の断面図であり、層間絶縁膜の上方から配線パターン溝以外に堆積したバリアメタル層が除去された状態を示している。It is sectional drawing of the board | substrate for demonstrating the manufacturing process of the semiconductor device concerning embodiment of this invention, and has shown the state from which the barrier metal layer deposited other than the wiring pattern groove | channel was removed from the upper direction of an interlayer insulation film . 本発明の変形例にかかる半導体装置を製造する製造システムを平面視で見た概略説明図である。It is the schematic explanatory drawing which looked at the manufacturing system which manufactures the semiconductor device concerning the modification of this invention in planar view. Ｃｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ除去工程、純水洗浄工程、Ｔｉ除去工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線の観察結果である。It is the observation result of Cu wiring at the time of performing the Cu removal process by CMP method, the pure water washing | cleaning process, Ti removal process, and the washing | cleaning process by the washing | cleaning liquid containing an acid with respect to the board | substrate with which the Cu conductive layer was formed in the whole surface. Ｃｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ除去工程、純水洗浄工程、Ｔｉ除去工程、Ｔｉ除去工程後の除電工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線の観察結果である。When a Cu removal process by a CMP method, a pure water cleaning process, a Ti removal process, a charge removal process after the Ti removal process, and a cleaning process using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface. It is an observation result of Cu wiring.

　７…搬入口
　８…搬出口
　１０…Ｃｕ除去装置
　１１…回転台
　１２…弾性体
　１３…支持部材
　１４…パッド
　１５…保持部材
　１７…押圧機構
　２０…ＢＭ除去装置
　３０…除電装置
　３１…支持部材
　３２…対向電極
　３３…針状電極
　３４…円孔
　４０…洗浄装置
　４１…支持部材
　４１ａ…支持部
　４１ｂ…柱部
　４３…洗浄ブラシ対
　４３ａ…上ブラシ
　４３ｂ…下ブラシ
　５０…Ｃｕ仕上装置
　６０…除電装置
　７０…Ｃｕ洗浄装置
　１００…基板本体　　
　１０２…層間絶縁膜
　１０４…配線パターン溝
　１０５…ＢＭ膜
　１０７…Ｃｕめっきシード層
　１１０…Ｃｕ導電層
　１１５…Ｃｕ配線
　Ａ…半導体装置
　Ｓ、Ｓ’…製造システム
　Ｌ…搬送経路
　Ｗ…基板 DESCRIPTION OF SYMBOLS 7 ... Carry-in port 8 ... Carry-out port 10 ... Cu removal apparatus 11 ... Turntable 12 ... Elastic body 13 ... Supporting member 14 ... Pad 15 ... Holding member 17 ... Pressing mechanism 20 ... BM removal apparatus 30 ... Static elimination apparatus 31 ... Support member 32 ... counter electrode 33 ... acicular electrode 34 ... circular hole 40 ... cleaning device 41 ... support member 41a ... support part 41b ... column part 43 ... cleaning brush pair 43a ... upper brush 43b ... lower brush 50 ... Cu finishing device 60 ... static elimination device 70 ... Cu cleaning device 100 ... Substrate body
DESCRIPTION OF SYMBOLS 102 ... Interlayer insulating film 104 ... Wiring pattern groove | channel 105 ... BM film | membrane 107 ... Cu plating seed layer 110 ... Cu conductive layer 115 ... Cu wiring A ... Semiconductor device S, S '... Manufacturing system L ... Conveyance path W ... Substrate

　以下、本発明の実施の形態について図面を参照して説明する。なお、本明細書および図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

　図１は、本発明の実施の形態にかかる半導体装置Ａを製造する製造システムＳを平面視で見た概略説明図である。図１に示すように、製造システムＳには、基板Ｗを搬送する搬送経路Ｌが設けられている。搬送経路Ｌは製造システムＳ内に基板Ｗが搬入される搬入口７（上流）から、基板Ｗが製造システムＳから搬出される搬出口８（下流）までの基板搬送路であり、図示しない搬送アームによって搬送経路Ｌに沿って基板Ｗが搬送される。また、搬送経路Ｌ上には、その上流から下流に向かってＣＭＰ法によって基板Ｗの研磨を行うＣｕ除去装置１０、ＣＭＰ法によって基板Ｗの研磨を行うバリアメタル（以下、ＢＭとも表記）除去装置２０、例えばイオナイザーである除電装置３０および洗浄装置４０がこのような順序でもって設けられている。 FIG. 1 is a schematic explanatory view of a manufacturing system S for manufacturing a semiconductor device A according to an embodiment of the present invention as seen in a plan view. As shown in FIG. 1, the manufacturing system S is provided with a transport path L for transporting the substrate W. The transfer path L is a substrate transfer path from the carry-in port 7 (upstream) where the substrate W is carried into the manufacturing system S to the carry-out port 8 (downstream) where the substrate W is carried out from the production system S, and is not shown. The substrate W is transported along the transport path L by the arm. Further, on the transport path L, a Cu removing device 10 that polishes the substrate W by the CMP method from upstream to downstream, and a barrier metal (hereinafter also referred to as BM) removing device that polishes the substrate W by the CMP method. 20, for example, an ionizer 30 and a cleaning device 40 which are ionizers are provided in this order.

　図２は、ＣＭＰ法によって基板ＷのＣｕを除去するＣｕ除去装置１０の説明図である。図２に示すように、Ｃｕ除去装置１０内には、基板Ｗを研磨する略円板形状の回転台１１が設けられ、回転台１１はＣｕ除去装置１０の下部に設けられた弾性体１２を備える支持部材１３によって支持されている。また、回転台１１の上面には、その上面全体をほぼ覆うように、ＣＭＰ法を行うための略円形状のパッド１４が配置されている。回転台１１は図示しない駆動機構によって回転自在に構成されており、パッド１４も回転台１１の回転に合わせて一体的に回転する。 FIG. 2 is an explanatory diagram of the Cu removing apparatus 10 that removes Cu from the substrate W by the CMP method. As shown in FIG. 2, a substantially disk-shaped turntable 11 for polishing the substrate W is provided in the Cu removal apparatus 10, and the turntable 11 includes an elastic body 12 provided at a lower portion of the Cu removal apparatus 10. It is supported by the supporting member 13 provided. A substantially circular pad 14 for performing the CMP method is disposed on the upper surface of the turntable 11 so as to substantially cover the entire upper surface. The turntable 11 is configured to be rotatable by a drive mechanism (not shown), and the pad 14 also rotates integrally with the rotation of the turntable 11.

また、図２に示すように、回転台１１の上方には、基板Ｗを略円板形状の下面において保持する、例えば多孔質の樹脂であるパッキングフィルムを備えた保持部材１５が設置されており、水を浸透させ基板Ｗを吸着させることで基板Ｗを保持する構成となっている。保持部材１５には、保持部材１５を回転台１１に対して押し付けるように押圧力を加える押圧機構１７が接続されている。 Further, as shown in FIG. 2, a holding member 15 having a packing film made of, for example, a porous resin for holding the substrate W on the substantially disk-shaped lower surface is installed above the turntable 11. The substrate W is held by allowing water to penetrate and adsorbing the substrate W. The holding member 15 is connected to a pressing mechanism 17 that applies a pressing force so as to press the holding member 15 against the turntable 11.

図２に示すように構成されるＣｕ除去装置１０に基板Ｗが搬送された場合、基板Ｗは回転する保持部材１５に保持された状態で、押圧機構１７の稼動により回転している回転台１１（パッド１４）に研磨面を下向きにして押し付けられる。このとき、図示しない研磨剤（スラリー）供給機構から研磨剤（スラリー）が回転台１１上面（パッド１４上面）に所定の量供給される。回転する保持部材１５の下面に保持された基板Ｗが、回転するパッド１４に押し付けられることで、基板Ｗの研磨が行われる。なお、Ｃｕ除去装置１０と、ＢＭ除去装置２０の装置構成は同様のものとなっているため、ＢＭ除去装置２０の装置構成についての説明は省略する。ＢＭ除去装置２０においては、図２に示す構成と同様に構成されるＣＭＰ装置において、用いる研磨剤の種類・量や、保持部材１５および回転台１１の回転速度・押圧力等を変化させることにより、同様の構成であるＣＭＰ装置でもって、ＢＭ除去工程等の様々な研磨処理が可能となっている。 When the substrate W is transferred to the Cu removing apparatus 10 configured as shown in FIG. 2, the turntable 11 is rotated by the operation of the pressing mechanism 17 while the substrate W is held by the rotating holding member 15. The pad is pressed against the pad 14 with the polishing surface facing downward. At this time, a predetermined amount of abrasive (slurry) is supplied to the upper surface of the turntable 11 (upper surface of the pad 14) from an unillustrated abrasive (slurry) supply mechanism. The substrate W held on the lower surface of the rotating holding member 15 is pressed against the rotating pad 14, whereby the substrate W is polished. In addition, since the apparatus structure of Cu removal apparatus 10 and BM removal apparatus 20 is the same, description about the apparatus structure of BM removal apparatus 20 is abbreviate | omitted. In the BM removing apparatus 20, in the CMP apparatus configured similarly to the structure shown in FIG. 2, by changing the type and amount of abrasive used, the rotational speed and pressing force of the holding member 15 and the turntable 11, and the like. With a CMP apparatus having the same configuration, various polishing processes such as a BM removal process can be performed.

また、図３はイオナイザーである除電装置３０の概略説明図であり、図３（ａ）は除電装置３０の側面図、図３（ｂ）は除電装置３０の平面図である。図３に示すように、除電装置３０は、棒状の支持部材３１の両側に対向電極３２を離して配置し、支持部材３１の両側面に複数本の針状電極３３を所定の間隔で取り付けた構成になっている。対向電極３２には所定の間隔で円孔３４が形成されており、それら円孔３４の中心に針状電極３３がそれぞれ位置している。 3 is a schematic explanatory view of the static eliminator 30 that is an ionizer, FIG. 3A is a side view of the static eliminator 30, and FIG. 3B is a plan view of the static eliminator 30. As shown in FIG. 3, the static eliminator 30 is arranged by disposing the counter electrodes 32 on both sides of the rod-like support member 31 and attaching a plurality of needle-like electrodes 33 to both sides of the support member 31 at a predetermined interval. It is configured. Circular holes 34 are formed in the counter electrode 32 at predetermined intervals, and the needle-like electrodes 33 are located at the centers of the circular holes 34.

図３に示すように構成される除電装置３０においては、対向電極３２と針状電極３３との間に空気の絶縁破壊強度以上の電圧をかけることにより、除電装置３０近傍に＋イオンと－イオンを発生させることが可能である。このように除電装置３０近傍に＋イオンと－イオンを発生させた状態で、帯電した基板Ｗを近づける（干渉させる）ことにより、基板Ｗの除電が行われる。 In the static eliminator 30 configured as shown in FIG. 3, by applying a voltage higher than the dielectric breakdown strength of air between the counter electrode 32 and the needle electrode 33, + ions and − ions in the vicinity of the static eliminator 30. Can be generated. In this manner, the substrate W is neutralized by bringing the charged substrate W close (interfering) in a state where + ions and − ions are generated in the vicinity of the neutralization device 30.

また、図４は研磨後の基板Ｗの洗浄を行う洗浄装置４０の説明図である。図４に示すように洗浄装置４０においては、搬入された基板Ｗの周縁部三点を支持する支持部材４１が３箇所に設けられている。支持部材４１は略円板形状の支持部４１ａと支持部４１ａを支える柱部４１ｂから構成され、略円板形状の支持部４１ａは図示しない駆動機構によって回転自在に構成されている。洗浄装置４０に搬送された基板Ｗは、その周縁部三点が３つの支持部４１ａの周縁部とそれぞれ接触するように支持される。また、支持部４１ａの回転により、支持部４１ａの回転に伴い支持された基板Ｗも回転する構成となっている。 FIG. 4 is an explanatory diagram of a cleaning device 40 that cleans the substrate W after polishing. As shown in FIG. 4, in the cleaning apparatus 40, support members 41 that support three peripheral edge portions of the substrate W that has been carried in are provided at three locations. The support member 41 includes a substantially disc-shaped support portion 41a and a column portion 41b that supports the support portion 41a. The substantially disc-shaped support portion 41a is configured to be rotatable by a drive mechanism (not shown). The substrate W transported to the cleaning device 40 is supported such that the three peripheral edge portions thereof are in contact with the peripheral edge portions of the three support portions 41a. The substrate W supported by the rotation of the support portion 41a is also rotated by the rotation of the support portion 41a.

　また、図４に示すように、基板Ｗの上方および下方には、図示しないロール軸によって支持されるロール形状の洗浄ブラシ対４３（上ブラシ４３ａ、下ブラシ４３ｂ）が備えられており、洗浄ブラシ対４３は適宜基板Ｗの上面および下面に当接可能となっている。また、洗浄ブラシ対４３は、図示しないロール軸の回転により回転自在となっており、さらに、図示しないロール軸は移動自在に構成され、洗浄ブラシ対４３の移動により、基板の上面前面に上ブラシ４３ａが、下面の全面に下ブラシ４３ｂがそれぞれ当接できるような構成となっている。なお、図４に図示はしていないが、洗浄時には洗浄液供給機構から適宜所定の量の洗浄液が基板Ｗに対し供給される。ここで、洗浄液は例えば純水等でもよいが、クエン酸やシュウ酸等の酸を含む洗浄液であることがより好ましい。 Further, as shown in FIG. 4, above and below the substrate W, a pair of roll-shaped cleaning brushes 43 (upper brush 43a and lower brush 43b) supported by a roll shaft (not shown) are provided. The pair 43 can be brought into contact with the upper and lower surfaces of the substrate W as appropriate. Further, the cleaning brush pair 43 is rotatable by rotation of a roll shaft (not shown), and further, the roll shaft (not shown) is configured to be movable. 43a is configured such that the lower brush 43b can contact the entire lower surface. Although not shown in FIG. 4, a predetermined amount of cleaning liquid is appropriately supplied from the cleaning liquid supply mechanism to the substrate W during cleaning. Here, the cleaning liquid may be pure water or the like, but is more preferably a cleaning liquid containing an acid such as citric acid or oxalic acid.

　図４に示す洗浄装置４０に基板Ｗは搬送された場合には、基板Ｗは支持部材４１によって支持され、支持部４１ａの回転に伴って回転する。また、基板Ｗの上面および下面には回転する洗浄ブラシ対４３が当接させられ、洗浄液が供給された状態で基板Ｗを洗浄する。これにより、Ｃｕ除去装置１０およびＢＭ除去装置２０においてＣＭＰ法によって除去され基板Ｗ上に残るＣｕ残渣物やＢＭ残渣物および研磨剤（スラリー）が洗浄され、清浄化された基板Ｗが洗浄装置４０から搬出される。 When the substrate W is transported to the cleaning device 40 shown in FIG. 4, the substrate W is supported by the support member 41 and rotates as the support portion 41a rotates. Further, a rotating cleaning brush pair 43 is brought into contact with the upper and lower surfaces of the substrate W, and the substrate W is cleaned in a state where the cleaning liquid is supplied. Thus, the Cu residue, the BM residue, and the abrasive (slurry) that are removed by the CMP method in the Cu removing device 10 and the BM removing device 20 and remain on the substrate W are washed, and the cleaned substrate W is washed. It is carried out from.

以上、本発明の実施の形態にかかる製造システムＳと製造システムＳを構成する各装置の装置構成について図１～図４を参照して説明したが、以下には、製造システムＳとその前処理工程（製造システムＳに搬入されるまでに基板Ｗに行われる処理）と製造システムＳにおいて行われる基板処理について図５～図９を参照して説明する。 The manufacturing system S according to the embodiment of the present invention and the device configuration of each device constituting the manufacturing system S have been described above with reference to FIGS. 1 to 4. Hereinafter, the manufacturing system S and its pre-processing will be described. A process (a process performed on the substrate W before being carried into the manufacturing system S) and a substrate process performed in the manufacturing system S will be described with reference to FIGS.

図５～図９は、本発明の実施の形態にかかる半導体装置Ａの製造工程を示す説明図である。即ち、Ｓｉ等からなる半導体の基板Ｗにおいて、基板本体１００の上面にＣｕ配線が形成される過程を図示している。 FIG. 5 to FIG. 9 are explanatory views showing manufacturing steps of the semiconductor device A according to the embodiment of the present invention. That is, a process of forming a Cu wiring on the upper surface of the substrate body 100 in the semiconductor substrate W made of Si or the like is illustrated.

先ず、図５に示すように、例えば基板本体１００上に形成されたＣＦ膜等からなる層間絶縁膜１０２の表面に、配線パターン溝１０４が形成される。続いて、フォトリソグラフィにより層間絶縁膜１０２の上に形成された図示しないマスク材に配線パターンが形成される。さらに、反応性イオンエッチング（ＲＩＥ）により、層間絶縁膜１０２の表面に配線パターン溝１０４が形成され、マスク材は取り除かれる。 First, as shown in FIG. 5, a wiring pattern groove 104 is formed on the surface of an interlayer insulating film 102 made of, for example, a CF film formed on the substrate body 100. Subsequently, a wiring pattern is formed on a mask material (not shown) formed on the interlayer insulating film 102 by photolithography. Furthermore, the wiring pattern groove 104 is formed on the surface of the interlayer insulating film 102 by reactive ion etching (RIE), and the mask material is removed.

次に、図６に示すように、配線パターン溝１０４の内面を被覆するように、バリアメタル（以下、ＢＭと呼称する）膜１０５とＣｕめっきシード層１０７が層間絶縁膜１０２上に連続して形成される。ＢＭ膜１０５は、層間絶縁膜１０２の全面にＴｉＮ膜をスパッタリングして形成される。ＢＭ膜１０５は、Ｔｉ膜、Ｔｉ化合物膜またはＴｉ合金膜の単層膜、もしくは、Ｔａ膜、ＴａＮ膜またはＴａ合金膜の単層膜やこれらの２種以上の積層膜である。また、Ｃｕめっきシード層１０７は、例えばスパッタリングにより形成される。 Next, as shown in FIG. 6, a barrier metal (hereinafter referred to as BM) film 105 and a Cu plating seed layer 107 are continuously formed on the interlayer insulating film 102 so as to cover the inner surface of the wiring pattern groove 104. It is formed. The BM film 105 is formed by sputtering a TiN film on the entire surface of the interlayer insulating film 102. The BM film 105 is a single layer film of a Ti film, a Ti compound film, or a Ti alloy film, or a single layer film of a Ta film, a TaN film, or a Ta alloy film, or a laminated film of two or more of these. The Cu plating seed layer 107 is formed by sputtering, for example.

次に、図７に示すように、Ｃｕ導電層１１０が、Ｃｕめっきシード層１０７の上から配線パターン溝１０４を埋め込むように、基板Ｗの表面全体に形成される。Ｃｕ導電層１１０は、純Ｃｕに限らずＣｕ合金であってもよく、合金Ｃｕめっき、スパッタリング等で形成される。なお、Ｃｕ導電層１１０の形成により、Ｃｕめっきシード層１０７は、Ｃｕ導電層１１０に一体化される。 Next, as shown in FIG. 7, a Cu conductive layer 110 is formed on the entire surface of the substrate W so as to fill the wiring pattern groove 104 from above the Cu plating seed layer 107. The Cu conductive layer 110 is not limited to pure Cu but may be a Cu alloy, and is formed by alloy Cu plating, sputtering, or the like. The Cu plating seed layer 107 is integrated with the Cu conductive layer 110 by forming the Cu conductive layer 110.

次に、図８に示すように、Ｃｕ導電層１１０の表層部分、即ち配線パターン溝１０４の内部にあるＣｕ導電層１１０を除いたＣｕ導電層１１０がＣＭＰ法により除去される。こうして、配線溝１０４の内部にＣｕ導電層１１０が残され、配線溝１０４以外の基板表面がＢＭ層１０５によって覆われた状態となる。 Next, as shown in FIG. 8, the surface of the Cu conductive layer 110, that is, the Cu conductive layer 110 excluding the Cu conductive layer 110 inside the wiring pattern groove 104 is removed by the CMP method. Thus, the Cu conductive layer 110 is left inside the wiring groove 104, and the substrate surface other than the wiring groove 104 is covered with the BM layer 105.

次に、図９に示すように、配線パターン溝１０４の内部にあるＣｕ導電層１１０とＢＭ層１０５の部分を残して、層間絶縁膜１０２の上方からＢＭ層１０５がＣＭＰ法により除去される。こうして、配線パターン溝１０４の内部にＢＭ層１０５で囲まれた状態でＣｕ配線１１５が形成され、ダマシン配線構造を有する半導体装置Ａが製造される。 Next, as shown in FIG. 9, the BM layer 105 is removed from above the interlayer insulating film 102 by the CMP method, leaving the portions of the Cu conductive layer 110 and the BM layer 105 inside the wiring pattern groove 104. Thus, the Cu wiring 115 is formed in the wiring pattern groove 104 surrounded by the BM layer 105, and the semiconductor device A having the damascene wiring structure is manufactured.

ここで、図８、図９等に示すＣｕ導電層１１０とＢＭ層１０５のＣＭＰ法による除去は図１に示したＣｕ除去装置１０、ＢＭ除去装置２０等を備えた製造システムＳによって行われる。そこで、以下には図面を参照して、製造システムＳにおいて行われる基板Ｗに対する処理（図９に示したＣｕ導電層１１０およびＢＭ層１０５の除去）について説明する。 Here, the removal of the Cu conductive layer 110 and the BM layer 105 shown in FIGS. 8 and 9 by the CMP method is performed by the manufacturing system S including the Cu removal device 10 and the BM removal device 20 shown in FIG. In the following, a process for the substrate W (removal of the Cu conductive layer 110 and the BM layer 105 shown in FIG. 9) performed in the manufacturing system S will be described with reference to the drawings.

図１に示す製造システムＳにおいて、上述した図５～図７において説明する工程でもって作製されるＣｕ導電層１１０が表面全体に形成された基板Ｗが搬入口７から搬入される。そして、搬入口７から搬入された基板Ｗは、搬送経路Ｌに沿って搬送され、先ず、Ｃｕ除去装置１０においてＣＭＰ法によるＣｕの除去が行われる。即ち、図７に示す状態で基板Ｗ上に堆積しているＣｕ導電層１１０の研磨が行われ、図８に示すように、配線パターン溝１０４以外に堆積したＣｕが除去され、配線パターン溝１０４内部にＣｕ導電層１１０が残留し、配線パターン溝１０４以外の基板表面にはＢＭ層１０５が堆積された状態となる。 In the manufacturing system S shown in FIG. 1, the substrate W on which the entire surface of the Cu conductive layer 110 manufactured by the steps described in FIGS. 5 to 7 is formed is carried in from the carry-in entrance 7. Then, the substrate W carried in from the carry-in entrance 7 is carried along the carrying path L, and first, Cu is removed by the CMP method in the Cu removing apparatus 10. That is, the Cu conductive layer 110 deposited on the substrate W in the state shown in FIG. 7 is polished, and the Cu deposited in addition to the wiring pattern groove 104 is removed as shown in FIG. The Cu conductive layer 110 remains inside, and the BM layer 105 is deposited on the substrate surface other than the wiring pattern groove 104.

次いで、基板ＷはＢＭ除去装置２０に搬送される。ＢＭ除去装置２０においては、配線パターン溝１０４内部にＣｕ導電層１１０を囲むように残留するＢＭ層以外のＢＭ層１０５がＣＭＰ法により除去される。そして、図９に示すように配線パターン溝１０４以外に堆積する部分のＢＭ層１０５は研磨され、基板Ｗの表面にはＢＭ層１０５、Ｃｕ導電層１１０と層間絶縁膜１０２が表面に露出した状態となる。 Next, the substrate W is transferred to the BM removal apparatus 20. In the BM removing apparatus 20, the BM layer 105 other than the BM layer remaining inside the wiring pattern groove 104 so as to surround the Cu conductive layer 110 is removed by the CMP method. Then, as shown in FIG. 9, the portion of the BM layer 105 deposited other than the wiring pattern groove 104 is polished, and the BM layer 105, the Cu conductive layer 110 and the interlayer insulating film 102 are exposed on the surface of the substrate W. It becomes.

ここで、半導体装置Ａの製造工程においては、図９に示すように、Ｃｕ導電層１１０とＢＭ層１０５は基板Ｗ内において隣接して成膜されている。ここで、例えば純ＣｕであるＣｕ導電層１１０と、例えば純ＴｉであるＢＭ層１０５との間には、両金属間のイオン化傾向が異なることにより、両者間で電子の移動が生じ、いわゆる電池の状態となり、Ｃｕ配線１１５に腐食が生じてしまうこととなる。 Here, in the manufacturing process of the semiconductor device A, the Cu conductive layer 110 and the BM layer 105 are formed adjacent to each other in the substrate W as shown in FIG. Here, between the Cu conductive layer 110 made of, for example, pure Cu and the BM layer 105 made of, for example, pure Ti, the ionization tendency between the two metals is different, so that the movement of electrons occurs between the two, so-called battery. Thus, the Cu wiring 115 is corroded.

加えて、上述したようにＣｕ除去装置１０およびＢＭ除去装置２０においてＣＭＰ法を用いた研磨が行われる場合、図２を参照して上述したように、基板Ｗを保持部材１５によって固定し、保持部材１５に基板Ｗを固定した状態で研磨剤を供給すると共に、基板Ｗをパッド１４に押し付けながら回転させることで研磨が行われる。このとき、基板Ｗとパッド１４との摩擦によって研磨が行われるため、基板Ｗには摩擦によって生じる静電気が帯電する。 In addition, when polishing using the CMP method is performed in the Cu removing device 10 and the BM removing device 20 as described above, the substrate W is fixed and held by the holding member 15 as described above with reference to FIG. Polishing is performed by supplying the abrasive with the substrate W fixed to the member 15 and rotating the substrate W while pressing it against the pad 14. At this time, since the polishing is performed by the friction between the substrate W and the pad 14, the substrate W is charged with static electricity generated by the friction.

基板Ｗに摩擦によって生じた静電気が帯電したままの状態では、Ｃｕ導電層１１０とＢＭ層１０５との間での電子の移動がさらに促進され、腐食が進行してしまう。さらに、ＣＭＰ法を用いた研磨を行った場合、研磨時に発生した残渣物や研磨剤（スラリー）等を洗浄する洗浄工程を行う必要があるが、その際に残渣物等を金属酸化物として洗浄処理するために酸を用いた洗浄液が用いられるため、上記Ｃｕ配線１１５の腐食は洗浄によってより促進されてしまう。 In a state where static electricity generated by friction on the substrate W remains charged, the movement of electrons between the Cu conductive layer 110 and the BM layer 105 is further promoted, and corrosion progresses. In addition, when polishing using the CMP method is performed, it is necessary to perform a cleaning process for cleaning residues and abrasives (slurry) generated during polishing. At that time, the residues and the like are cleaned as a metal oxide. Since a cleaning solution using an acid is used for the treatment, the corrosion of the Cu wiring 115 is further promoted by the cleaning.

そこで、本実施の形態にかかる製造システムＳにおいては、製造工程中に基板Ｗに生じた電気や、ＣＭＰ法を用いて基板Ｗの研磨を行った際に研磨時の摩擦によって基板Ｗに帯電する静電気等を取り除くために、Ｃｕ除去装置１０、ＢＭ除去装置２０において研磨処理された基板Ｗは、図３に示した例えばイオナイザーである除電装置３０に搬送され、除電装置３０に、帯電した基板Ｗを干渉させることで、基板Ｗの除電が行われる。なお、基板Ｗの除電を行う場合に、除電装置３０を基板Ｗの上方１００ｍｍ以内に配置し除電を行うことが好ましく、さらに好適には基板Ｗの上方３０ｍｍ以内に配置することが望ましい。また、除電装置３０として例えばイオナイザーを図３に例示して説明したが、これに限られるものではなく、基板Ｗの除電を行うことが可能な装置であればよい。他種の除電装置３０としては、例えば軟Ｘ線照射装置や紫外線照射装置等が挙げられる。 Therefore, in the manufacturing system S according to the present embodiment, when the substrate W is polished using the electricity generated on the substrate W during the manufacturing process or using the CMP method, the substrate W is charged by friction during polishing. In order to remove static electricity or the like, the substrate W polished in the Cu removing device 10 and the BM removing device 20 is transferred to the charge removing device 30 which is, for example, an ionizer shown in FIG. 3, and the charged substrate W is transferred to the charge removing device 30. Makes the substrate W neutralize. In addition, when performing static elimination of the board | substrate W, it is preferable to arrange | position the static elimination apparatus 30 within 100 mm above the substrate W, and it is desirable to arrange | position within 30 mm above the board | substrate W more suitably. Further, for example, an ionizer is illustrated as an example of the charge removal device 30 in FIG. 3, but the present invention is not limited to this, and any device that can remove the substrate W may be used. Examples of the other types of static eliminating devices 30 include a soft X-ray irradiation device and an ultraviolet irradiation device.

続いて、除電された基板Ｗは洗浄装置４０に搬送される。Ｃｕ除去装置１０およびＢＭ除去装置２０において除去（研磨）されたＣｕやＢＭはスラリー状の残渣物として基板Ｗに付着した状態となり、また、研磨に用いられた研磨剤（スラリー）も基板Ｗに付着した状態で残る。そこで、洗浄装置４０においては、例えばクエン酸やシュウ酸等の酸を含む洗浄液を用いて上記残渣物やスラリーが洗浄され、基板Ｗが清浄化される。そして清浄化された基板Ｗは搬出口８を通じて製造システムＳの外部へ搬出される。このようにして、Ｃｕ配線への腐食の発生を抑制させたダマシン配線構造である半導体装置Ａが製造される。 Subsequently, the discharged substrate W is transported to the cleaning device 40. Cu or BM removed (polished) in the Cu removing device 10 and the BM removing device 20 is attached to the substrate W as a slurry-like residue, and the polishing agent (slurry) used for polishing is also applied to the substrate W. It remains attached. Therefore, in the cleaning device 40, the residue and the slurry are cleaned using a cleaning liquid containing an acid such as citric acid or oxalic acid, and the substrate W is cleaned. Then, the cleaned substrate W is carried out of the manufacturing system S through the carry-out port 8. Thus, the semiconductor device A having a damascene wiring structure in which the occurrence of corrosion on the Cu wiring is suppressed is manufactured.

以上説明したように、図１～図４を参照して説明した製造システムＳにおいて、図５～図７に説明した工程でもって作製されるＣｕ導電層１１０が表面全体に形成された基板Ｗに対し、図８に示した工程であるＣｕ導電層１１０の除去、図９に示した工程であるＢＭ層１０５の除去が行われ、配線パターン溝１０４の内部にＢＭ層１０５で囲まれた状態でＣｕ配線１１５が形成された半導体装置Ａが製造される。このとき、Ｃｕ導電層１１０およびＢＭ層１０５のＣＭＰ法による研磨・除去工程後、かつ、研磨・除去工程において発生した残渣物等の洗浄前において除電装置３０による除電工程が基板Ｗに対し行われる。 As described above, in the manufacturing system S described with reference to FIGS. 1 to 4, the Cu conductive layer 110 manufactured by the steps described in FIGS. 5 to 7 is formed on the substrate W on the entire surface. On the other hand, the Cu conductive layer 110 is removed as shown in FIG. 8 and the BM layer 105 is removed as shown in FIG. 9, and the wiring pattern groove 104 is surrounded by the BM layer 105. The semiconductor device A in which the Cu wiring 115 is formed is manufactured. At this time, after the polishing / removal process by the CMP method of the Cu conductive layer 110 and the BM layer 105 and before the cleaning of the residues generated in the polishing / removal process, the neutralization process by the static eliminator 30 is performed on the substrate W. .

これら除電工程を行うことにより、Ｃｕ導電層１１０とＢＭ層１０５のイオン化傾向の差によって両金属膜（Ｃｕ導電層とＢＭ層）の間での電子の移動によって生じるＣｕ配線の腐食が抑制される。さらには、Ｃｕ配線１１５の腐食が、ＣＭＰ法による基板Ｗの静電気の帯電や、洗浄時に用いられる酸の基板Ｗへの付着によって促進されることを防止することができる。その結果、配線（Ｃｕ配線１１５）抵抗の上昇が抑制され、信頼性の担保された半導体装置を製造することが可能となる。 By performing these static elimination steps, corrosion of Cu wiring caused by the movement of electrons between both metal films (Cu conductive layer and BM layer) due to the difference in ionization tendency between Cu conductive layer 110 and BM layer 105 is suppressed. . Furthermore, it is possible to prevent the corrosion of the Cu wiring 115 from being promoted by electrostatic charging of the substrate W by the CMP method or adhesion of an acid used during cleaning to the substrate W. As a result, an increase in the resistance of the wiring (Cu wiring 115) is suppressed, and it becomes possible to manufacture a semiconductor device with guaranteed reliability.

以上、本発明の実施の形態の一例を説明したが、本発明は図示の形態に限定されない。当業者であれば、特許請求の範囲に記載された思想の範疇において、各種の変更例または修正例に想到し得ることは明らかであり、それらについても当然に本発明の技術的範囲に属するものと了解される。 As mentioned above, although an example of embodiment of this invention was demonstrated, this invention is not limited to the form of illustration. It is obvious that those skilled in the art can come up with various changes and modifications within the scope of the idea described in the claims, and these naturally belong to the technical scope of the present invention. It is understood.

以下、本発明の変形例にかかる製造システムＳ’について図面を参照して説明する。図１０は本発明の変形例にかかる製造システムＳ’を平面視で見た概略説明図である。なお、図１０および以下の説明において上記実施の形態にかかる製造システムＳと同様の構成要素については同一の符号を用いて示し、その説明については省略する。 Hereinafter, a manufacturing system S ′ according to a modification of the present invention will be described with reference to the drawings. FIG. 10 is a schematic explanatory view of the manufacturing system S ′ according to the modification of the present invention as seen in a plan view. In addition, in FIG. 10 and the following description, about the component similar to the manufacturing system S concerning the said embodiment, it shows using the same code | symbol, and abbreviate | omits about the description.

図１０に示すように、製造システムＳ’において搬送経路Ｌ上には、その上流から下流に向かってＣＭＰ法によって基板Ｗの研磨を行うＣｕ除去装置１０、ＣＭＰ法によって仕上研磨を行うＣｕ仕上装置５０、例えばイオナイザーである除電装置６０、ＣＭＰ法による研磨によって発生したＣｕ残渣物等を洗浄するＣｕ洗浄装置７０、ＣＭＰ法によって研磨を行うＢＭ除去装置２０、除電装置３０およびＣＭＰ法による研磨によって発生したＢＭ残渣物等を洗浄する洗浄装置４０がこのような順序でもって設けられている。 As shown in FIG. 10, on the transport path L in the manufacturing system S ′, a Cu removing device 10 that polishes the substrate W from the upstream toward the downstream by the CMP method, and a Cu finishing device that performs the finish polishing by the CMP method. 50, for example, a static elimination device 60 that is an ionizer, a Cu cleaning device 70 that cleans Cu residues generated by polishing by the CMP method, a BM removal device 20 that performs polishing by the CMP method, a static elimination device 30, and the polishing by the CMP method The cleaning device 40 for cleaning the BM residue and the like is provided in this order.

即ち、本変形例は、上記実施の形態で説明したＣｕ除去装置１０によるＣｕ除去工程とＢＭ除去装置２０によるＢＭ除去工程との間に、Ｃｕ仕上装置５０によるＣｕ仕上工程、除電装置６０による除電工程およびＣｕ洗浄装置７０によるＣｕ洗浄工程を加えた構成となっている。そこで、以下では、上記実施の形態の説明において説明していないＣｕ仕上工程、Ｃｕ洗浄工程およびＣｕ仕上工程とＣｕ洗浄工程との間において行われる除電工程について説明する。なお、Ｃｕ仕上工程を行うＣｕ仕上装置５０の装置構成は上記図２を参照して説明したＣｕ除去装置と同様（ＣＭＰ法を用いた研磨装置）の構成であり、Ｃｕ洗浄工程を行うＣｕ洗浄装置７０の装置構成は上記図４を参照して説明した洗浄装置４０と同様の構成であり、除電装置６０の装置構成は、上記図３を参照して説明した除電装置３０と同様の構成であるため、その装置構成についての説明はここでは省略する。 That is, in this modification, the Cu finishing process by the Cu finishing apparatus 50 and the static elimination by the static eliminating apparatus 60 are performed between the Cu removing process by the Cu removing apparatus 10 and the BM removing process by the BM removing apparatus 20 described in the above embodiment. The process and the Cu cleaning process by the Cu cleaning apparatus 70 are added. Therefore, hereinafter, a Cu finishing process, a Cu cleaning process, and a static elimination process performed between the Cu finishing process and the Cu cleaning process, which are not described in the description of the above embodiment, will be described. The apparatus configuration of the Cu finishing apparatus 50 that performs the Cu finishing process is the same as that of the Cu removing apparatus described with reference to FIG. 2 (a polishing apparatus using the CMP method), and the Cu cleaning process that performs the Cu cleaning process. The apparatus configuration of the apparatus 70 is the same as that of the cleaning apparatus 40 described with reference to FIG. 4, and the apparatus configuration of the static elimination apparatus 60 is the same as that of the static elimination apparatus 30 described with reference to FIG. Therefore, description of the device configuration is omitted here.

図１０に示す製造システムＳ’においては、Ｃｕ除去装置１０においてＣｕ導電層１１０の除去が行われた基板Ｗは、Ｃｕ仕上装置５０に搬送され、再度ＣＭＰ法による基板Ｗの研磨が行われる。Ｃｕ仕上装置５０における基板Ｗの研磨は、Ｃｕ除去装置１０における研磨に比べより精密な条件でもって研磨が行われるように設定される。即ち、Ｃｕ除去装置１０における研磨の後に、Ｃｕ仕上装置５０におけるＣｕ仕上工程（仕上げ用研磨）を行うことで、配線パターン溝１０４にのみＣｕ導電層１１０（Ｃｕ配線１１５）が残り、配線パターン溝１０４が形成されている部分以外の層間絶縁膜１０２およびＢＭ層１０５の上面にＣｕ導電層１１０が全く残留していない基板Ｗが得られる。 In the manufacturing system S ′ shown in FIG. 10, the substrate W from which the Cu conductive layer 110 has been removed by the Cu removing apparatus 10 is transferred to the Cu finishing apparatus 50, and the substrate W is polished again by the CMP method. The polishing of the substrate W in the Cu finishing device 50 is set so that the polishing is performed under more precise conditions than the polishing in the Cu removing device 10. That is, by performing the Cu finishing process (finishing polishing) in the Cu finishing device 50 after polishing in the Cu removing device 10, the Cu conductive layer 110 (Cu wiring 115) remains only in the wiring pattern groove 104, and the wiring pattern groove. A substrate W in which the Cu conductive layer 110 does not remain at all on the upper surfaces of the interlayer insulating film 102 and the BM layer 105 other than the portion where the 104 is formed is obtained.

次に、Ｃｕ仕上装置５０によって研磨された基板Ｗは、例えばイオナイザーである除電装置６０に搬送される。Ｃｕ除去装置１０、Ｃｕ仕上装置５０において用いられるＣＭＰ法とは、図２を参照して上述したように、基板Ｗを保持部材１５によって固定し、保持部材１５に基板Ｗを固定した状態で研磨剤（スラリー）を供給すると共に、基板Ｗをパッド１４に押し付けながら回転させることで、研磨を行う方法である。このとき、基板Ｗとパッド１４との摩擦によって研磨が行われるため、基板Ｗには摩擦によって生じる静電気が帯電する。そこで、Ｃｕ仕上装置５０において研磨処理された基板Ｗは、除電装置６０に搬送され、除電装置６０に帯電した基板Ｗを干渉させることで、基板Ｗの除電が行われる。 Next, the substrate W polished by the Cu finishing device 50 is transported to a static eliminator 60 that is, for example, an ionizer. The CMP method used in the Cu removing apparatus 10 and the Cu finishing apparatus 50 is the polishing with the substrate W fixed by the holding member 15 and the substrate W fixed to the holding member 15 as described above with reference to FIG. In this method, polishing is performed by supplying an agent (slurry) and rotating the substrate W while pressing it against the pad 14. At this time, since the polishing is performed by the friction between the substrate W and the pad 14, the substrate W is charged with static electricity generated by the friction. Therefore, the substrate W polished in the Cu finishing device 50 is transported to the static eliminator 60, and the charged substrate W is caused to interfere with the static eliminator 60, so that the substrate W is neutralized.

次いで、除電装置６０において除電された基板ＷはＣｕ洗浄装置７０に搬送される。Ｃｕ除去装置１０およびＣｕ仕上装置５０において除去（研磨）されたＣｕはスラリー状の残渣物として基板Ｗに付着した状態となる。そこで、Ｃｕ洗浄装置７０においては、例えばクエン酸やシュウ酸等の酸を含む洗浄液を用いて上記スラリー状の残渣物や研磨後に残る研磨剤（スラリー）等が洗浄され、基板Ｗが清浄化される。 Next, the substrate W that has been neutralized in the static eliminator 60 is transferred to the Cu cleaning device 70. Cu removed (polished) in the Cu removing device 10 and the Cu finishing device 50 is attached to the substrate W as a slurry residue. Therefore, in the Cu cleaning apparatus 70, for example, the slurry-like residue and the polishing agent (slurry) remaining after polishing are cleaned using a cleaning liquid containing an acid such as citric acid or oxalic acid, and the substrate W is cleaned. The

Ｃｕ洗浄装置７０において清浄化された基板Ｗは、ＢＭ除去装置２０に搬送され、上記実施の形態と同様にＢＭ層１０５の除去（研磨）は行われる。そして、除電装置３０において基板Ｗの除電が行われた後、ＢＭ除去装置２０における研磨において発生したＢＭの残渣物や研磨後に残る研磨剤（スラリー）等が洗浄装置４０において洗浄され、清浄化された基板Ｗは搬出口８を通じて製造システムＳ’の外部へ搬出される。 The substrate W cleaned in the Cu cleaning device 70 is transferred to the BM removal device 20, and the removal (polishing) of the BM layer 105 is performed in the same manner as in the above embodiment. After the neutralization of the substrate W in the static eliminator 30, the BM residue generated in the polishing in the BM removal apparatus 20 and the abrasive (slurry) remaining after the polishing are cleaned and cleaned in the cleaning apparatus 40. The substrate W is unloaded from the manufacturing system S ′ through the unloading port 8.

以上、図１０を参照して説明した本発明の変形例にかかる製造システムＳ’においては、Ｃｕ除去工程後にＣｕ仕上工程を行っていることにより、配線溝１０４の内部に残留させるＣｕ（即ち、Ｃｕ配線１１５）以外のＣｕ導電層１１０の除去が極めて高精度でもって行われる。また、Ｃｕ除去工程およびＣｕ仕上工程の後に基板Ｗの除電工程・洗浄工程を行い、さらにＢＭ除去工程の後に基板Ｗの除電工程・洗浄工程を行うこととしており、ＣＭＰ法による基板Ｗへの静電気の帯電や、帯電した基板Ｗへの洗浄時に用いられる酸の付着などによるＣｕ配線１１５の腐食が効率的に防止される。これにより、配線抵抗の上昇が抑制され、信頼性の担保された半導体装置が得られる。 As described above, in the manufacturing system S ′ according to the modified example of the present invention described with reference to FIG. 10, the Cu finishing process is performed after the Cu removing process, so that the Cu remaining inside the wiring trench 104 (that is, Removal of the Cu conductive layer 110 other than the Cu wiring 115) is performed with extremely high accuracy. In addition, the static elimination process and the cleaning process of the substrate W are performed after the Cu removal process and the Cu finishing process, and the static elimination process and the cleaning process of the substrate W are performed after the BM removal process. The Cu wiring 115 is effectively prevented from being corroded due to the charging of the metal and the adhesion of the acid used for cleaning the charged substrate W. As a result, an increase in wiring resistance is suppressed, and a semiconductor device with guaranteed reliability can be obtained.

　本発明の実施例として、Ｃｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ（Ｃｕ導電層）除去工程、Ｔｉ（ＢＭ層）除去工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線（比較例）と、Ｃｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ（Ｃｕ導電層）除去工程、純水洗浄工程、Ｔｉ（ＢＭ層）除去工程、Ｔｉ除去工程後の除電工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線（実施例）のそれぞれを電子顕微鏡（ＳＥＭ）によって観察し、比較を行った。 As an embodiment of the present invention, a Cu (Cu conductive layer) removing step by a CMP method, a Ti (BM layer) removing step, and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface. Cu wiring (comparative example) and a substrate on which the Cu conductive layer is formed on the entire surface, a Cu (Cu conductive layer) removing step by CMP, a pure water cleaning step, a Ti (BM layer) removing step, Each of the Cu wirings (Examples) in the case of performing the static elimination process after the Ti removal process and the cleaning process using the cleaning solution containing an acid was observed and compared with an electron microscope (SEM).

　図１１は、Ｃｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ（Ｃｕ導電層）除去工程、Ｔｉ（ＢＭ層）除去工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線（比較例）の観察結果である。
　一方、図１２はＣｕ導電層が表面全体に形成された基板に対し、ＣＭＰ法によるＣｕ（Ｃｕ導電層）除去工程、純水洗浄工程、Ｔｉ（ＢＭ層）除去工程、Ｔｉ除去工程後の除電工程および酸を含む洗浄液による洗浄工程を行った場合のＣｕ配線（実施例）の観察結果である。このとき、前記除電工程はイオナイザーを用いて行い、イオナイザーは基板の上方３０ｍｍの位置に配置した。 FIG. 11 shows a case where a Cu (Cu conductive layer) removing step, a Ti (BM layer) removing step and a cleaning step using an acid-containing cleaning solution are performed on a substrate having a Cu conductive layer formed on the entire surface. It is an observation result of Cu wiring (comparative example).
On the other hand, FIG. 12 shows a static electricity removal after a Cu (Cu conductive layer) removing step, a pure water cleaning step, a Ti (BM layer) removing step, and a Ti removing step by a CMP method on a substrate having a Cu conductive layer formed on the entire surface. It is an observation result of Cu wiring (Example) at the time of performing the cleaning process by the cleaning liquid containing a process and an acid. At this time, the static elimination step was performed using an ionizer, and the ionizer was disposed at a position 30 mm above the substrate.

　図１１と図１２のＣｕ配線を比較した場合、特にＣｕ配線と周囲のＢＭ層との境界部分（界面）において、図１１のＣｕ配線の方に顕著な腐食が観察された。即ち、Ｃｕ除去工程およびＢＭ除去工程後に除電工程を行うことで、Ｃｕ配線の腐食が抑制されたことが分かった。 When comparing the Cu wirings of FIG. 11 and FIG. 12, remarkable corrosion was observed on the Cu wiring of FIG. 11, particularly at the boundary portion (interface) between the Cu wiring and the surrounding BM layer. That is, it was found that the corrosion of the Cu wiring was suppressed by performing the charge removal step after the Cu removal step and the BM removal step.

　本発明は、半導体装置の製造方法および半導体装置の製造システムに有用である。 The present invention is useful for a semiconductor device manufacturing method and a semiconductor device manufacturing system.

Claims (15)

ダマシン配線構造を有する半導体装置の製造方法であって、
基板上の層間絶縁膜に形成される配線パターン溝にバリアメタル膜およびＣｕ膜が形成された状態で、ケミカルメカニカルポリッシングによって配線パターン溝以外に堆積したＣｕを除去する工程と、
配線パターン溝以外に堆積したバリアメタルをケミカルメカニカルポリッシングによって除去する工程と、
前記バリアメタルを除去する工程後、除電する工程と、
基板上に残るスラリーおよび残渣物を洗浄する工程と、を有する半導体装置の製造方法。 A method of manufacturing a semiconductor device having a damascene wiring structure,
A step of removing Cu deposited other than the wiring pattern groove by chemical mechanical polishing in a state in which the barrier metal film and the Cu film are formed in the wiring pattern groove formed in the interlayer insulating film on the substrate;
Removing the barrier metal deposited other than the wiring pattern groove by chemical mechanical polishing;
After removing the barrier metal, removing electricity,
Cleaning the slurry and residue remaining on the substrate. 前記Ｃｕを除去する工程後、前記Ｃｕ洗浄工程前に除電する工程と、前記Ｃｕを除去する工程後に基板上に残るスラリーおよび残渣物を洗浄するＣｕ洗浄工程と、を有する請求項１に記載の半導体装置の製造方法。 2. The method according to claim 1, further comprising: a step of removing electricity after the step of removing Cu and before the step of cleaning Cu, and a step of cleaning Cu for cleaning slurry and residue remaining on the substrate after the step of removing Cu. A method for manufacturing a semiconductor device. 前記Ｃｕを除去する工程後、Ｃｕの仕上研磨を行う仕上工程を有する、請求項１に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, further comprising a finishing step of performing a finish polishing of Cu after the step of removing Cu. 前記除電はイオナイザー、軟Ｘ線の照射または紫外線の照射によって行われる、請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the charge removal is performed by an ionizer, soft X-ray irradiation, or ultraviolet irradiation. 除電において前記イオナイザーは基板の上方１００ｍｍ以内に配置される、請求項４に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 4, wherein the ionizer is disposed within 100 mm above the substrate in the charge removal. 除電において前記イオナイザーは基板の上方３０ｍｍ以内に配置される、請求項４に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 4, wherein the ionizer is disposed within 30 mm above the substrate in the charge removal. 前記バリアメタルはＴｉ、ＴｉＮ、ＴｉとＴｉＮの合金のいずれかである、請求項１に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein the barrier metal is any one of Ti, TiN, and an alloy of Ti and TiN. 前記層間絶縁膜はＣＦ膜である、請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a CF film. 基板上にダマシン配線構造が形成された半導体装置を製造する製造システムであって、
基板搬送経路上に、
基板上に形成されたＣｕ膜を除去するＣｕ除去装置と、
基板上に堆積したバリアメタルを除去するバリアメタル除去装置と、
バリアメタル除去後に除電を行う除電装置と、
基板上に残るスラリーおよび残渣物を洗浄する洗浄装置と、を順に配置した製造システム。 A manufacturing system for manufacturing a semiconductor device having a damascene wiring structure formed on a substrate,
On the board transfer path,
A Cu removing device for removing a Cu film formed on the substrate;
A barrier metal removing device for removing the barrier metal deposited on the substrate;
A static eliminator that removes static electricity after removing the barrier metal;
The manufacturing system which has arrange | positioned in order the washing | cleaning apparatus which wash | cleans the slurry and residue which remain | survive on a board | substrate. Ｃｕ除去後、Ｃｕ洗浄前に除電を行う除電装置と、Ｃｕ除去後に残るスラリーおよび残渣物を洗浄するＣｕ洗浄装置と、を備える、請求項９に記載の製造システム。 The manufacturing system of Claim 9 provided with the static elimination apparatus which performs static elimination after Cu removal and before Cu washing | cleaning and the Cu washing | cleaning apparatus which wash | cleans the slurry and residue which remain after Cu removal. Ｃｕ除去後に配線パターン溝以外に堆積されたＣｕの仕上研磨を行うＣｕ仕上装置を備える、請求項９に記載の製造システム。 The manufacturing system according to claim 9, further comprising a Cu finishing device that performs finish polishing of Cu deposited other than the wiring pattern grooves after Cu removal. 前記除電装置は、イオナイザー、軟Ｘ線照射装置、紫外線照射装置のいずれかである、請求項９に記載の製造システム。 The manufacturing system according to claim 9, wherein the static eliminator is one of an ionizer, a soft X-ray irradiator, and an ultraviolet irradiator. 前記イオナイザーは基板搬送経路の上方１００ｍｍ以内に配置される、請求項１２に記載の製造システム。 The manufacturing system according to claim 12, wherein the ionizer is disposed within 100 mm above the substrate transfer path. 前記イオナイザーは基板搬送経路の上方３０ｍｍ以内に配置される、請求項１２に記載の製造システム。 The manufacturing system according to claim 12, wherein the ionizer is disposed within 30 mm above the substrate transfer path. 前記バリアメタルはＴｉ、ＴｉＮ、ＴｉとＴｉＮの合金のいずれかである、請求項９に記載の製造システム。 The manufacturing system according to claim 9, wherein the barrier metal is any one of Ti, TiN, and an alloy of Ti and TiN.
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