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WO2009134009A2 - Substrat électrolytique contenant une couche de catalyseur métallique et une couche d'ensemencement métallique, et procédé de production d'une carte à circuit imprimé - Google Patents

Substrat électrolytique contenant une couche de catalyseur métallique et une couche d'ensemencement métallique, et procédé de production d'une carte à circuit imprimé Download PDF

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Publication number
WO2009134009A2
WO2009134009A2 PCT/KR2009/001460 KR2009001460W WO2009134009A2 WO 2009134009 A2 WO2009134009 A2 WO 2009134009A2 KR 2009001460 W KR2009001460 W KR 2009001460W WO 2009134009 A2 WO2009134009 A2 WO 2009134009A2
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WO
WIPO (PCT)
Prior art keywords
layer
seed layer
metal seed
metal catalyst
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2009/001460
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English (en)
Korean (ko)
Other versions
WO2009134009A3 (fr
Inventor
백영환
유대환
강동엽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
P&I Corp
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P&I Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by P&I Corp filed Critical P&I Corp
Publication of WO2009134009A2 publication Critical patent/WO2009134009A2/fr
Publication of WO2009134009A3 publication Critical patent/WO2009134009A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H05K3/387—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive for electroless plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating

Definitions

  • the present invention relates to a material of a printed circuit board and a method of manufacturing a printed circuit board, and more particularly, to an electroplating substrate including a metal catalyst layer and a metal seed layer, and a printed circuit board using the same. It relates to a manufacturing method.
  • a tenting method and a semiadditive method are used in the manufacturing process of a printed circuit board.
  • the tenting method is to form a circuit pattern by removing the copper foil layer of the remaining portion except the circuit wiring by wet etching among the copper foil layers laminated on the substrate.
  • the tenting method has a limitation in forming a fine circuit pattern due to the nature of wet etching. Therefore, the tenting method is mainly used to form circuit patterns having a relatively wide wiring width.
  • the semi-additive method that can form a relatively fine and detailed circuit pattern compared to the tenting method is mainly used to form a fine circuit pattern.
  • a process of forming a fine circuit pattern using a general semi-additive method will be briefly described as follows. First, a metal seed layer is formed on the surface of the substrate by an electroless plating process or a dry deposition process, and a dry film is applied on the metal seed layer. Thereafter, the dry film is exposed and developed to pattern the dry film so that the metal seed layer in the portion corresponding to the circuit wiring is exposed to the outside.
  • the adhesion between the metal seed layer formed by the electroless plating process or the dry deposition process and the substrate is varied depending on the material of the printed circuit board, but the bismaleimide triazine (BT) and the ajinomoto build-up film (ABF) It is difficult to form a metal seed layer on the surface of the same glass fiber reinforced epoxy-based rigid substrate with sufficient adhesion to the rigid substrate by electroless plating or dry deposition.
  • BT bismaleimide triazine
  • ABSF ajinomoto build-up film
  • Adhesion deterioration caused by the plating process is recovered over time, but depending on the material of the substrate and the type of surface treatment process to enhance the adhesion between the metal seed layer and the substrate, the recovery time of the adhesive force and the restored adhesive strength Since the value of is different, there is still a limitation in forming a fine circuit pattern on a substrate using a conventional semi-additive method.
  • the present invention provides a substrate for electroplating comprising a hard substrate having a surface treated to form a reactive functional group and a metal catalyst layer continuously or discontinuously formed between the metal seed layers.
  • the present invention removes a number of factors including hydrogen and moisture, which have a great influence on lowering the adhesion between the metal seed layer and the hard substrate, by removing the metal catalyst layer activated by the heating process and the heating process, thereby reducing the hardness after electrolytic plating.
  • a method of manufacturing a printed circuit board which can shorten the recovery time of adhesion between the substrate and the metal seed layer, and can alleviate and stabilize the stress of the electroplating film.
  • the electroplating substrate according to the present invention comprises a rigid substrate, a metal catalyst layer, and a metal seed layer.
  • the rigid substrate includes a surface treatment layer containing reactive functional groups formed by a surface treatment process.
  • the metal catalyst layer is formed continuously or discontinuously by a dry deposition process on the surface treatment layer of the rigid substrate.
  • the metal seed layer is formed by a dry deposition process on the entire surface of the rigid substrate on which the metal catalyst layer is formed.
  • the metal catalyst layer is activated by a heating process.
  • the activated metal catalyst layer may be formed by removing hydrogen generated in the electrolytic plating layer and moisture introduced into the electrolytic plating layer during the electroplating process of forming a circuit pattern on the metal seed layer in manufacturing the printed circuit board. The recovery time of adhesion between the hard substrate and the metal seed layer reduced by the hydrogen and moisture is shortened.
  • a method of manufacturing a printed circuit board according to the present invention includes forming a surface treatment layer including a reactive functional group on a surface of a rigid substrate by a surface treatment process; Forming a metal catalyst layer, continuously or discontinuously, on the surface treatment layer of the rigid substrate by a dry deposition process; Forming a metal seed layer on the entire surface of the rigid substrate on which the metal catalyst layer is formed by a dry deposition process; Applying a dry film on the metal seed layer; Exposing and developing the dry film to pattern the dry film so that the metal seed layer in the portion corresponding to the set circuit wiring is exposed to the outside; Performing an electrolytic plating process to form a plating layer on the externally exposed metal seed layer, thereby forming circuit wiring made of the plating layer; Removing the dry film pattern, and then performing a flash etching process to remove the metal seed layer except for the metal seed layer under the plating layer; And performing a heating process of heating the rigid substrate on which the plating layer is formed.
  • various factors including hydrogen and moisture, which are generated in the electrolytic plating film during the electroplating process and have a great influence on reducing the adhesion between the metal seed layer and the rigid substrate, are activated by the heating process and the heating process. It can be removed by the metal catalyst layer. As a result, the adhesion recovery time between the hard substrate and the metal seed layer, which are degraded after electrolytic plating, can be shortened, and the stress of the electroplating film can be alleviated and stabilized.
  • FIG. 1 is a cross-sectional view showing a manufacturing process of an electroplating substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of an electroplating substrate according to another embodiment of the present invention.
  • FIG 3 is a cross-sectional view illustrating a manufacturing process of a printed circuit board according to an exemplary embodiment of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a manufacturing process of a printed circuit board according to another exemplary embodiment of the present invention.
  • 5 is a cross-sectional view of an experimental printed circuit board.
  • FIG. 6 is a table illustrating a configuration of the printed circuit board illustrated in FIG. 5 and peel strengths according to respective process conditions.
  • FIG. 1 is a cross-sectional view showing a manufacturing process of an electroplating substrate 101 according to an embodiment of the present invention.
  • a surface treatment process is performed on the rigid substrate 110.
  • the surface treatment process may include at least one of an ion assist reaction method, an ion beam treatment method, and a plasma treatment method. That is, the surface treatment process may be performed by using any one of an ion assist reaction method, an ion beam treatment method, a plasma treatment method, or a mixture of two or more methods.
  • the plasma treatment method may include any one of an atmospheric pressure plasma treatment method, a DC plasma treatment method, and an RF plasma treatment method.
  • the ion particles used in the surface treatment process one of the inert gases containing argon, or one of the reactive gases containing nitrogen, hydrogen, helium, oxygen, ammonia, or the inert gases and the reactive It may comprise a mixture comprising at least two of the gases.
  • the reactive gas used in the surface treatment process may include one of active gases including oxygen, nitrogen, ammonia and hydrogen, or a mixed gas including at least two of the active gases.
  • the metal catalyst layer 130a is formed discontinuously on the surface treatment layer 120 of the rigid substrate 110 by a dry deposition process.
  • the metal catalyst layer 130a may be formed to a thickness of about 1 to 40 nm according to the shape of the surface of the rigid substrate 110.
  • the dry deposition process for forming the metal catalyst layer 130a may include any one of ion beam sputtering, DC sputtering, RF sputtering, and evaporation.
  • the metal catalyst layer 130a may include any one of nickel (Ni), chromium (Cr), nickel alloys, and chromium alloys.
  • the metal catalyst layer 130a may include an oxide or a nitride of a metal including any one of nickel (Ni), chromium (Cr), nickel alloy, and chromium alloy.
  • the metal seed layer 140 is formed by a dry deposition process on the entire surface of the hard substrate 110 on which the metal catalyst layer 130a is formed.
  • the dry deposition process for forming the metal seed layer 140 may include any one of ion beam sputtering, DC sputtering, RF sputtering, and evaporation.
  • the metal seed layer 140 includes copper (Cu).
  • the metal catalyst layer 130a Activated by a heating process.
  • the activated metal catalyst layer 130a is formed between the hard substrate 110 and the metal seed layer 140 reduced by an electroplating process of forming a circuit pattern on the metal seed layer 140 in manufacturing a printed circuit board. Shorten the time it takes for adhesion to recover. In addition, by the surface treatment process, the adhesion between the rigid substrate 110 and the metal seed layer 140 may be enhanced.
  • FIG. 2 is a cross-sectional view showing a manufacturing process of the electroplating substrate 102 according to another embodiment of the present invention.
  • the manufacturing process of the electroplating substrate 102 is similar to the manufacturing process of the electroplating substrate 101 described above except for one difference. Therefore, in order to avoid duplication of description, the present embodiment will be described based on the difference between the manufacturing process of the electroplating substrates (102, 101).
  • the difference between the manufacturing processes of the electroplating substrates 102 and 101 is that in the manufacturing process of the electroplating substrate 102, as shown in FIG. 2C, the surface treatment of the rigid substrate 110 is performed.
  • metal catalyst layer 130b is formed continuously by a dry deposition process.
  • the metal catalyst layer 130b may be formed to a thickness of 40 nm or less according to the shape of the surface of the rigid substrate 110. Since the metal catalyst layer 130b is continuously formed on the surface treatment layer 120 of the rigid substrate 110, the metal seed layer 140 when the printed circuit board is manufactured using the electroplating substrate 102. The recovery time of the adhesive force between the rigid substrate 110 and the metal seed layer 140 after performing the electroplating process and the heating process on the N may be further shortened.
  • FIG. 3 is a cross-sectional view illustrating a manufacturing process of a printed circuit board according to an exemplary embodiment of the present invention.
  • the metal seed layer 140 of the electroplating substrate 101 (the electroplating substrate manufactured by the process shown in FIGS. 1A to 1D).
  • the dry film 210 is apply
  • the manufacturing process of the electroplating substrate 101 is the same as described above, its detailed description is omitted.
  • the dry film 210 is exposed and developed, and as a result, as shown in FIG. 3C, the metal seed layer of the portion corresponding to the set circuit wiring ( The dry film 210 is patterned so that the 140 is exposed to the outside. Thereafter, as illustrated in FIG. 3D, an electrolytic plating process is performed to form a plating layer 220 on the metal seed layer 140 exposed to the outside. As a result, a circuit wiring formed of the plating layer 220 is formed on the metal seed layer 140 exposed to the outside.
  • the circuit wiring may be a fine circuit pattern, and each may be a fine circuit pattern having a line and a space of 15 ⁇ m or less.
  • the rigid substrate 110 may be a substrate including a glass fiber reinforced epoxy resin.
  • the glass fiber reinforced epoxy resin may include, for example, flame retardant-4 (FR-4), bismaleimide triazine (BT), ajinomoto build-up film (ABF), or the like.
  • FR-4 flame retardant-4
  • BT bismaleimide triazine
  • ABSF ajinomoto build-up film
  • the maximum heating temperature may be set to a glass transition temperature (Tg), and the heating time may be set to 10 minutes to 120 minutes.
  • the printed circuit board 201 manufactured by the above-described process includes a metal catalyst layer 130a between the hard substrate 110 and the metal seed layer 141, and thus may be degraded due to the electroplating process.
  • the adhesion between the 110 and the metal seed layer 141 can be quickly recovered by the metal catalyst layer 130a activated by the heating process.
  • hydrogen is generated in the plating layer 220, and moisture is introduced into the plating layer 220, thereby reducing adhesion between the hard substrate 110 and the metal seed layer 141. Factors may occur in the plating layer 220.
  • the heating process is performed after the electrolytic plating process, the adhesion between the rigid substrate 110 and the metal seed layer 141 is reduced by the heating process and the metal catalyst layer 130a activated by the heating process. Various factors including hydrogen, moisture, and the like can be eliminated, and stress relaxation and stabilization of the electroplating film can be achieved. Since the activated metal catalyst layer 130a and the heating process remove various factors including hydrogen and moisture, the hard substrate 110 and the metal seed reduced by various factors including hydrogen and moisture. The recovery time of the adhesion between the layers 141 can be shortened.
  • FIG. 4 is a cross-sectional view illustrating a manufacturing process of a printed circuit board according to another exemplary embodiment of the present invention.
  • the manufacturing process of the printed circuit board 202 is similar to the manufacturing process of the printed circuit board 201 described above with one difference. Therefore, in order to avoid duplication of description, the present embodiment will be described based on the difference between the manufacturing process of the printed circuit boards (202, 201).
  • the difference between the manufacturing processes of the printed circuit boards 202 and 201 is that, in the manufacturing process of the printed circuit board 202, as shown in FIG. 4A, the electroplating substrate 102 (FIG. 2). Electroplating substrate prepared by the process shown in (a) to (d) of)) is used.
  • the electroplating substrate 102 includes a metal catalyst layer 130b continuously formed on the surface treatment layer 120 of the rigid substrate 110. Therefore, the adhesive force between the hard substrate 110 and the metal seed layer 140, which may be degraded by the electrolytic plating process, may be restored more quickly by the metal catalyst layer 130b activated by the heating process.
  • the activated metal catalyst layer 130b and the heating process various factors including hydrogen generated in the plating layer 220 and moisture introduced into the plating layer 220 are removed during the electrolytic plating process. Therefore, the recovery time of the adhesive force between the hard substrate 110 and the metal seed layer 141 reduced by various factors including hydrogen and moisture may be shortened.
  • the heating process and the metal catalyst layer 130b activated by the heating process stress relaxation and stabilization of the electroplating film can be achieved.
  • FIG. 5A is a cross-sectional view of an experimental printed circuit board electrolytically plated on the entire surface of the electroplating substrate shown in FIG. 1D and then heat treated
  • FIG. Fig. 1 is a sectional view of a printed circuit board which does not include a metal catalyst layer as a printed circuit board for checking with the printed circuit board shown in (a).
  • FIG. 6 is a table showing a configuration of the printed circuit board illustrated in FIGS. 5A and 5B and peel strengths according to respective process conditions.
  • electrolytic plating is performed on the entire surface of the metal seed layer 140 to form a copper plating layer 150 having a thickness of 20 ⁇ m.
  • Printed circuit boards were prepared. Peel strength between the hard substrate 110 and the metal seed layer 140 of the 14 printed circuit boards on which the copper plating layer 150 was formed was measured. Finally, 14 printed circuits are removed to reduce stress and stabilize the plating layer 150 by removing various factors including hydrogen generated in the plating layer 150 and moisture introduced into the plating layer 150. The substrate was heated at a heating temperature of 80 ° C. for 60 minutes. After the heating process, the peel strength between the rigid substrate 110 and the metal seed layer 140 of the 14 printed circuit boards was measured, respectively.
  • a metal catalyst layer 130a of an alloy of nickel / chromium or an alloy of nickel / copper is respectively fired on a thickness of about 1 or 3 nm on six rigid substrates using DC sputtering or ion beam sputtering. Deposited continuously. Thereafter, the metal seed layer 140 containing copper was dry deposited to a thickness of 500 nm on the eight rigid substrates by the same sputtering method as the method for forming the metal catalyst layer 130a.
  • electrolytic plating is performed on the entire surface of the metal seed layer 140 to form a copper plating layer 150 having a thickness of 20 ⁇ m.
  • Printed circuit boards were prepared. Peel strength between the hard substrate 110 and the metal seed layer 140 of the eight printed circuit boards on which the copper plating layer 150 was formed were respectively measured. Finally, eight printed circuits are removed to reduce stress and stabilize the plating layer 150 by removing various factors including hydrogen generated in the plating layer 150 and moisture introduced into the plating layer 150. The substrate was heated at a heating temperature of 80 ° C. for 60 minutes. After the heating process, the peel strength between the rigid substrate 110 and the metal seed layer 140 of the eight printed circuit boards was measured, respectively.
  • One of the eight rigid substrates comprising a flame retardant-4 (FR-4) raw material is not surface treated, and the rest is subjected to Ion Assist Reaction (IAR), as referenced in the table of FIG. 6. Surface treatment respectively.
  • IAR Ion Assist Reaction
  • an alloy of nickel, nickel / chromium, and nickel / copper having a thickness of about 1 or 3 nm using DC sputtering or ion beam sputtering
  • the metal catalyst layers 130a of were respectively discontinuously deposited.
  • the metal seed layer 140 containing copper was dry deposited to a thickness of 500 nm on the eight hard substrates by the same sputtering method as the method for forming the metal catalyst layer 130a.
  • electrolytic plating is performed on the entire surface of the metal seed layer 140 to form a copper plating layer 150 having a thickness of 20 ⁇ m.
  • Printed circuit boards were prepared. Peel strength between the hard substrate 110 and the metal seed layer 140 of the eight printed circuit boards on which the copper plating layer 150 was formed were respectively measured. Finally, the eight printed circuits are removed to reduce stress and stabilize the plating layer 150 by removing various factors including hydrogen generated in the plating layer 150 and moisture introduced into the plating layer 150.
  • the substrate was heated at a heating temperature of 80 ° C. for 60 minutes. After the heating process, the peel strength between the rigid substrate 110 and the metal seed layer 140 of the eight printed circuit boards was measured, respectively.
  • Peel strength measured in each of Experiments 1 to 3 is as shown in the table of FIG. 6.
  • the printed circuit board including the metal catalyst layer 130a has a greater peeling strength and is not subjected to the surface treatment process. It can be seen that the peeling strength of the printed circuit board subjected to the surface treatment process is greater than that of the circuit board. In addition, it can be seen that the peeling strength of the printed circuit board after the heating process is further increased as compared with before the heating process.
  • the reduction in adhesion between the hardened substrate and the metal seed layer appearing after electroplating by a metal catalyst layer continuously or discontinuously formed between the surface-treated hard substrate and the metal seed layer and the heating process is alleviated and complemented. It is possible to quickly restore and stabilize the adhesive force.
  • a printed circuit board including a fine circuit pattern each having a line and a space of 15 ⁇ m or less Manufacturing becomes possible.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

L'invention porte sur un substrat électrolytique contenant une couche de catalyseur métallique et une couche d'ensemencement métallique, et sur un procédé de production d'une carte à circuit imprimé. Le substrat électrolytique précité comprend un substrat rigide, une couche de catalyseur métallique et une couche d'ensemencement métallique. Le substrat rigide comprend une couche de traitement de surface contenant un groupe fonctionnel réactif. La couche de catalyseur métallique est formée de manière continue ou discontinue sur la couche de traitement de surface du substrat rigide par un processus de dépôt à sec. La couche d'ensemencement métallique est formée par dépôt à sec sur la surface avant du substrat rigide sur laquelle la couche de catalyseur métallique a été formée. La couche de catalyseur métallique est activée par un processus d'échauffement, lequel processus d'échauffement permet en outre, avec la couche de catalyseur métallique activée, d'éliminer divers facteurs tels que l'hydrogène et l'humidité, qui se forment normalement sur un film électrolytique au cours du processus d'électrodéposition destiné à produire une carte à circuit imprimé et qui détériorent l'adhérence entre la couche d'ensemencement métallique et le substrat rigide. L'invention permet de réduire le temps requis pour restaurer l'adhérence entre la couche d'ensemencement métallique et le substrat rigide qui se détériore à la suite de l'électrodéposition, et permet de renforcer ladite adhérence.
PCT/KR2009/001460 2008-04-29 2009-03-23 Substrat électrolytique contenant une couche de catalyseur métallique et une couche d'ensemencement métallique, et procédé de production d'une carte à circuit imprimé Ceased WO2009134009A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020080039731A KR20090113995A (ko) 2008-04-29 2008-04-29 금속 촉매층 및 금속 시드층을 포함하는 전해도금용 기판,및 이를 이용한 인쇄회로기판의 제조 방법
KR10-2008-0039731 2008-04-29

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WO2009134009A2 true WO2009134009A2 (fr) 2009-11-05
WO2009134009A3 WO2009134009A3 (fr) 2009-12-23

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KR (1) KR20090113995A (fr)
TW (1) TW200945974A (fr)
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Cited By (1)

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US10396007B2 (en) 2016-03-03 2019-08-27 Infineon Technologies Ag Semiconductor package with plateable encapsulant and a method for manufacturing the same

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CN110771270B (zh) * 2017-05-19 2023-05-30 佐佐木贝慈 电子部件搭载用基板及其制造方法
CN116230686A (zh) 2021-12-02 2023-06-06 群创光电股份有限公司 电子装置的复合层电路结构的制造方法
KR102606192B1 (ko) * 2021-12-30 2023-11-29 주식회사 큐프럼 머티리얼즈 구리 접합 질화물 기판용 구리 접합층 니켈 합금 조성물
WO2023128687A1 (fr) * 2021-12-30 2023-07-06 주식회사 큐프럼 머티리얼즈 Composition d'alliage de nickel pour couche de liaison au cuivre pour substrat de nitrure lié au cuivre

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KR960016650B1 (ko) * 1994-05-16 1996-12-19 양승택 광대역 서비스의 데이타율 감시를 이용한 부가과금 처리방법
JP2001020077A (ja) * 1999-07-07 2001-01-23 Sony Corp 無電解めっき方法及び無電解めっき液
JP4559936B2 (ja) * 2004-10-21 2010-10-13 アルプス電気株式会社 無電解めっき方法およびこの方法を用いた回路形成方法
JP2008007800A (ja) * 2006-06-27 2008-01-17 Seiko Epson Corp めっき基板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10396007B2 (en) 2016-03-03 2019-08-27 Infineon Technologies Ag Semiconductor package with plateable encapsulant and a method for manufacturing the same
US11081417B2 (en) 2016-03-03 2021-08-03 Infineon Technologies Ag Manufacturing a package using plateable encapsulant

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KR20090113995A (ko) 2009-11-03
TW200945974A (en) 2009-11-01
WO2009134009A3 (fr) 2009-12-23

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