200945974 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種印刷電路板（Printed Circuit Board )的材料以及印刷 電路板的製造方法，更詳細地說，涉及包含金屬觸媒層和金屬晶種層的電 鍍用基板以及利用該基板的印刷電路板的製造方法（Board for the use of electroplating including metal catalyst layer and metal seed layer, and fabrication method of printed circuit board using the board ) 【先前技術】 o ❹ 最近，隨著半導體製造技術的發展，印刷電路板變得較輕且被小型 化。這樣，印刷電路板上的金屬佈線的寬度和半導體元件連接的通孔（via hole)的大小也變得越來越小，要求用於形成更細微的電路圖案的方法，這 就是當前實情。通常地，在印刷電路板的製造過程中使用掩蔽（tenting)方 式和半加（semiadditive)方式。掩蔽方式通過濕式蝕刻去除層疊在基板上 的銅箔層中除了電路佈線以外的部分的鋼箔層，從而形成電路圖案。但是， 由於濕式蝕刻的特性’通過掩蔽方式形成細微電路圖案是受限制的。因此 掩蔽方式主要用於形成具有較寬的佈線寬度的電路圖案。 另一方面，與掩蔽方式相比能夠形成比較精細的電路圖案的半加方式 主要用於开>成細微的電路圖案。利用一般的半加方式形成細微電路圖案的 過程如下：首先，通過無電鍍工序或者乾式蒸鍍工序，在基板表面上形成 金屬明種層，在該金屬晶種層上塗敷幹膜（办gim)。之後，對幹膜進行 曝光以及麟’並在幹膜上形細案，使得與電路佈線對應的部分的金屬 晶種層被暴露在外部。 其後’在將幹臈形成了 ®⑽基板上執行電鍵王序，從而在暴露於外 部的金屬晶種層上形賴金層。其絲，形成由鍍金層構成的電路佈線。 去除幹臈減侧絲刻（flash etehing)，制去除除了電路佈線下方的 金屬晶種層以外的部分的金屬晶種層，基板上路佈線。 在此，通過無電鑛工序或者乾式蒸錢工序形成的金屬晶種層和基板之 ==艮形1印刷電路板的材料而不同，但是通過無電鍍或者乾式 BT (bismalemude tnazine) > ABF (ajinomoto build-up film) ^ 200945974 :=====基板表面上顧具有細性基板的紐的枯結力 因此，究了祕加強金屬晶種層和基板之_·力的各種表面處 ^法it是用於加強金屬晶種層和基板之間_結力的現有的表面處理 方法至今未能實現金屬晶種層和基板之_充分曝結力。另—方面，由 於在金屬晶種層的形#序之後執行的電虹序，發生金屬晶種層和基板 之間祕結力進-步下降的現象’這樣金屬晶種層和基板之間_結力進 =減小’因此難以形成基板材料。錄金卫和丨起賴結力下降現象隨 者時間的㈣而恢復’但是根據形成基板的材料和用於加強金屬晶種層和 ❹ _之間_結力的表面處理工序的麵，赌力的恢復賴和恢復的枯 結力大小也不同，至今為止，制現有的半加方式在基板上形成細微 的電路圖案是有限的。 【發明内容】 本發明提供-種包含硬性基板、金屬觸媒層以及金屬晶種層（seed) 層的電鑛用基板。硬性基板包含通過表面處理工序而形成的表面處理層， 該表面處理層包含反應性功能基。通過乾式蒸鍍工序，金屬觸媒層連續或 不連續地形成在硬性基板的表面處理層上。通過乾式蒸鍍工序，金屬晶種 層形成在硬性基板的整個面上，該硬性基板上形成有金屬觸媒層。金屬觸 〇 媒層通過加熱工序而被活性化。被活性化的金屬觸媒層在製造印刷電路板 時去除在電鍍層内產生的氫氣和流入到上述電鍍層内的水分，從而縮短由 於上述氫氣以及水分而減小的上述硬性基板和上述金屬晶種層之間的粘結 力的恢復_ ’其中’所錢氣是在上述金屬晶種層上職電路圖案的電 鍍工序中產生的，所述水分是在上述金屬晶種層上形成電路圖案的電鍍工 序中流入的。 本發明供一種印刷電路板的製造方法。本發明的印刷電路板的製造 方法包括：通過表面處理工序，在硬性基板的表面上形成包含反應性功能 基的表面處理層的步驟；在上述硬性基板的上述表面處理層上，通過乾式 蒸鍍工序，連續或者不連續地形成金屬觸媒層的步驟；在形成有上述金屬 觸媒層的上述硬性基板的整個面上，通過乾式蒸鍍工序形成金屬晶種層的 200945974 步驟；在上述金屬晶種層上錄幹賴步驟；對上雜親行曝光以及顯 影’並在上赫膜上形細案，以使無定的電路佈線對應的部分的金屬 晶種廣暴露在外部的步驟；執行電鍍工序，以在暴露於外部的金屬晶種層 上形成鍍金層，從而形成由鍍金層構成的電路佈線的步驟；在去除上述幹 膜圖案後，執行閃光侧，從而去除除了上述鑛金層下方的金屬晶種層以 外的部分的金屬晶種層的步驟；以及執行加熱工序的步驟，其中，所述加 熱工序用於對形成有上述鍍金層的硬性基板進行加熱。 根據本發m過加熱工序和金刺騎，_去除包括在電鑛工序 令在電鑛膜内產生的氫氣以及水分等的各種因素，其中，所述包括氯氣和 水分等的各種因素對金屬晶種層和硬性基板之間的粘結力下降帶來很大的 © 影響’所述金屬觸媒層通過加熱工序已被活性化。其結果，能夠縮短電鍵 後下降的硬性基板和金屬晶種層之_滅力的恢復時間，電鍍膜的應力 得以緩和，能夠實現穩定化。 ’ 【實施方式】 下面，參照附圖對本發明的優選實施例進行說明。但是，本發明並不 限定於以下公開的實施例，能夠以不同的各種形態體現，本實施例僅僅是 為了使本發明的公開更完整、向普通技術人員告知發明的範圍而提供的。 圖1是表示本發明的一個實施例的電鍍用基板（101)的製造過程的 Q 剖視圖。如圖1 (a)所示，對硬性基板（110)進行表面處理工序。表面處 理工序可使用離子辅助反應法、離子束處理法、等離子處理法中的至少一 種方法。即，可以混用離子輔助反應法、離子束處理法、等離子處理法中 的一種或者兩種以上的方法來執行上述表面處理工序。等離子處理法可包 含常壓等離子處理法、DC等離子處理法、RF等離子處理法中的一種方法。 另外，在上述表面處理工序中使用的離子粒子可包含：包含氬氣的惰性氣 體中的一種氣體，或者，包含氮氣、氣氣、氛氣、氧氣、氨氣的反應性氣 體中的一種氣體，或者，包含上述惰性氣體以及上述反應性氣髏中的至少 兩種氣體的混合物。在上述表面處理工序中使用的反應性氣體可包含：包 含氧氣、氮氣、氨氣、氫氣的活性氣體中的一個，或者，包含上述活性氣 體中的至少兩種氣體的混合氣體。上述表面處理工序的結果，如圖1 (b) 200945974 所示’在硬性基板（110)的表面上形成包含反應性功能基（如jctional识〇叩） (未圖示）的表面處理層（120)。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board material and a method of manufacturing a printed circuit board, and more particularly to a metal catalyst layer and a metal seed crystal. "Board for the use of electroplating including metal catalyst layer and metal seed layer, and fabrication method of printed circuit board using the board" [Prior Art] o ❹ With the development of semiconductor manufacturing technology, printed circuit boards have become lighter and miniaturized. Thus, the width of the metal wiring on the printed circuit board and the size of the via hole to which the semiconductor element is connected become smaller and smaller, and a method for forming a finer circuit pattern is required, which is the current situation. Generally, a tenting method and a semiadditive method are used in the manufacture of a printed circuit board. The masking method removes the steel foil layer of a portion other than the circuit wiring in the copper foil layer laminated on the substrate by wet etching, thereby forming a circuit pattern. However, the formation of fine circuit patterns by masking due to the characteristics of wet etching is limited. Therefore, the masking method is mainly used to form a circuit pattern having a wider wiring width. On the other hand, a half-addition method capable of forming a relatively fine circuit pattern as compared with the masking method is mainly used for opening > into a fine circuit pattern. The process of forming a fine circuit pattern by a general half-addition method is as follows: First, a metal seed layer is formed on a surface of a substrate by an electroless plating process or a dry evaporation process, and a dry film is applied on the metal seed layer (gim) . Thereafter, the dry film is exposed and the film is formed on the dry film so that the metal seed layer of the portion corresponding to the circuit wiring is exposed to the outside. Thereafter, a key sequence is performed on the substrate on which the xenon is formed into a (10) substrate, thereby depositing a gold layer on the metal seed layer exposed to the outside. The wire forms a circuit wiring composed of a gold plating layer. The flash etehing is removed to remove a portion of the metal seed layer other than the metal seed layer under the circuit wiring, and the substrate is routed. Here, the metal seed layer formed by the electroless ore-free process or the dry steaming process differs from the material of the ==1 printed circuit board, but by electroless plating or dry BT (bismalemude tnazine) > ABF (ajinomoto) Build-up film) ^ 200945974 :===== The dry end of the substrate with a fine substrate on the surface of the substrate. Therefore, it is necessary to strengthen the various layers of the metal seed layer and the substrate. The existing surface treatment method for strengthening the _junction between the metal seed layer and the substrate has not yet achieved sufficient entanglement of the metal seed layer and the substrate. On the other hand, due to the electro-red sequence performed after the shape of the metal seed layer, a phenomenon in which the secret force between the metal seed layer and the substrate progresses stepwise is decreased, such that the metal seed layer and the substrate are between each other. The junction force is reduced = so it is difficult to form the substrate material. Recording Jin Wei and 丨 赖 结 结 下降 下降 下降 下降 下降 下降 下降 下降 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是 但是The recovery and recovery of the recovery force are also different. So far, the conventional semi-additive method has a limited formation of a fine circuit pattern on the substrate. SUMMARY OF THE INVENTION The present invention provides a substrate for electric ore comprising a hard substrate, a metal catalyst layer, and a metal seed layer. The rigid substrate includes a surface treatment layer formed by a surface treatment process, and the surface treatment layer contains a reactive functional group. The metal catalyst layer is continuously or discontinuously formed on the surface treatment layer of the rigid substrate by a dry evaporation process. In the dry vapor deposition step, a metal seed layer is formed on the entire surface of the rigid substrate, and a metal catalyst layer is formed on the rigid substrate. The metal contact dielectric layer is activated by a heating process. The activated metal catalyst layer removes hydrogen generated in the plating layer and moisture flowing into the plating layer when manufacturing the printed circuit board, thereby shortening the hard substrate and the metal crystal reduced by the hydrogen gas and moisture described above. Recovering the adhesion between the layers _ 'where' is generated in the electroplating process of the above-mentioned metal seed layer upper circuit pattern, which forms a circuit pattern on the above metal seed layer Inflow during the plating process. The present invention is directed to a method of fabricating a printed circuit board. A method of manufacturing a printed circuit board according to the present invention includes: a step of forming a surface treatment layer containing a reactive functional group on a surface of a rigid substrate by a surface treatment step; and performing dry evaporation on the surface treatment layer of the hard substrate a step of forming a metal catalyst layer continuously or discontinuously; a step of forming a metal seed layer by a dry evaporation process on the entire surface of the hard substrate on which the metal catalyst layer is formed; a step of recording the dry layer on the seed layer; exposing and developing the upper dummy film and forming a fine pattern on the upper film to expose the metal crystal seed of the portion corresponding to the amorphous circuit wiring to the outside; performing electroplating a step of forming a gold plating layer on the metal seed layer exposed to the outside to form a circuit wiring composed of a gold plating layer; after removing the dry film pattern, performing a flash side, thereby removing the underside of the gold layer a step of a metal seed layer of a portion other than the metal seed layer; and a step of performing a heating process, wherein the heating worker A rigid substrate on which the above-described gold plating layer is formed is heated. According to the present invention, the heating process and the golden thorn riding are used to remove various factors including hydrogen gas and moisture generated in the electric ore film in the electric ore process, wherein the various factors including chlorine gas and moisture are applied to the metal seed crystal. The decrease in the adhesion between the layer and the rigid substrate causes a large influence. The metal catalyst layer has been activated by the heating process. As a result, the recovery time of the hard substrate and the metal seed layer which are lowered after the key change can be shortened, the stress of the plating film can be relaxed, and stabilization can be achieved. [Embodiment] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are merely provided to make the disclosure of the present invention more complete and to disclose the scope of the invention to those skilled in the art. Fig. 1 is a cross-sectional view showing the manufacturing process of a substrate (101) for electroplating according to an embodiment of the present invention. As shown in FIG. 1(a), the hard substrate (110) is subjected to a surface treatment process. At least one of the ion assisted reaction method, the ion beam treatment method, and the plasma treatment method can be used for the surface treatment step. That is, the surface treatment step can be carried out by mixing one or two or more of the ion assisted reaction method, the ion beam treatment method, and the plasma treatment method. The plasma treatment method may include one of a normal pressure plasma treatment method, a DC plasma treatment method, and an RF plasma treatment method. Further, the ionic particles used in the surface treatment step may include one of an inert gas containing argon gas or a gas containing a reactive gas of nitrogen, gas, atmosphere, oxygen, or ammonia. Or a mixture comprising the above inert gas and at least two of the above reactive gas. The reactive gas used in the surface treatment step may include one of active gases containing oxygen, nitrogen, ammonia, and hydrogen, or a mixed gas containing at least two of the above-described active gases. As a result of the surface treatment step, as shown in Fig. 1 (b) 200945974, a surface treatment layer (120) containing a reactive functional group (e.g., jctional) (not shown) is formed on the surface of the rigid substrate (110). ).
其後，如圖1 (c)所示，通過乾式蒸鍍工序，在硬性基板（11〇)的 表面處理層（120)上不連續地形成金屬觸媒層（13〇a)。此時，金屬觸媒 層（130a)根據硬性基板（ι10)的表面形狀可形成約丨〜仙麵的厚度。用 於形成上述金屬觸媒層（13〇a)的乾式蒸鍍工序可使用離子束塗敷（i〇nbeam sputtering)法、DC塗敷法、Rp塗敷法、蒸發法（evap〇rati〇n)中的一種方 法。金屬觸媒層（130a)可包含鎳（Ni)、鉻（Cr)、鎳合金、鉻合金中 的一種。另外，金屬觸媒層（13〇a)可包含一種金屬的氧化物或者氮化物， 該金屬包含鎳（Ni)、鉻（〇)、鎳合金、鉻合金中的一種。如圖 所示，通過乾式蒸鍍工序，在形成有金屬觸媒層〇3〇a)的硬性基板（11〇) 的整個面上形成金屬晶種層（14〇)。用於形成上述金屬晶種層（14〇)的 乾式蒸鍍工序可使用離子束塗敷法、DC塗敷法、即塗敷法、蒸發法 (evaporation)中的一種方法。 —當卿通過上述過麵製造的電顧基板⑽）製造_電路板時， 右在金屬日日種層（I4。}上執行電鍍卫序以及加熱工序，則金屬觸媒層⑴⑻ 通過加熱工序碰活性化。被活性化的金朗縣⑽在製造印刷電 路板時能夠驗恢復餘力所需要的咖，其巾，所·結料由於在金 屬晶種層⑽）上形成電路圖案的_工序而減少的硬性基板⑽）和 金屬晶種層（14G)之間魄結力。另外，通過上述表面處理卫序，可增強 硬性基板（11G)和金屬晶種層（14())之間的枯結力。 、圖2是表示本發明的另一實施例的電鍍用基板（102)的製造過程的 剖視圖。除了-個不同點以夕卜，電鑛用基板（1〇2)的製造過程與上述電鑛 1板的製造過軸似。@此’為了避免重複說明 以電鑛用基板（1G2、1G1) 州 «, c1〇2 -1〇1) 電翻基板（1〇2)的觀抛中，親乾式驗工序，树 "(130b) 二在硬性=⑴^一下的厚度。 表面處理層（12G)上連續地形成金屬觸媒層 200945974 b)因此虽利用電鑛用基板（102)製造印刷電路板時，可進一步縮 Μ在金屬晶種層⑽）上執行麵功以及加熱工序後的硬絲板⑽） 和金屬晶種層（140)之間的枯結力的恢復時間。 圖3疋表不本發明的一個實施例的印刷電路板的製造過程的刮視圖。 如圖3 (a)所示，在電鍍用基板⑽）（通過圖1⑷至圖ι⑷所示 的過程製造的電鑛用基板）的金屬晶種層（14〇)上塗敷幹膜⑵。在 此’電鍵用基板（101)的製造過程與上述同樣，因此省略其詳細說明。 如圖3 (b)所示，對幹膜（21〇)進行曝光以及顯影，其結果，如圖 3 (c)所示，在幹膜（21〇)上形成圖案（patteming)，以使與設定的電路 佈，對應的部分的金屬晶種層（140)暴露在外部。其後，如圖3⑷所示， Ο 執行電鍍工序，在暴露於外部的金屬晶種層（14〇)上形成鑛金層（22〇)。 其結果，在暴露於外部的金屬晶種層（14〇)上形成由鑛金層（22〇)構成 的電路佈線。在此’電路佈線為細微電路圖案，可以為線〇ine)、以及間 隙（space)分別為i5Hm以下的細微的電路圖案。 如圖3 (e)所示’在去除幹膜（211)後執行閃光蝕刻（flashetching) 工序。其結果，如圖3 (f)所示，除了鍍金層（220)的下方的金屬晶種層 (140)以外的部分的金屬晶種層（140)被去除。此時，鍍金層（220)的 上方表面也稿微被姓刻。 其後’如圖3 ( g)所示，執行對形成有鍍金層（220)的硬性基板（丨10) Q 進行加熱的加熱工序。硬性基板（110)可以是包含玻璃纖維強化環氧類樹 脂的基板。例如，玻璃纖維強化環氧類樹脂可包含FR_4(flame retardant_4)， BT(bismaleimide trizine) ’ ABF(ajinomoto build-up film)等。在上述加熱工序 中最南加熱溫度可设定為玻璃轉移溫度（Tg; glass transition temperature)， 加熱時間的範圍可設定為l〇〜120分鐘。 由於通過上述過程而製造的印刷電路板（201)在硬性基板（110)和 金屬晶種層（141)之間包含金屬觸媒層（130a)，因此由於上述電鑛工序 而有可能下降的硬性基板（110)和金屬晶種層（141)之間的粘結力通過 被活性化的金屬觸媒層（130a)可迅速恢復’其中，上述金屬觸媒層（130a) 是通過加熱工序而被活性化的。在執行上述電鑛工序的期間，在鍵金層 (220)内有可能發生包括在鑛金層（220)内產生的氫氣、在鍍金層（220) 200945974 、 内流入的水分等的各種因素，其中，該各種因素降低硬性基板（110)和金 屬晶種層（141)之間的粘結力。但是，由於在上述電鍍工序後執行加熱工 序，因此通過加熱工序以及金屬觸媒層（13〇a)能夠去除包括氫氣和水分 等的各種因素’可實現電鍍膜的應力（stress)的緩和以及穩定化，其中， 所述金屬觸媒層（130a)通過加熱工序已被活性化，包括氫氣和水分等的 各種因素降低硬性基板（110)和金屬晶種層（141)之間的粘結力。由於 通過被活性化的金屬觸媒層（130a)和上述加熱工序而去除包括氫氣和水 分等的各種因素，因此可縮短由於包括氫氣和水分等的各種因素而減小的 硬性基板（110)和金屬晶種層（141)之間的粘結力的恢復時間。 圖4是表示本發明的另一實施例的印刷電路板的製造過程的剖視圖。 © 除了一個不同點以外’印刷電路板（202)的製造過程和上述的印刷電路板 (201)的製造過程類似。因此，為了避免重複說明，在本實施例中以印刷 電路板（202、201)的製造過程之間的不同點為主進行說明。印刷電路板 (202、201)的製造過程之間的不同點為，如圖4 (a)所示，在印刷電路 板（202)的製造過程中，使用電鍍用基板（1〇2)(通過圖2 (a)至圖2 (d)所示的過程而製造的電鍍用基板）。電鍍用基板（1〇2)在硬性基板 (110)的表面處理層（12〇)上包含連續形成的金屬觸媒層（13〇b)。因 此，由於電鍍工序而有可能下降的硬性基板（110)和金屬晶種層（14〇) 之間的粘結力通過被活性化的金屬觸媒層（i3〇b)可迅速恢復，其中，所 q 述金屬觸媒層（13〇b)是通過加熱工序而被活性化的。 即’通過被活性化的金屬觸媒層（13〇b)和上述加熱工序，去除包括 在上述電鍍工序中在鍍金層（220)内產生的氫氣、流入到鍍金層（220) 内的水分等的各種因素，因此能夠縮短由於包括氫氣以及水分等的各種因 素而減小的硬性基板（110)和金屬晶種層（141)之間的粘結力的恢復時 間。另外，通過加熱工序以及金屬觸媒層（13〇b)，可實現電鍍膜的應力 (stress)的緩和以及穩定化，其中，所述金屬觸媒層（13〇b)通過加熱工 序已被活性化。 下面，參照圖5對硬性基板和金屬觸媒層的材料以及各工序條件下的 試驗用印刷電路板的剝離強度進行說明。圖5 (a)是在圖j (d)所示的電 鍍用基板的整個表面上電鍍後進行加熱處理的試驗用印刷電路板的剖視 200945974 圖’圖5 (b)是與圖5 (a)所示的印刷電路板對照用的印刷電路板，是不 包括金屬觸媒層的印刷電路板的剖視圖。表！是表示圖5 以及圖5 所示的印刷電路板的結構以及各工序條件下的剝離程度。 (實驗1) 如表1所示，通過離子束輔助反應法（IAR; I〇n勉細尺從此⑽），對 包含BT(bismaleimide triazine)原材料的9個硬性基板分別進行表面處理，或 者，不進行表面處理而利用DC塗敷法或者離子束塗敷法，在12個硬性基 板上以約1〜40nm的厚度分別連續以及不連續地蒸鍍鎳、鎳/路的合金、鎳/ 鋼（Cu)的合金的金屬觸媒層（130a)。其後，通過與金屬觸媒層（13〇a) 的形成方法相同的塗敷法’在14個硬性基板上，以500nm的厚度將包含銅 €) 的金屬晶種層（140)進行乾式蒸鑛。之後，如圖5 (a)或圖5 (b)所示， 對於金屬晶種層（140)的整個面執行電鍵，以2〇μηι的厚度形成鋼錢金層 (150) ’從而製造了 14個印刷電路板。分別測量了形成有鋼鍍金層（15〇) 的14個印刷電路板的硬性基板（11〇)和金屬晶種層〇4〇)之間的剝離強 度。最後，去除包括在鍍金層（150)内產生的氫氣、流入到鍍金層（15〇) 内的水分等的各種因素’為了鐘金層（150)的應力緩和以及穩定化，在8〇。匸 的加熱溫度下，對於14個印刷電路板進行了 60分鐘的加熱。在加熱工序 後’分別測量了 14個印刷電路板的硬性基板（110)和金屬晶種層（14〇) 之間的剝離強度。 Q (實驗2) 如表1所示，通過常壓等離子處理法(APP; Atmospheric PressureThereafter, as shown in Fig. 1(c), the metal catalyst layer (13〇a) is discontinuously formed on the surface treatment layer (120) of the rigid substrate (11) by a dry vapor deposition step. At this time, the metal catalyst layer (130a) can form a thickness of about 丨 to 仙面 according to the surface shape of the rigid substrate (1010). The dry vapor deposition step for forming the metal catalyst layer (13〇a) may be performed by ion beam coating, DC coating, Rp coating, or evaporation (evap〇rati〇n). One of the methods. The metal catalyst layer (130a) may comprise one of nickel (Ni), chromium (Cr), a nickel alloy, and a chromium alloy. Further, the metal catalyst layer (13〇a) may comprise an oxide or nitride of a metal containing one of nickel (Ni), chromium (iridium), a nickel alloy, and a chromium alloy. As shown in the figure, a metal seed layer (14 Å) is formed on the entire surface of the rigid substrate (11 〇) on which the metal catalyst layer 〇3 〇 a) is formed by a dry vapor deposition step. The dry vapor deposition step for forming the above metal seed layer (14 Å) may be one of an ion beam coating method, a DC coating method, that is, a coating method, and an evaporation method. - When the _ circuit board is manufactured by the above-mentioned over-the-counter manufacturing substrate (10), the plating process and the heating process are performed on the metal day layer (I4.), and the metal catalyst layer (1) (8) is touched by the heating process. Activated. Jinlang County (10), which is activated, is able to verify the rest of the coffee when manufacturing a printed circuit board, and the towel and the material are reduced by the process of forming a circuit pattern on the metal seed layer (10). The crucible force between the hard substrate (10) and the metal seed layer (14G). Further, the dry force between the rigid substrate (11G) and the metal seed layer (14()) can be enhanced by the above surface treatment. Fig. 2 is a cross-sectional view showing a manufacturing process of a plating substrate (102) according to another embodiment of the present invention. Except for a different point, the manufacturing process of the electric ore substrate (1〇2) is similar to the manufacturing of the above-mentioned electric ore plate. @这' In order to avoid repeating the description of the electro-minening substrate (1G2, 1G1), the state «, c1〇2 -1〇1) is turned on the substrate (1〇2), the pro-dry process, the tree " 130b) The thickness of the second is hard = (1) ^. The metal catalyst layer 200945974 is continuously formed on the surface treatment layer (12G). b) Therefore, when the printed circuit board is manufactured by using the electric ore substrate (102), surface work and heating can be further performed on the metal seed layer (10). Recovery time of the dead force between the hard wire plate (10) after the process and the metal seed layer (140). Figure 3 is a plan view showing a manufacturing process of a printed circuit board which is not an embodiment of the present invention. As shown in Fig. 3 (a), a dry film (2) is applied to the metal seed layer (14 Å) of the plating substrate (10) (the substrate for electric ore produced by the processes shown in Figs. 1 (4) to (4)). The manufacturing process of the 'battery substrate (101) is the same as that described above, and thus detailed description thereof will be omitted. As shown in Fig. 3 (b), the dry film (21 Å) was exposed and developed, and as a result, as shown in Fig. 3 (c), a pattern (patteming) was formed on the dry film (21 Å) so that The set circuit cloth has a corresponding portion of the metal seed layer (140) exposed to the outside. Thereafter, as shown in Fig. 3 (4), 电镀 a plating process is performed to form a gold layer (22 Å) on the metal seed layer (14 Å) exposed to the outside. As a result, a circuit wiring composed of a gold ore layer (22 Å) is formed on the metal seed layer (14 Å) exposed to the outside. Here, the circuit wiring is a fine circuit pattern, which may be a line circuit, and a space is a subtle circuit pattern of i5Hm or less. As shown in Fig. 3 (e), a flash etching process is performed after the dry film (211) is removed. As a result, as shown in Fig. 3 (f), the metal seed layer (140) of the portion other than the metal seed layer (140) below the gold plating layer (220) is removed. At this time, the upper surface of the gold plating layer (220) is also slightly engraved. Thereafter, as shown in Fig. 3 (g), a heating step of heating the hard substrate (?10) Q on which the gold plating layer (220) is formed is performed. The rigid substrate (110) may be a substrate comprising a glass fiber reinforced epoxy resin. For example, the glass fiber reinforced epoxy resin may include FR_4 (flame retardant_4), BT (bismaleimide trizine)' ABF (ajinomoto build-up film), or the like. In the above heating step, the southernmost heating temperature can be set to a glass transition temperature (Tg; glass transition temperature), and the heating time can be set to a range of from 1 Torr to 120 minutes. Since the printed circuit board (201) manufactured by the above process includes the metal catalyst layer (130a) between the rigid substrate (110) and the metal seed layer (141), it is likely to be lowered due to the above-described electric ore process. The adhesion between the substrate (110) and the metal seed layer (141) can be quickly recovered by the activated metal catalyst layer (130a), wherein the metal catalyst layer (130a) is Activated. During the execution of the above-described electric ore process, various factors including hydrogen gas generated in the gold layer (220), moisture in the gold plating layer (220) 200945974, and the like may occur in the gold layer (220). Among them, the various factors reduce the adhesion between the rigid substrate (110) and the metal seed layer (141). However, since the heating step is performed after the plating step, the heating process and the metal catalyst layer (13〇a) can remove various factors including hydrogen gas and moisture, and the stress of the plating film can be alleviated and stabilized. The metal catalyst layer (130a) has been activated by a heating process, and various factors including hydrogen gas and moisture reduce the adhesion between the hard substrate (110) and the metal seed layer (141). Since various factors including hydrogen gas, moisture, and the like are removed by the activated metal catalyst layer (130a) and the above-described heating process, the rigid substrate (110) which is reduced by various factors including hydrogen gas and moisture, and the like can be shortened. The recovery time of the adhesion between the metal seed layers (141). 4 is a cross-sectional view showing a manufacturing process of a printed circuit board according to another embodiment of the present invention. © The manufacturing process of the printed circuit board (202) except for a different point is similar to the manufacturing process of the above printed circuit board (201). Therefore, in order to avoid redundancy, the differences between the manufacturing processes of the printed circuit boards (202, 201) will be mainly described in the present embodiment. The difference between the manufacturing processes of the printed circuit boards (202, 201) is that, as shown in FIG. 4(a), in the manufacturing process of the printed circuit board (202), the substrate for plating (1〇2) is used (through The substrate for electroplating manufactured by the processes shown in Figs. 2(a) to 2(d)). The substrate for plating (1〇2) contains a continuously formed metal catalyst layer (13〇b) on the surface treatment layer (12〇) of the rigid substrate (110). Therefore, the adhesion between the hard substrate (110) and the metal seed layer (14〇) which may be lowered due to the electroplating process can be quickly recovered by the activated metal catalyst layer (i3〇b), wherein The metal catalyst layer (13〇b) is activated by a heating process. In other words, the hydrogen gas generated in the gold plating layer (220) and the water flowing into the gold plating layer (220) in the plating step are removed by the activated metal catalyst layer (13〇b) and the heating step described above. Various factors, therefore, can shorten the recovery time of the adhesion between the rigid substrate (110) and the metal seed layer (141) which is reduced due to various factors including hydrogen gas and moisture. Further, the stress and stress of the plating film can be alleviated and stabilized by the heating step and the metal catalyst layer (13〇b) which has been activated by the heating process. Chemical. Next, the material of the rigid substrate and the metal catalyst layer and the peel strength of the test printed circuit board under the respective process conditions will be described with reference to Fig. 5 . Fig. 5 (a) is a cross-sectional view of a test printed circuit board which is subjected to heat treatment after plating on the entire surface of the plating substrate shown in Fig. j (d), 200945974. Fig. 5 (b) is the same as Fig. 5 (a) The illustrated printed circuit board for printed circuit board comparison is a cross-sectional view of a printed circuit board that does not include a metallic catalyst layer. table! The structure of the printed circuit board shown in FIG. 5 and FIG. 5 and the degree of peeling under each process condition are shown. (Experiment 1) As shown in Table 1, nine hard substrates containing BT (bismaleimide triazine) raw materials were subjected to surface treatment by ion beam assisted reaction method (IAR; I〇n勉 fine ruler (10)), or Surface treatment is carried out by DC coating or ion beam coating, and nickel, nickel/road alloy, nickel/steel (Cu) are continuously and discontinuously deposited on 12 rigid substrates at a thickness of about 1 to 40 nm. a metal catalyst layer (130a) of the alloy. Thereafter, the metal seed layer (140) containing copper at a thickness of 500 nm was dry-steamed on the 14 rigid substrates by the same coating method as the method of forming the metal catalyst layer (13〇a). mine. Thereafter, as shown in FIG. 5(a) or FIG. 5(b), a key is performed on the entire surface of the metal seed layer (140), and a steel money layer (150) is formed in a thickness of 2 〇μηι to manufacture 14 Printed circuit boards. The peel strength between the hard substrate (11 Å) and the metal seed layer 14 4 〇 of 14 printed circuit boards on which the steel gold plating layer (15 Å) was formed was measured, respectively. Finally, various factors including the hydrogen gas generated in the gold plating layer (150), the moisture flowing into the gold plating layer (15 Å), and the like are removed, and the stress relaxation and stabilization of the gilt layer (150) are at 8 Torr. The 14 printed circuit boards were heated for 60 minutes at 加热 heating temperature. The peel strength between the rigid substrate (110) and the metal seed layer (14 Å) of 14 printed circuit boards was measured after the heating process. Q (Experiment 2) As shown in Table 1, by atmospheric pressure plasma treatment (APP; Atmospheric Pressure
Plasma)，對包含 ABF(ajinomoto build-up film)和 BT(bismaleimide triazine)原 材料的8個硬性基板進行表面處理，或者，不進行表面處理而利用Dc塗 敷法或者離子束塗敷法’在6個硬性基板上，以約lnm或3nm的厚度不連 續地分別蒸鍍了鎳/絡的合金、或者鎳/銅的合金的金屬觸媒層（13〇a)。 其後，通過與金屬觸媒層（13〇a)的形成方法相同的塗敷法，在8個硬性 基板上’以500nm的厚度將包含銅的金屬晶種層（140)進行乾式蒸鍍。之 後’如圖5 (a)或圖5 (b)所示’對於金屬晶種層（14〇)的整個面執行 電鍍’以20μπι的厚度形成銅鍍金層（150)，從而製造了 8個印刷電路板。 分別測量了形成有銅鍍金層（150)的8個印刷電路板的硬性基板（11〇) 200945974 、和金屬晶種層（140)之間的剝離強度。最後，去除包括在鍍金層（15〇) 内產生的統、流人到鍍金層（15G)内的水分等的各翻素，為了錢金廣 (150)的應力緩和以及穩定化，在8(rc的加熱溫度下，對於8個印刷電路 板進行了 60分鐘的加熱。在加熱工序後，分別測量了 8個印刷電路板的硬 性基板（110)和金屬晶種層（140)之間的剝離強度。 (實驗3) _對於包含FR-4 (flameretard邮-4)原材料的8個硬性基板中的一個進 行表面處理，對於其他硬性基板，如表丨所示，通過離子束辅助反應法(; Ion Assist Reaction)分別進行表面處理。其後，在進行過表面處理的7個硬 性基板中的6個硬性基板上’通過DC塗敷法或者離子束塗敷法，以約lnm Ό 或者3腿的厚度不連續地分別蒸鐘了鎳、錄/鉻的合金、鎳/銅的合金的金屬 觸媒層（130a)。其後，通過與金屬觸媒層⑽〇的形成方法相同的塗敷 法，在8個硬性基板上，以500nm的厚度將包含鋼的金屬晶種層（14〇)進 行乾式蒸鍍。之後，如圖5⑷或圖5 (b)所示，對於金屬晶種層⑽） 的整個面執行電锻’以20叫的厚度形成銅錄金層〇5〇)，從而製造了 8 個印刷電路板。分別測量了形成有銅鍍金層（15〇)的8個印刷電路板 性基板（110)和金屬晶種層（140)之間的剝離強度。最後，去除包括在 鍍金層（15〇)内產生的氫氣、流入到錄金層（15〇) 0的水分等的各種因 素，為了鍍金層（150)的應力緩和以及穩定化，在啊的加熱溫度下對 〇 於8個印刷電路板進行了 60分鐘的加熱。在加熱工序後，分別測量了 8個 印刷電路板的硬性基板（110)和金屬晶種層（14〇)之間的剝離強度。 在上述實驗1至實驗3中分別測量的剝離強度如表i所示。根據該表 可知’與不包括金屬觸媒層（13〇a)的印刷電路板相比，包括金屬觸媒層 (130a)的印刷電路板的剝離強度更強，與未執行表面處理工序的印刷電 路板相比，執行了表面處理工序的印刷電路板的剝離強度更強。另外，還 可以知道’與執行加熱工序之前相比，執行加熱工序之後的印刷電路板的 剝離強度進一步被增強。 上述實施例用於說明本發明，本發明並不限定於這些實施例，在本發 明的範圍内可以使用各種實施例。另外，雖然未進行說明，但是可以認為 等價的方法也結合到本發明。因此’本發明的真正的保護範圍應由申請專 200945974 ' 利範圍限定。 產業上的可利用性 根據本發明’通過金屬觸媒層和加熱工序，電鑛後產生的硬性基板和 金屬晶種層之間的枯結力下降現象得以缓和以及保持，可迅速恢復粘結力 以及可以實現穩定化’其中，所述催化層連績或不連續地形成在進行過表 面處理的硬性基板和金屬晶種層之間。另外，利用硬性基板和金屬晶種層 之間的枯結力變得強大的電鍍用基板，以半加方式可製造包含線（line)以 及間隙（space)分別為15师以下的細微電路圖案的印刷電路板。 【圖式簡單說明】 〇 圖Ka)〜(d)是表示本發明一實施例的電鍍用基板的製造過程的剖視圖； 圖2(a)〜(d)是表示本發明另一實施例的電鍵用基板的製造過程的剖視圖； 圖3(a)〜(g)是表示本發明一實施例的印刷電路板的製造過程的剖視圖； 圖4⑷〜(g)是表示本發明另一實施例的印刷電路板的製造過程的剖視圖； 以及 圖5是實驗用印刷電路板的剖視圖，其中圖5 (a)是在圖1 (d)所示的電 鍵用基板的整個表面上電鑛後進行加熱處理的試驗用印刷電路板的剖視 圖，圖5 (b)是與圖5 (a)所示的印刷電路板對照用的不包括金屬觸媒層 的印刷電路板的剖視圖。 〇 【主要元件符號說明】 101、102電鍍用基板 110 硬性基板 120 表面處理層 130a、130b金屬觸媒層 140 金屬晶種層 141 金屬晶種層 150、220鍍金層 20卜202印刷電路板 210、211 幹臈 11Plasma), surface treatment of 8 rigid substrates containing ABF (ajinomoto build-up film) and BT (bismaleimide triazine) raw materials, or using Dc coating method or ion beam coating method without surface treatment On each of the rigid substrates, a nickel/cobalt alloy or a nickel/copper alloy metal catalyst layer (13〇a) was vapor-deposited discontinuously at a thickness of about 1 nm or 3 nm. Thereafter, the metal seed layer (140) containing copper was subjected to dry vapor deposition on a thickness of 500 nm on the eight rigid substrates by the same coating method as the method of forming the metal catalyst layer (13〇a). Then, as shown in FIG. 5(a) or FIG. 5(b), 'plating is performed on the entire surface of the metal seed layer (14〇)', and a copper gold plating layer (150) is formed with a thickness of 20 μm, thereby producing 8 printings. Circuit board. The peel strength between the rigid substrate (11〇) 200945974 and the metal seed layer (140) of the eight printed circuit boards on which the copper gold plating layer (150) was formed was measured. Finally, the various factors including the moisture generated in the gold plating layer (15 〇) and the water flowing into the gold plating layer (15G) are removed, and the stress relaxation and stabilization of Qian Jinguang (150) are at 8 ( At the heating temperature of rc, eight printed circuit boards were heated for 60 minutes. After the heating process, peeling between the rigid substrate (110) and the metal seed layer (140) of eight printed circuit boards was measured. Strength (Experiment 3) _ Surface treatment of one of the eight rigid substrates containing FR-4 (flameretard)-4, for other rigid substrates, as shown in Table ,, by ion beam assisted reaction (; Ion Assist Reaction) separately subjected to surface treatment. Thereafter, on 6 rigid substrates of 7 hard substrates subjected to surface treatment, 'by DC coating method or ion beam coating method, about 1 nm Ό or 3 legs The metal catalyst layer (130a) of nickel, the alloy of the recording/chromium, and the alloy of nickel/copper is vapor-deposited discontinuously. Thereafter, the coating method is the same as the method of forming the metal catalyst layer (10). On 8 rigid substrates, will be included in a thickness of 500nm The metal seed layer (14 〇) is subjected to dry evaporation. Thereafter, as shown in FIG. 5 (4) or FIG. 5 (b), electric forging is performed on the entire surface of the metal seed layer (10)). The gold layer was 〇5〇), resulting in 8 printed circuit boards. The peel strength between the eight printed circuit board substrates (110) on which the copper gold plating layer (15 turns) and the metal seed layer (140) were formed was measured, respectively. Finally, various factors including hydrogen gas generated in the gold plating layer (15 Å), moisture flowing into the gold plating layer (15 Å) 0, and the like are removed, and the stress is moderated and stabilized for the gold plating layer (150). The heating of the eight printed circuit boards was carried out for 60 minutes at a temperature. After the heating process, the peel strength between the rigid substrate (110) and the metal seed layer (14 Å) of the eight printed circuit boards was measured. The peel strengths measured in the above Experiments 1 to 3, respectively, are shown in Table i. According to the table, it is understood that the printed circuit board including the metal catalyst layer (130a) has a stronger peeling strength than the printed circuit board not including the metal catalyst layer (13a), and the printing is performed without performing the surface treatment process. The peeling strength of the printed circuit board on which the surface treatment process is performed is stronger than that of the circuit board. Further, it is also known that the peeling strength of the printed circuit board after the execution of the heating process is further enhanced as compared with before the execution of the heating process. The above embodiments are intended to illustrate the invention, and the invention is not limited to the embodiments, and various embodiments may be employed within the scope of the invention. Further, although not illustrated, it is considered that an equivalent method is also incorporated in the present invention. Therefore, the true scope of protection of the present invention should be limited by the scope of the application. INDUSTRIAL APPLICABILITY According to the present invention, by the metal catalyst layer and the heating process, the phenomenon of a decrease in the dry force between the hard substrate and the metal seed layer generated after the electric ore is alleviated and maintained, and the adhesion can be quickly restored. And stabilization can be achieved, wherein the catalytic layer is formed continuously or discontinuously between the hard substrate and the metal seed layer subjected to the surface treatment. In addition, a substrate for plating which has a strong dryness between a hard substrate and a metal seed layer can be manufactured in a semi-additive manner by a fine circuit pattern including a line and a space of 15 divisions or less. A printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2(a) to (d) are cross-sectional views showing a manufacturing process of a substrate for plating according to an embodiment of the present invention; and FIGS. 2(a) to 2(d) are diagrams showing a key of another embodiment of the present invention; Fig. 3 (a) to (g) are cross-sectional views showing a manufacturing process of a printed circuit board according to an embodiment of the present invention; and Figs. 4 (4) to (g) are printing showing another embodiment of the present invention; A cross-sectional view of a manufacturing process of the circuit board; and FIG. 5 is a cross-sectional view of the experimental printed circuit board, wherein FIG. 5(a) is subjected to heat treatment after electro-mineralization on the entire surface of the substrate for a key shown in FIG. 1(d) A cross-sectional view of the test printed circuit board, and Fig. 5(b) is a cross-sectional view of the printed circuit board not including the metal catalyst layer for comparison with the printed circuit board shown in Fig. 5(a). 〇 [Main component symbol description] 101, 102 plating substrate 110 rigid substrate 120 surface treatment layer 130a, 130b metal catalyst layer 140 metal seed layer 141 metal seed layer 150, 220 gold plating layer 20 202 printed circuit board 210, 211 Cognac 11