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TWI291221B - Printed circuit board, flip chip ball grid array board and method of fabricating the same - Google Patents

Printed circuit board, flip chip ball grid array board and method of fabricating the same Download PDF

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Publication number
TWI291221B
TWI291221B TW095101000A TW95101000A TWI291221B TW I291221 B TWI291221 B TW I291221B TW 095101000 A TW095101000 A TW 095101000A TW 95101000 A TW95101000 A TW 95101000A TW I291221 B TWI291221 B TW I291221B
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TW
Taiwan
Prior art keywords
resin
base substrate
layer
insulator
bare
Prior art date
Application number
TW095101000A
Other languages
Chinese (zh)
Other versions
TW200633176A (en
Inventor
Hong-Won Kim
Seung-Chul Kim
Chang-Hyun Nam
Original Assignee
Samsung Electro Mech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW200633176A publication Critical patent/TW200633176A/en
Application granted granted Critical
Publication of TWI291221B publication Critical patent/TWI291221B/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The current invention relates to a flip chip ball grid array board, in which a thin unclad type core and a semi-additive process are used to form a circuit pattern, thereby providing a highly dense circuit pattern and an ultrathin core, and to a method of fabricating such a flip chip ball grid array board.

Description

1291221 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種印刷電路板，尤指一種覆晶球柵陣 列板（FC-BGAB)及其製造方法，特別是指一種於FC-BGAB 5 中，薄裸型核板（thin unclad type core )與半加成製程係被 使用於印刷電路圖案之形成，藉此提供高密度電路圖案與 超薄核板，並指一種製造印刷電路板的方法，特別是指覆 晶球柵陣列板。 10 【先前技術】 近來，隨著半導體設備的效能大幅改善，封裝基板 (packaging substrate)係需要具有相當的性能。典型地， 有需要對封裝基板設計成具有高密度、高速、及縮減尺寸 與設計成實現系統封裝。 15 此封裝基板例如為FC-BGAB，其應具有細微的電路圖 案、高電氣特性、高可靠度、及高速訊號遷移結構，且超 薄、並依半導體設備需求而定。 例如：依據在2007年FC-BGAB的技術趨勢而言，一個 FC-BGAB被預設成：0.2 mm的厚度以及具有10 um/10 um的 20 L/S之電路圖案，其中L係指線寬，以定義線的寬度，S係指 線之間的距離。 圖1A〜1H為製造習知FC-BGAB製程的連續剖視圖，圖2 為習知FC-BGAB問題的剖視圖。 如圖1A所示，由增強材料與樹脂所組成之絕緣層11的 5 1291221 兩個表面係覆蓋有銅f|12，12，，以準備成—㈣基板（ccl) 10 ° 如圖1B所示，通孔a被處理通過CCL 1〇以連接CCL 1〇 之上層與下層銅箔12，12,的電路。 5 >圖1C所示’為了電性連接形成的通孔a，無電鍍銅層 13，13’形成在CCL 10上層與下層銅箔12，12，之上，且形成在 CCL 10中的通孔a的内壁。 如圖1D所示，銅電鍍層14，14，形成於在ccl 1〇上層與 I 下層銅猪12，12,之無電鑛銅層13，13,的上面，且形成在ccl 10 1〇中的通孔a的内壁。 如圖1E所示，具有電鍍内壁之通孔以系被填滿導電膠 15，俾能在其中不具有空隙。 5 如圖1?所示，乾膜20,20’被塗佈於銅電鍍層14，14，上層 /、下層上、、二曝光及顯影後以形成一银刻抗银圖案。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a printed circuit board, and more particularly to a flip chip ball grid array board (FC-BGAB) and a method of fabricating the same, and more particularly to FC-BGAB 5 In the middle, a thin unclad type core and a semi-additive process are used for forming a printed circuit pattern, thereby providing a high-density circuit pattern and an ultra-thin core plate, and a method of manufacturing a printed circuit board. In particular, it refers to a flip chip ball grid array board. 10 [Prior Art] Recently, as the performance of semiconductor devices has been greatly improved, a packaging substrate is required to have comparable performance. Typically, there is a need to design package substrates that are high density, high speed, and downsized and designed to implement system packaging. 15 This package substrate is, for example, FC-BGAB, which should have a fine circuit pattern, high electrical characteristics, high reliability, and high-speed signal migration structure, and is ultra-thin and depends on the requirements of semiconductor devices. For example, according to the technical trend of FC-BGAB in 2007, an FC-BGAB is preset to a thickness of 0.2 mm and a circuit pattern of 20 L/S with 10 um/10 um, where L is the line width To define the width of the line, S is the distance between the lines. 1A to 1H are continuous cross-sectional views showing a conventional FC-BGAB process, and Fig. 2 is a cross-sectional view showing a conventional FC-BGAB problem. As shown in FIG. 1A, the surface of 5 1291221 of the insulating layer 11 composed of a reinforcing material and a resin is covered with copper f|12, 12, to prepare a substrate (ccl) 10 ° as shown in FIG. 1B. The via hole a is processed through the CCL 1 〇 to connect the upper layer of the CCL 1 与 with the underlying copper foil 12, 12, the circuit. 5 > shown in FIG. 1C, 'the electroless copper layers 13, 13' are formed on the upper and lower copper foils 12, 12 of the CCL 10 for the via holes a formed by the electrical connection, and are formed in the CCL 10 The inner wall of the hole a. As shown in FIG. 1D, copper plating layers 14, 14 are formed on the upper surface of the ccl 1 and the lower copper pigs 12, 12, and the electroless copper layers 13, 13 are formed on the ccl 10 1〇. The inner wall of the through hole a. As shown in FIG. 1E, the through hole having the plated inner wall is filled with the conductive paste 15, and there is no void therein. 5 As shown in Fig. 1, the dry film 20, 20' is applied to the copper plating layers 14, 14, the upper layer, the lower layer, the second exposure layer, and developed to form a silver-etched anti-silver pattern.

15 ^如圖1G所示，具有適用蝕刻阻質之乾膜20,20,的CCL 1〇係被浸泡在蝕刻液中，藉此移除部份上層與下層銅箔 > 12，12’、無電錢鋼層13，13，、及銅電錢層14，14,，前述移除 部份係對應乾膜2〇,2〇,之預設圖案。 如圖1H所示，乾膜2〇,2〇，自CCL 1〇之上表面與下表面 20移除，藉此準備習知FC-BGAB的核板。 坆種製造FC-BGAB的方法已揭露於韓國專利第 190622號，中請於咖年…则，由本案中請人所 的。 然而，由於習>FC_BGAB使用厚的CCL 1〇作為核板， 6 1291221 其具有一整個增加的厚度且因此造成難以製造具有〇2 mm 或更少厚度的超薄基板。 此外’習知FC-BGAB有其缺點，係因在圖1〇所示之蝕 刻處理中，電路圖案的侧表面沿著銅箔12，12，、無電鍍銅層 5 n，13’、及銅電鍍層14，14,的所有厚度皆被蝕刻。因此，習 知FC-BGAB的真實電路圖案如圖2所示。 因此，於習知FC-BGAB中，核板之電路圖案的l/s實際 上係不會形成50μπι/50μηι或更少。 ^ 因此，習知FC-BGAB之核板的上層與下層電路圖案很 1〇難達，細微的程度，且習知FC-BGAB因此無法滿足高密 度、回速、或縮減尺寸等要求，且亦因此不適合使於用封 裝中的系統。 另外，必須注意地，上述難蟬係適用於所有和 FC-BGAB—樣的印刷電路板。 15 【發明内容】 θ因此，本發明已經記住上述發生於相關技術領域的問 題，且本發明之一目的在於提供一印刷電路板，尤指一種 具有高密度電路圖案與超薄核板之fc_bgab。 ί0 本發明之另一目的係在提供一種製造如此fc-bgab 的方法。 為達成上述目的，本發明提供一種1^_]6(3八8，包括一 =’該核板包括··—具有表面_度與包括增強材料及 树月曰之基礎基板；在該基礎基板之預設圖案所形成的無電 7 1291221 鍍層；以及形成於無電鍍層之上的電鍍層。 於本發明之FC-BGAB中，基礎基板較佳為裸型絕緣 體’其係包括增強材料及樹脂。 於本發明之FC-BGAB中，基礎基板較佳地包括裸型絕 5緣體以及複數樹脂層，裸型絕緣體包括增強材料及樹脂， 該等樹脂層能具有粗糙度且被塗怖於裸型絕緣體的兩個表 面0 此外’本發明提供一種製造FC_BGAB的方法，包括下 述步驟：（A)提供包括增強材料及樹脂之基礎基板；（B) 1〇於該基礎基板上形成粗糙度；（C)於該具有表面粗糙度之 基礎基板上形成無電鍍層；（D)於該無電鍍層之上形成預 設電鍍抗蝕圖案；（E)於該無電鍍層之對應電鍍抗蝕圖案 沒有被形成部分形成電鍍層；（F)移除電鍍抗蝕圖案；以 及（G)對應電鍍層沒有被形成之部份移除無電鍍層，藉此 15 製造一核板。 曰 於本發明FC-BGAB之製造方法中，步驟（a)較佳藉 由提供作為基礎基板之裸型絕緣體來實施，該裸型絕緣^ 包括增強材料及樹脂，且步驟（B)較佳透過於該裸型絕緣 體上形成粗糙度來實現。 20 於本發明FC-BGAB之製造方法中，步驟（A)較佳藉 由提供作為基礎基板之裸型絕緣體與樹脂層來實施，該^ 型絕緣體包括增強材料及複數樹脂層，該等樹脂層能具有 粗糙度且被塗佈於裸型絕緣體的兩個表面，且步驟（B)較 佳透過於该能具有粗糖度之樹脂層上形成粗輪度來實現。 8 1291221 * 【實施方式】 下述，本發明FC-BGAB及其製造方法的詳細說明將會 被提供，有關其說明敬請參照所提供之圖式。 圖3A〜3H係本發明第一較佳實施例之製造fc_bgab製 5 程的連續剖視圖。 如圖3A所示，準備一超薄裸型絕緣體U1。 超薄裸型絕緣體111較佳由樹脂所組成，增強材料包括 Φ 於該樹脂中，樹脂例如可為環氧樹脂、聚亞醯胺、或酸馬 來醯胺三氮樹脂（Bismaleinide Triazine; Βτ樹脂），增強 10材料例如可為玻璃纖維、芳綸（aramid)、或紙。曰 若使用不具有增強材料的樹脂作為超薄裸型絕㈣ ⑴，對於核板而言，將可能會有不符物理特性需求的問 題，諸如強度、硬度、或熱膨脹逮率。 如圖3B所示，通孔A穿透超薄裸型絕緣體111而形成， 15以連接超薄裸型絕緣體Hi之上層電路與下層電路。 通孔A較佳於-種方式形成，諸如在預設位置使用CNC (電腦數控設備）鑽孔或雷射鑽孔來形成通孔A。 、如圖3C所示，超薄裸型絕緣體⑴之上表面及下表面與 通孔A之内壁經歷表面處理而形成粗糙度表面，以增加 20下來的鍍銅製程中和銅的黏著度。 。上述表面處理係可使用化學製程(例如：除膠渣製 釭）、電漿製程、或化學機械研磨製程。 如圖3D所^為了電性連接超薄裸型絕緣體⑴之上表 面及下表面與為了在超薄裸型絕緣體⑴之上形成電路圖 9 1291221 案，作為晶種層之無電鍍銅層12,係形成於超薄裸型絕 緣體ill之上表面與下表面，且形成於超薄裸型絕緣體η 1 中的通孔a的内壁。 無電鍍銅層112，112,係利用催化沉積製程或濺鍍製程 5 來形成。 特別地，無電鍍銅層112，112,透過催化沉積製程形成於 超薄裸型絕緣體111的兩個表面上，且形成於超薄裸型絕緣 體111中的通孔A的内壁，其中催化沉積製程包括下述步 1 驟：清洗、微蝕、預先催化、催化、加速化、無電鍍銅、 10 及防止氧化。 在其他實施中，無電鍍銅層112，112,可透過濺鍍形成於 超薄裸型絕緣體111的兩個表面上，且形成於超薄裸型絕緣 體111中的通孔A的内壁，其中在濺鍍製程中，氣體離子粒 子（例如：Ar+ )藉由電漿撞擊銅靶材所產生。 15 如圖3E所示，與電路圖案相對應的電鍍抗蝕圖案 120，120’形成於無電鍍銅層112，112,的上面與下面。 丨 電鑛抗蝕圖案120，120,使用乾膜或感光液來形成。 上述乾膜或感光液被塗佈於無電鍍銅層112，112，之 上。接著’藉由具有預設圖案之光罩的使用，乾膜或感光 20液被曝光與顯影，藉此將乾膜或感光液形成電鍍抗蝕圖案 120，120,。 、 就其本身而論，感光液的使用係更佳的，因為感光液 的塗佈係比乾膜薄，以此形成較細微的電路圖案。此外， 於此例子中無電鍍銅層丨^ 12,的上表面與下表面係不對 1291221 _ 稱，其係可均勻地被填滿感光液。 如圖3m示’對應電鑛抗㈣案12G，12G，沒有形成的部 份’銅钱層113，113,形成於無讀銅層112，112，的上面與 下面以及形成於通孔A之中。 5 銅電鐘層113，113,以一種諸如基板被浸泡在銅電鍍池 中，以利用直流（DC)整流器來引導銅電鍍的方式形成。 就其本身而論，該銅電鍍製程較佳為藉由下述方式處理， 計算電鍍區域，然後提供一所需之預設電流，以利用直流 整流裔電鍵所什鼻之區域，以沉積銅。 10 銅電鍍製程係有其優點，因為銅電鍍層對於無電鍍銅 層112，112’具有物理特性優勢，且銅電鍍層容易形成厚的厚 度。 5當銅電鍍線路對於使用於銅電鍍層113，113，的形成 冲，可各別地形成銅電鍍線。然而，於本發明較佳實施例 15中，對於銅電鍍層113，丨13’的形成，無電鍍銅層112，112,係 較佳地用來作為銅電鍍線路。 # 如圖3G所示，移除電鍍抗蝕圖案120,120,。 如圖3H所示，用以喷灑蝕刻液於該基板之快速蝕刻製 程係被引導，藉此移除對應銅電鍍層沒有形成部分的無電 20 鍍銅層 112，112,。 之後，製作一絕緣層薄板程序、形成通孔A、形成無電 錢銅層112，112’、及形成銅電鍍層113，113,等步驟係重複地 貫行’直到所要的層數被獲得為止。隨後，再額外形成阻 焊漆、電鍍鎳/金、及形成輪廓，以此方式製造本發明第一 11 1291221 ， 實施例所要的FC-BGAB。 於第一實施例所製造的FC-BGAB中，由於電鍍抗蝕圖 案 120,120’利用光傳導直線方式（Hght traveling straight) 來形成’如圖3E所示，該等電鍍抗蝕圖案120,120,側表面係 5 垂直於無電鍍銅層112,112，。因此，銅電鍍層113,113,的側 表面亦垂直於無電鍍銅層112,112,，如圖3G所示。 第一貫施例之FC-ΒΘΑΒ，由於非常薄的無電鍵銅層 112，112’被鍅刻，如圖3H所示，核板之上面與下面電路圖 _ 案的邊緣蝕刻會發生的情況非常小。 10 因此，第一實施例之FC-BGAB能夠具有核板的電路圖 案’且核板具有1〇μιη/ 1〇μιη或更少的L/s，其中L係指線寬， 定義線的寬度，S係指線與線之間的距離。 此外，第一實施例iFC_BGAB可以碑製造成具有〇·2 mm或更小的厚度，由於超薄裸型絕緣體1U的使用以形成 15 核板，係顯示於圖3 A。 現在翻至圖4A〜4H，係顯示本發明第二實施例之製造 _ FC-BGAB製程的連續剖視圖。於製造FC-BGAB製程中，使 用不具有表面粗糙度的裸型絕緣體以形成一核板。 如圖4A所示，準備基礎基板21〇，其包括有超薄裸型絕 20緣體211以及能夠具有表面粗糙度與塗佈於該超薄裸型絕 緣體211之兩面的樹脂層212,212,。 此裸型絕緣體211較佳地包括樹脂，增強材料包括於該 树月曰中树知例如可為環氧樹脂、聚亞醯胺、或bt樹脂， 增強材料例如可為玻璃纖維、芳綸（aramid)、或紙。 12 1291221 具有表面粗糙度之樹脂層212,212,係由ABF (Ajinomoto Build_upFilm)或聚亞醯胺所形成。 如圖4B所示，通孔B穿透基礎基板210而形成，以連接 基礎基板210之上層電路與下層電路。 5 通孔B以一種諸如在預設位置使用CNC鑽孔或雷射鑽 孔的方式來形成通孔B。 如圖4C所示，能夠具有粗糙度之樹脂層212,212,與通 I 孔B之内壁的表面，經由表面處理以形成粗縫度，俾能增加 在接下來的鍍銅製程中和銅的黏著度。 10 上述表面處理係可使用化學製程（例如：除膠渣製 程）、電漿製程、或CMP製程。 如圖4D所示，為了電性連接基礎基板210之上表面與下 表面與為了在基礎基板210之上形成電路圖案之目的，作為 晶種層之無電鍍銅層213,213,係形成於能夠具有粗糙度之 15 樹脂層212,212’的表面，且形成於通孔b的内壁。 無電鍍銅層213,213’係利用催化沉積製程或濺鍍製程 來形成。 如圖4E所示，與電路圖案相對應的電鍍抗餘圖案 220,220’形成於能夠具有粗糙度之樹脂層212,212，的表面。 20 電鍍抗蝕圖案120，120’使用乾膜或感光液來形成。 如圖4F所示，對應電鍍抗蝕圖案220,220,沒有形成的部 份’銅電鍍層214,214’被提供於能夠具有上面粗糙度與下面 粗糙度之樹脂層212,212’上以及形成於通孔b之中。 銅電鍍層214,214’以一種諸如基板被浸泡在銅電鍍池 13 1291221 • 中，以利用DC整流器來引導銅電鍍的方式形成。銅電鍍製 程較佳為藉由下述方式處理，計算電鍍區域，然後提供一 所需之預設電流，以利用DC整流器電鍍所計算之區域，以 沉積銅。 5 如圖4G所示，移除電鍍抗蝕圖案220,220,。 如圖4H所示，用以喷灑蝕刻液於該基板之快速蝕刻製 程係被引導，藉此移除對應銅電鍍層沒有形成部分的無電 鍍銅層213,213’。 馨 之後，製作一絕緣層薄板程序、形成通孔B '形成無電 10 鍍銅層213,213’、及形成銅電鍍層214,214,等步驟係重複地 實行，直到所要的層數被獲得為止。隨後，再額外形成阻 焊漆、電鑛鎳/金、及形成輪廓，以此方式製造本發明第二 實施例所要的FC-BGAB。 6 第二實施例所製造的FC-BGAB中，由於使用由ABF或 15 聚亞醯胺製造的樹脂層212,212,以形成粗糙度，核板的電路 圖案，其具有一 ΙΟμίϋ/ΙΟμιη的L/S或更少，其中L係指線寬， φ 定義線的寬度，S係指線間的距離，甚至可形成於不具有粗 轅度的超薄裸型絕緣體211上。 於一較佳實施例中，本發明之fc_bgab的銅電鍍層不 2〇 限於完全由純銅組成的電鍍層，但意謂大部份由銅所組成 之電鍍層。這可以藉由使用分析設備分析銅電鍍層的化學 組成物來被檢驗。分析設備例如為χ射線能量散佈分析儀 (EDAX) ’係典型地被提供成一掃瞄電子顯微鏡。 此外’於一較佳實施例中，本發明FC-BGAB的電鍍層 1291221 可以依據需要來由傳導材質形成，諸如：金（Au)、鎳（Ni)、 錫（Sn)等，此外還有銅（Cu)。 同時’上述實施例大部分地揭露利用FC_BGab的便利 性。然而，明顯的本發明之特徵應用於多數包括有F c _ B G A B =P刷電路板。換言之，各式各樣修改的實施例可以被製 1於所有的印刷電路板中，其中在該印刷電路板中，薄裸 5L核板與半加成製程係被使用於電路圖案之形成，藉此提 > 供高密度電路圖案與超薄核板。 —如上所述，本發明提供FC-BGAB及其製造方法。依據 10該^姻心及其製造方法，由於使用薄裸型核板與半加成 製％於電路圖案之形成，所以可提供高密度電路圖案與超 此外，依據該FC-BGAB及其製造方法，能夠具有粗糙 度之樹脂可以被塗佈於裸型絕緣體上。因此，雖然使用不 具有粗糙度之薄裸型絕緣體，但仍可提供具有高密度電路 圖案之核板。15 ^ As shown in FIG. 1G, the CCL 1 lanthanum having the dry film 20, 20 suitable for etching resistance is immersed in the etching liquid, thereby removing part of the upper and lower copper foils > 12, 12', The electroless steel layer 13, 13 and the copper electric money layer 14, 14 are replaced by a predetermined pattern corresponding to the dry film 2〇, 2〇. As shown in Fig. 1H, the dry film 2 〇, 2 〇 was removed from the upper surface and the lower surface 20 of the CCL 1 ,, thereby preparing a conventional nuclear plate of FC-BGAB. The method of manufacturing FC-BGAB has been disclosed in Korean Patent No. 190622, which is in the year of the coffee... then, in this case, the person in charge of the case. However, since the <FC_BGAB uses a thick CCL 1 〇 as a core plate, 6 1291221 has an overall increased thickness and thus makes it difficult to manufacture an ultra-thin substrate having a thickness of 〇 2 mm or less. In addition, the conventional FC-BGAB has its disadvantages because the side surface of the circuit pattern is along the copper foil 12, 12, the electroless copper plating layer 5 n, 13', and copper in the etching process shown in FIG. All thicknesses of the plating layers 14, 14 are etched. Therefore, the actual circuit pattern of the conventional FC-BGAB is shown in Fig. 2. Therefore, in the conventional FC-BGAB, the l/s of the circuit pattern of the core plate does not actually form 50 μm / 50 μm or less. ^ Therefore, the upper and lower circuit patterns of the nuclear board of the FC-BGAB are very difficult, subtle, and the FC-BGAB cannot meet the requirements of high density, speed, or size reduction. Therefore, it is not suitable for use in a system in a package. In addition, it must be noted that the above difficulties are applicable to all FC-BGAB-like printed circuit boards. 15 [Abstract] Therefore, the present invention has already in mind the above-mentioned problems occurring in the related art, and an object of the present invention is to provide a printed circuit board, especially a fc_bgab having a high-density circuit pattern and an ultra-thin nuclear plate. . Another object of the present invention is to provide a method of manufacturing such an fc-bgab. In order to achieve the above object, the present invention provides a substrate having a surface _degree and a base substrate including a reinforcing material and a tree raft; on the base substrate, The electroless 7 1291221 plating formed by the predetermined pattern; and the electroplated layer formed on the electroless plating layer. In the FC-BGAB of the present invention, the base substrate is preferably a bare insulator which includes a reinforcing material and a resin. In the FC-BGAB of the present invention, the base substrate preferably includes a bare-type rim body and a plurality of resin layers, and the bare-type insulator includes a reinforcing material and a resin, and the resin layers can have roughness and are coated on the bare type. Two surfaces of the insulator 0 In addition, the present invention provides a method of manufacturing FC_BGAB, comprising the steps of: (A) providing a base substrate comprising a reinforcing material and a resin; (B) forming a roughness on the base substrate; C) forming an electroless plating layer on the base substrate having surface roughness; (D) forming a predetermined plating resist pattern on the electroless plating layer; (E) the corresponding plating resist pattern on the electroless plating layer is not Formed part Forming a plating layer; (F) removing the plating resist pattern; and (G) removing the electroless plating layer from the portion where the plating layer is not formed, thereby fabricating a core plate. 曰 Manufacturing of the FC-BGAB of the present invention In the method, the step (a) is preferably carried out by providing a bare insulator as a base substrate, the bare insulator comprising a reinforcing material and a resin, and the step (B) preferably forming a roughness on the bare insulator. In the manufacturing method of the FC-BGAB of the present invention, the step (A) is preferably carried out by providing a bare insulator and a resin layer as a base substrate, the insulator comprising a reinforcing material and a plurality of resin layers, The resin layer can have roughness and is applied to both surfaces of the bare insulator, and the step (B) is preferably carried out by forming a coarse rotation on the resin layer having a coarse sugar content. 8 1291221 * [Implementation MODES OF THE INVENTION The following detailed description of the FC-BGAB of the present invention and its manufacturing method will be provided, and the description thereof will be referred to the drawings provided. Figures 3A to 3H show the manufacture of fc_bgab according to the first preferred embodiment of the present invention. Continuous process As shown in Fig. 3A, an ultra-thin bare insulator U1 is prepared. The ultra-thin bare insulator 111 is preferably composed of a resin, and the reinforcing material includes Φ in the resin, and the resin may be, for example, epoxy resin or polyarylene. An amine, or an acid maleimine triazine resin (Bismaleinide Triazine; Βτ resin), the reinforcing material 10 can be, for example, glass fiber, aramid, or paper. If a resin having no reinforcing material is used as the ultra-thin bare Type (4) (1), for the nuclear board, there may be problems that do not meet the physical characteristics, such as strength, hardness, or thermal expansion rate. As shown in Figure 3B, the through hole A penetrates the ultra-thin bare insulator 111. Formed, 15 to connect the ultra-thin bare insulator Hi upper layer circuit and the lower layer circuit. The through hole A is preferably formed in a manner such as a through hole A using a CNC (Computer Numerical Control Equipment) drilling or a laser drilling at a preset position. As shown in Fig. 3C, the upper surface and the lower surface of the ultra-thin bare insulator (1) and the inner wall of the through hole A are subjected to surface treatment to form a roughness surface to increase the adhesion of copper to the copper plating process. . The above surface treatment may be carried out using a chemical process (for example, a desmear process), a plasma process, or a chemical mechanical polishing process. As shown in FIG. 3D, in order to electrically connect the upper surface and the lower surface of the ultra-thin bare insulator (1) and to form a circuit pattern 9 1291221 on the ultra-thin bare insulator (1), the electroless copper layer 12 as a seed layer is used. The upper surface and the lower surface of the ultra-thin bare insulator ill are formed, and are formed in the inner wall of the through hole a in the ultra-thin bare insulator η 1 . The electroless copper plating layers 112, 112 are formed by a catalytic deposition process or a sputtering process 5. Specifically, the electroless copper plating layers 112, 112 are formed on both surfaces of the ultra-thin bare insulator 111 by a catalytic deposition process, and are formed on the inner wall of the via hole A in the ultra-thin bare insulator 111, wherein the catalytic deposition process This includes the following steps: cleaning, microetching, pre-catalysis, catalysis, accelerating, electroless copper plating, 10 and preventing oxidation. In other implementations, the electroless copper plating layers 112, 112 are formed on both surfaces of the ultra-thin bare insulator 111 by sputtering, and are formed on the inner walls of the via holes A in the ultra-thin bare insulator 111, wherein In the sputtering process, gas ion particles (for example, Ar+) are generated by plasma impinging on a copper target. As shown in Fig. 3E, plating resist patterns 120, 120' corresponding to the circuit patterns are formed on the upper and lower surfaces of the electroless copper plating layers 112, 112.丨 Electrode resist patterns 120, 120 are formed using a dry film or a photosensitive liquid. The above dry film or photosensitive liquid is applied onto the electroless copper plating layers 112, 112. Then, by using the photomask having a predetermined pattern, the dry film or the photosensitive liquid 20 is exposed and developed, whereby the dry film or the photosensitive liquid is formed into the plating resist patterns 120, 120. As such, the use of the photosensitive liquid is better because the coating of the photosensitive liquid is thinner than the dry film, thereby forming a finer circuit pattern. In addition, in this example, the upper surface and the lower surface of the electroless copper plating layer 12 are not aligned with the 1291221 _, which is uniformly filled with the photosensitive liquid. As shown in Fig. 3m, the corresponding electro-mineral resistance (4) case 12G, 12G, the unformed portion 'copper layer 113, 113, formed on the upper and lower sides of the unread copper layer 112, 112, and formed in the through hole A . The copper bell layer 113, 113 is formed in such a manner that a substrate such as a substrate is immersed in a copper plating bath to direct copper plating using a direct current (DC) rectifier. For its part, the copper plating process is preferably processed by calculating the plating area and then providing a desired preset current to utilize the region of the DC rectifying key to deposit copper. The copper plating process has its advantages because the copper plating layer has physical property advantages for the electroless copper plating layer 112, 112', and the copper plating layer is liable to form a thick thickness. 5 When the copper plating line is formed for the copper plating layers 113, 113, a copper plating line can be formed separately. However, in the preferred embodiment 15 of the present invention, for the copper plating layer 113, the formation of the ruthenium 13', the electroless copper plating layers 112, 112 are preferably used as copper plating lines. # As shown in FIG. 3G, the plating resist patterns 120, 120 are removed. As shown in Figure 3H, a rapid etch process for spraying etchant onto the substrate is directed, thereby removing the uncharged 20 copper plated layers 112, 112 corresponding to portions of the copper plating. Thereafter, an insulating thin plate process is formed, through holes A are formed, copper-free copper layers 112, 112' are formed, and copper plating layers 113, 113 are formed, and the steps are repeated until the desired number of layers is obtained. Subsequently, a solder resist, an electroplated nickel/gold, and a profile are additionally formed, in such a manner that the first 11 1291221, FC-BGAB of the embodiment is produced. In the FC-BGAB manufactured in the first embodiment, since the plating resist patterns 120, 120' are formed by Hght traveling straight, as shown in FIG. 3E, the plating resist patterns 120, 120, side surface systems 5 perpendicular to the electroless copper layer 112, 112,. Therefore, the side surfaces of the copper plating layers 113, 113 are also perpendicular to the electroless copper plating layers 112, 112, as shown in Fig. 3G. In the FC-ΒΘΑΒ of the first embodiment, since the very thin electroless copper layers 112, 112' are engraved, as shown in Fig. 3H, the edge etching of the upper and lower circuit diagrams of the nuclear plate is very small. . 10 Therefore, the FC-BGAB of the first embodiment can have the circuit pattern ' of the core board' and the core board has L/s of 1 μm η / 1 〇 μηη or less, where L is the line width, defines the width of the line, S is the distance between the line and the line. Further, the first embodiment iFC_BGAB can be manufactured to have a thickness of 〇·2 mm or less, which is shown in Fig. 3A due to the use of the ultra-thin bare insulator 1U to form a 15 core plate. Turning now to Figures 4A to 4H, there is shown a continuous cross-sectional view of a manufacturing _FC-BGAB process of a second embodiment of the present invention. In the fabrication of the FC-BGAB process, a bare insulator having no surface roughness is used to form a core plate. As shown in Fig. 4A, a base substrate 21 is prepared which includes an ultra-thin bare rim 20 and a resin layer 212, 212 which can have a surface roughness and both surfaces coated on the ultra-thin bare insulator 211. The bare insulator 211 preferably comprises a resin, and the reinforcing material is included in the tree, and may be, for example, an epoxy resin, a polyamidamine, or a bt resin. The reinforcing material may be, for example, glass fiber or aramid. ), or paper. 12 1291221 Resin layer 212, 212 having surface roughness formed by ABF (Ajinomoto Build_upFilm) or polyamidamine. As shown in FIG. 4B, the via hole B is formed through the base substrate 210 to connect the upper layer circuit and the lower layer circuit of the base substrate 210. The through hole B forms the through hole B in such a manner as to use a CNC drilling or a laser drilling hole at a preset position. As shown in Fig. 4C, the resin layers 212, 212 having roughness and the surface of the inner wall of the through hole B are subjected to surface treatment to form a rough seam, which can increase the adhesion to copper in the subsequent copper plating process. 10 The above surface treatment can be performed using a chemical process (for example, a desmear process), a plasma process, or a CMP process. As shown in FIG. 4D, in order to electrically connect the upper surface and the lower surface of the base substrate 210 with the purpose of forming a circuit pattern on the base substrate 210, the electroless copper plating layers 213, 213 as the seed layer are formed to be rough. The surface of the resin layer 212, 212' is formed on the inner wall of the through hole b. The electroless copper plating layers 213, 213' are formed by a catalytic deposition process or a sputtering process. As shown in Fig. 4E, the plating resist patterns 220, 220' corresponding to the circuit patterns are formed on the surface of the resin layers 212, 212 which can have roughness. 20 The plating resist pattern 120, 120' is formed using a dry film or a photosensitive liquid. As shown in FIG. 4F, corresponding portions of the plating resist patterns 220, 220, which are not formed, are provided on the resin layers 212, 212' capable of having the upper roughness and the lower roughness and formed in the through holes b. . The copper plating layers 214, 214' are formed in such a manner that a substrate such as a substrate is immersed in a copper plating bath 13 1291221 to utilize a DC rectifier to guide copper plating. The copper plating process is preferably processed by calculating the plating area and then providing a desired preset current to electroplate the calculated area with a DC rectifier to deposit copper. 5 As shown in FIG. 4G, the plating resist patterns 220, 220 are removed. As shown in Fig. 4H, a rapid etching process for spraying an etchant onto the substrate is conducted, thereby removing the electroless copper plating layer 213, 213' corresponding to the unformed portion of the copper plating layer. After the sinter, an insulating thin plate process is formed, the through holes B' are formed to form the electroless 10 copper plating layers 213, 213', and the copper plating layers 214, 214 are formed, and the steps are repeatedly performed until the desired number of layers is obtained. Subsequently, a solder resist, an electric nickel/gold, and a profile are additionally formed, in such a manner that the FC-BGAB required in the second embodiment of the present invention is produced. 6 In the FC-BGAB manufactured in the second embodiment, since the resin layers 212, 212 made of ABF or 15 polytheneamine are used to form a roughness, the circuit pattern of the core plate has a L/S of ΙΟμίϋ/ΙΟμηη. Or less, where L is the line width, φ defines the width of the line, S means the distance between the lines, and may even be formed on the ultra-thin bare insulator 211 which does not have a roughness. In a preferred embodiment, the copper plating layer of fc_bgab of the present invention is not limited to a plating layer composed entirely of pure copper, but means a plating layer composed mostly of copper. This can be verified by analyzing the chemical composition of the copper plating layer using an analytical device. The analytical device, such as the Xenon Ray Energy Dispersion Analyzer (EDAX), is typically provided as a scanning electron microscope. In addition, in a preferred embodiment, the electroplated layer 1291221 of the FC-BGAB of the present invention may be formed of a conductive material as needed, such as gold (Au), nickel (Ni), tin (Sn), etc., in addition to copper. (Cu). Meanwhile, the above embodiment largely discloses the convenience of utilizing FC_BGab. However, it is apparent that the features of the present invention are applied to most of the circuit boards including F c _ B G A B =P. In other words, a wide variety of modified embodiments can be fabricated in all printed circuit boards in which thin bare 5L core plates and semi-additive processes are used to form circuit patterns. This mentions high-density circuit patterns with ultra-thin nuclear plates. - As described above, the present invention provides FC-BGAB and a method of manufacturing the same. According to the method and the manufacturing method thereof, since the thin bare core plate and the semi-additive system are formed in the circuit pattern, the high-density circuit pattern and the super-addition can be provided, according to the FC-BGAB and the manufacturing method thereof. The resin capable of having roughness can be coated on the bare insulator. Therefore, although a thin bare insulator having no roughness is used, a core plate having a high-density circuit pattern can be provided.

〜、疋故，本發明之]?(：：_；8<3八；3可以符合高密度、高速、及 細減尺寸等特性，且其更可應用於封裝的系統中。 20 雖然本發明較佳實施例以圖式的方式揭露，熟悉 技術者可理解各種修飾、添加或取代的可能，在不惊離本 發明的範圍及精神下以作為其申請專利範圍。 【圖式簡單說明】 圖1A〜m係製造習知FC姻Αβ製㈣連續剖視圖 15 1291221 圖2係習&FC_BGAB的問題剖視圖。 圖3A〜3H係本發明第一較佳實施例之製造FC-BGAB製 程的連續剖視圖。 圖4A〜4H係本發明第二較佳實施例之製造FC-BGAB製 5 程的連續剖視圖。 【主要元件符號說明】~, 疋 , 本 本 本 ( ( ( ( ( ( 本 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以 可以The preferred embodiments are disclosed in the drawings, and those skilled in the art can understand various modifications, additions, and substitutions, and the scope of the invention is not to be construed as the scope of the invention. 1A~m system manufacturing conventional FC marriage beta system (4) continuous cross-sectional view 15 1291221 Figure 2 is a cross-sectional view of the problem of < FC_BGAB. Figures 3A to 3H are successive cross-sectional views of the manufacturing process of the FC-BGAB of the first preferred embodiment of the present invention. 4A to 4H are continuous cross-sectional views showing a process of manufacturing FC-BGAB according to a second preferred embodiment of the present invention.

鋼箔基板Steel foil substrate

電錢抗钱圖案 無電鍍銅層 鋼電鍍層 導電膠 5 超薄裸型絕緣體 樹脂層 !〇 絕緣層 12,125 通孔 120，120’，220,220， 13，13，，112，112，，213,213, 14，14，，113，113，，214,214, 15 乾膜光阻 111,211 基板 212,212，Electric money anti-money pattern electroless copper layer steel plating conductive paste 5 ultra-thin bare insulator resin layer! 〇 insulation layer 12,125 through hole 120,120',220,220, 13,13,,112,112,,213,213, 14, 14, 113, 113,, 214, 214, 15 dry film photoresist 111, 211 substrate 212, 212,

11 a，A，B 20, 20, 21011 a, A, B 20, 20, 210

Claims (1)

1291221 十、申請專利範圍： ^ 一種覆晶球栅陣列板，包括一核板，該核板包括·· 一基礎基板，其具有表面粗糙度與包括一增強材料及 一樹脂； 5 一無電鍍層，其係形成於該基礎基板上之一預設圖案 中；以及 一電鍍層’其係形成於該無電鍍層之上。 > 2·如申請專利範圍第1項所述之覆晶球柵陣列板，其 中該基礎基板為一裸型絕緣體，其係包括該增強材料及該 10 樹脂。 3·如申請專利範圍第1項所述之覆晶球柵陣列板，其 中該基礎基板包括裸型絕緣體與複數樹脂層，該裸型絕緣 體包括該增強材料及該樹脂，該等樹脂層能具有粗糙度且 被塗佈於該裸型絕緣體之兩個表面。 15 4· 一種製造覆晶球柵陣列板的方法，包括下述步驟： (A)提供一包括一增強材料及一樹脂之基礎基板； ► (B)於該基礎基板上形成粗糙度； (C)於該具有表面粗糙度之基礎基板上形成一無電鍍 層； 20 (D)於該無電鍍層之上形成一預設電鍍抗蝕圖案； (E) 於該無電鍍層之對應該電鍍抗蝕圖案沒有被形成 部分形成一電鍍層； (F) 移除該電鍍抗蝕圖案；以及 (G) 對應該電鍍層沒有被形成之部份移除該無電鍍 17 1291221 、 層，藉此製造一核板。 5·如申請專利範圍第4項所述之方法，其中該步驟（a ) 藉由提供一作為該基礎基板之裸型絕緣體來被實施，該裸 型絶緣體包括該增強材料及該樹脂，以及該步驟（B )藉由 5 在该裸型絕緣體之上形成粗糙度來實現。 6·如申請專利範圍第4項所述之方法，其中步驟（A ) 藉由提供作為該基礎基板之裸型絕緣體以及複數樹脂層來 實施，該裸型絕緣體包括該增強材料及該樹脂，該等樹脂 齡層能具有粗糙度且被塗佈於該裸型絕緣體的兩個表面，以 10及步驟（B)藉由於該等能具有粗糙度之樹脂層上形成粗糙 度來實現。 7· —種印刷電路板，包括一核板，該核板包括·· 一基礎基板，其具有表面粗糙度與包括一增強材料及 一樹脂層； 、 15 一無電鍍層，其係形成於該基礎基板上之一預設圖案 中；以及 丨 一電鑛層，其係形成於該無電鍍層之上。 8·如申請專利範圍第7項所述之印刷電路板，其中該 基礎基板為一裸型絕緣體，其係包括該增強材料及該樹脂。 2〇 9·如申請專利範圍第7項所述之印刷電路板，其中該 基礎基板包括裸型絕緣體與複數樹脂層，該裸型絕緣體包 括該增強材料及該樹脂，該等樹脂層能具有粗糙度且被塗 佈於該裸型絕緣體之兩個表面。 18 251291221 X. Patent application scope: ^ A flip-chip ball grid array board comprising a core board, comprising: a base substrate having a surface roughness and comprising a reinforcing material and a resin; 5 an electroless plating layer And being formed in a predetermined pattern on the base substrate; and a plating layer formed on the electroless plating layer. The flip chip ball grid array board of claim 1, wherein the base substrate is a bare insulator comprising the reinforcing material and the resin. 3. The flip-chip ball grid array board of claim 1, wherein the base substrate comprises a bare insulator and a plurality of resin layers, the bare insulator comprising the reinforcing material and the resin, the resin layers having Roughness is applied to both surfaces of the bare insulator. 15 4. A method of manufacturing a flip chip grid array panel comprising the steps of: (A) providing a base substrate comprising a reinforcing material and a resin; and (B) forming a roughness on the base substrate; (C) Forming an electroless plating layer on the base substrate having surface roughness; 20 (D) forming a predetermined plating resist pattern on the electroless plating layer; (E) plating resist against the electroless plating layer The etched pattern is not formed into a plating layer; (F) removing the plating resist pattern; and (G) removing the electroless plating 17 1291221 and the layer corresponding to the portion where the plating layer is not formed, thereby fabricating a layer Nuclear board. 5. The method of claim 4, wherein the step (a) is performed by providing a bare insulator as the base substrate, the bare insulator comprising the reinforcing material and the resin, and This step (B) is achieved by forming a roughness on the bare insulator by 5. 6. The method of claim 4, wherein the step (A) is performed by providing a bare insulator as the base substrate and a plurality of resin layers, the bare insulator including the reinforcing material and the resin, The resin age layer can have roughness and is applied to both surfaces of the bare insulator, and is achieved by 10 and step (B) by forming roughness on the resin layer having roughness. 7. A printed circuit board comprising a core board, comprising: a base substrate having a surface roughness and comprising a reinforcing material and a resin layer; 15 an electroless plating layer formed on the substrate a predetermined pattern on the base substrate; and a first electric ore layer formed on the electroless plating layer. 8. The printed circuit board of claim 7, wherein the base substrate is a bare insulator comprising the reinforcing material and the resin. The printed circuit board of claim 7, wherein the base substrate comprises a bare insulator and a plurality of resin layers, the bare insulator comprising the reinforcing material and the resin, the resin layers being rough And applied to both surfaces of the bare insulator. 18 25
TW095101000A 2005-02-25 2006-01-11 Printed circuit board, flip chip ball grid array board and method of fabricating the same TWI291221B (en)

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KR20060094662A (en) 2006-08-30
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US20060191709A1 (en) 2006-08-31
TW200633176A (en) 2006-09-16

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