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WO2009005614A3 - Cellule r/w 3d à fuite inverse réduite et son procédé de fabrication - Google Patents

Cellule r/w 3d à fuite inverse réduite et son procédé de fabrication Download PDF

Info

Publication number
WO2009005614A3
WO2009005614A3 PCT/US2008/007758 US2008007758W WO2009005614A3 WO 2009005614 A3 WO2009005614 A3 WO 2009005614A3 US 2008007758 W US2008007758 W US 2008007758W WO 2009005614 A3 WO2009005614 A3 WO 2009005614A3
Authority
WO
WIPO (PCT)
Prior art keywords
diode
cell
making
semiconductor element
resistive semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2008/007758
Other languages
English (en)
Other versions
WO2009005614A2 (fr
Inventor
Tanmay Kumar
Christopher J Petti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk 3D LLC
Original Assignee
SanDisk 3D LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/819,895 external-priority patent/US7800939B2/en
Priority claimed from US11/819,989 external-priority patent/US7759666B2/en
Application filed by SanDisk 3D LLC filed Critical SanDisk 3D LLC
Priority to CN200880024858.4A priority Critical patent/CN101796588B/zh
Priority to EP08779718A priority patent/EP2165337A2/fr
Priority to JP2010514766A priority patent/JP5695417B2/ja
Publication of WO2009005614A2 publication Critical patent/WO2009005614A2/fr
Publication of WO2009005614A3 publication Critical patent/WO2009005614A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/33—Material including silicon
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Landscapes

  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif de mémoire non volatile qui comprend un élément d'orientation à diode à semi-conducteurs, et un élément de commutation de lecture/écriture à semi-conducteurs.
PCT/US2008/007758 2007-06-29 2008-06-23 Cellule r/w 3d à fuite inverse réduite et son procédé de fabrication Ceased WO2009005614A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200880024858.4A CN101796588B (zh) 2007-06-29 2008-06-23 具有减小的反向泄漏的3d读/写单元及其制造方法
EP08779718A EP2165337A2 (fr) 2007-06-29 2008-06-23 Cellule r/w 3d à fuite inverse réduite et son procédé de fabrication
JP2010514766A JP5695417B2 (ja) 2007-06-29 2008-06-23 逆方向リークが減少した３次元の読み書きセルとそれを作る方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/819,989 2007-06-29
US11/819,895 US7800939B2 (en) 2007-06-29 2007-06-29 Method of making 3D R/W cell with reduced reverse leakage
US11/819,989 US7759666B2 (en) 2007-06-29 2007-06-29 3D R/W cell with reduced reverse leakage
US11/819,895 2007-06-29

Publications (2)

Publication Number Publication Date
WO2009005614A2 WO2009005614A2 (fr) 2009-01-08
WO2009005614A3 true WO2009005614A3 (fr) 2009-03-26

Family

ID=39735143

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/007758 Ceased WO2009005614A2 (fr) 2007-06-29 2008-06-23 Cellule r/w 3d à fuite inverse réduite et son procédé de fabrication

Country Status (6)

Country Link
EP (1) EP2165337A2 (fr)
JP (1) JP5695417B2 (fr)
KR (1) KR20100049564A (fr)
CN (1) CN101796588B (fr)
TW (1) TW200908205A (fr)
WO (1) WO2009005614A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5367400B2 (ja) * 2009-02-12 2013-12-11 株式会社東芝 半導体記憶装置、及びその製造方法
JP2011165854A (ja) * 2010-02-09 2011-08-25 Toshiba Corp 記憶装置及びその製造方法
JP5422534B2 (ja) * 2010-10-14 2014-02-19 株式会社東芝 不揮発性抵抗変化素子および不揮発性抵抗変化素子の製造方法
WO2012169850A2 (fr) * 2011-06-10 2012-12-13 서울대학교산학협력단 Dispositif de mémoire non volatile tridimensionnel et procédé pour sa fabrication
WO2013044612A1 (fr) * 2011-09-29 2013-04-04 Tsinghua University Transistor à sélection verticale, cellule de mémoire, ainsi que structure tridimensionnelle de réseau de mémoire et son procédé de fabrication

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914055A (en) * 1989-08-24 1990-04-03 Advanced Micro Devices, Inc. Semiconductor antifuse structure and method
EP1376604A1 (fr) * 2002-06-21 2004-01-02 Hewlett-Packard Development Company, L.P. Structures de mémoire
WO2006078505A2 (fr) * 2005-01-19 2006-07-27 Matrix Semiconductor, Inc. Cellule de memoire non volatile comportant une couche dielectrique et un materiau a changement de phase montes en serie
US20070069276A1 (en) * 2005-09-28 2007-03-29 Scheuerlein Roy E Multi-use memory cell and memory array
US20070069217A1 (en) * 2003-12-03 2007-03-29 Herner S B P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse
US20070114508A1 (en) * 2005-11-23 2007-05-24 Matrix Semiconductor, Inc. Reversible resistivity-switching metal oxide or nitride layer with added metal

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050226067A1 (en) * 2002-12-19 2005-10-13 Matrix Semiconductor, Inc. Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material
JP2006511020A (ja) * 2002-12-20 2006-03-30 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 光情報記憶ユニット

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4914055A (en) * 1989-08-24 1990-04-03 Advanced Micro Devices, Inc. Semiconductor antifuse structure and method
EP1376604A1 (fr) * 2002-06-21 2004-01-02 Hewlett-Packard Development Company, L.P. Structures de mémoire
US20070069217A1 (en) * 2003-12-03 2007-03-29 Herner S B P-i-n diode crystallized adjacent to a silicide in series with a dielectric anitfuse
WO2006078505A2 (fr) * 2005-01-19 2006-07-27 Matrix Semiconductor, Inc. Cellule de memoire non volatile comportant une couche dielectrique et un materiau a changement de phase montes en serie
US20070069276A1 (en) * 2005-09-28 2007-03-29 Scheuerlein Roy E Multi-use memory cell and memory array
US20070114508A1 (en) * 2005-11-23 2007-05-24 Matrix Semiconductor, Inc. Reversible resistivity-switching metal oxide or nitride layer with added metal

Also Published As

Publication number Publication date
JP2010532564A (ja) 2010-10-07
EP2165337A2 (fr) 2010-03-24
TW200908205A (en) 2009-02-16
JP5695417B2 (ja) 2015-04-08
CN101796588B (zh) 2013-07-24
CN101796588A (zh) 2010-08-04
KR20100049564A (ko) 2010-05-12
WO2009005614A2 (fr) 2009-01-08

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