TW200908205A - 3D R/W cell with reduced reverse leakage and method of making thereof - Google Patents

Abstract

A nonvolatile memory device includes a semiconductor diode steering element, and a semiconductor read / write switching element.

Description

200908205 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory device and a method of manufacturing the same. The present application claims the benefit of U.S. Patent Application Serial Nos. Nos. [Prior Art]

Even when the power of the device is cut, the non-volatile memory array is still in the one-time-programmable array, and each memory cell is in an initial unprogrammed state. It is formed and can be converted into a stylized state. This change is permanent and the ones are not erasable. In other types of memory, the memory cells are erasable and can be rewritten multiple times. The unit may also be modified in terms of the &a achievable data state: by changing a certain characteristic of the price-measured unit (such as the electrical aa body in the unit> The data state is stored for a given applied voltage or a current flowing through the unit at a threshold voltage. The data status is the unique value of the unit, such as data, 〇, or data, 1, . , a solution for achieving an erasable or multi-state cell is a complex sub-gate and coffee (10) memory unit (for example) by storing charge: the presence or absence of charge stored in the eMule or The amount of change required for the competing in the transistor circuit is very small under I32477.doc 200908205 and operation. Other memory cells operate by varying the resistivity of the electrons of the opposite species (e.g., chalcogenization). It is difficult to challenge the chalcogen with the chalcogenide in the large-scale production and installation of the chalcogenide. The substantial advantage will be from the non-proportional wall, the thousand (four) materials (the structure is easy to be scaled to a small size) to form a unit of non-ΜΙ 1 μ 1 or eve state memory level 7L Non-volatile memory arrays are available. Fs

KJ SUMMARY OF THE INVENTION One embodiment provides a non-volatile memory device including a first-piece I-pole guide 70 and a semiconductor read/write switching element. Another embodiment of the present month provides - a main road threat. Ping Zhi Yu Wang's own hidden device, its Bao-Feng conductor diode guiding element, a semiconductor resistor read/write switching element, located At least one layer between the guiding element and the MX 7L 1 stem, the -f (four) (four) (four) M U conductive switching element first electrode and one electrically contacting the first electrode of the thousand § hai read/write switching element, the layer And the guiding element is arranged in series with the column electrode and the second electrode. The other embodiment provides a non-volatile memory device: a conductor diode guiding element, and a semiconductor read/write switching An element, at least a conductive acoustic member located between the guiding element and the switching element, for switching the read/write switching θ to a second resistivity state switching different from the first resistive energy The second resistivity state of the heart and is used to switch the edge/write switching element from the second resistance-state. "Wu Zhi this - Resistivity 132477.doc 200908205 Each of the aspects of the invention and the actual examples described herein can be used alone or in combination with each other. Now moxibustion 4 ☆ will now refer to the accompanying drawings The preferred embodiment and the embodiment are described. [Embodiment] It is known that the resistance of a resistor formed by a long-field doped polysilicon can be trimmed by applying an electric pulse, thereby adjusting the resistance of the positive % 穂疋Between states, these trimmerable resistors have been used as components in integrated circuits. However, conventionally, trimmed polycrystalline 7 resistors are not used to store data states in non-volatile memory cells. It is difficult to fabricate a memory array of polycrystalline (4). If a resistor is used as a memory cell in a large ss-point array, when a voltage is applied to the selected cell, the entire array In the case of the selected half of the unit and the unselected unit, there will be an improper leak. For example, turn to Figure 1, assuming that a battery is applied between the bit line B and the word line A to set, reset or sense. Selected unit s The current is intended to flow through the selected cell s. However, the n leakage current may flow over the alternate path, such as between the bit ❹ and word line A through unselected cells U1, U2, and U3. There may be many such alternative paths. In the embodiment of the present invention, the (four) leakage current can be greatly reduced by forming each memory cell into a two-terminal device including a diode and a resistor. The diode has a nonlinear IV characteristic, thereby allowing Very small electric current below the turn-on voltage and substantially higher current than the turn-on voltage. In general, the diode also acts as a one-way one that is easier to transfer current in the - direction than in the other direction. Therefore, 'as long as the bias mechanism is selected to ensure that only selected cells are subjected to a forward current higher than the turn-on voltage, I32477.doc 200908205 can be greatly reduced along unintended paths (such as Figure (4) (iv) path) Leakage current. In the practice of the present invention, a memory element formed by a semiconductor (4) (for example, a diode guiding element and a semiconductor resistor serving as a read/write switching X piece) can be reached by applying an appropriate electrical pulse. Two or more stable resistivity states. The switching elements are arranged in series, but preferably are opposite to the diode guiding parts. Preferably, the switching elements are located between the switching elements of the switching elements. One or more conductive layers (such as metal (7), (4)), metal lithium or nitride layer) are attached to the guiding element. The switching element, the guiding element and the conductive decoupling layer are arranged in series to form a non- Volatile memory cell. The blade-changing 7G component preferably comprises an amorphous 1 Å semiconductor resistor, a polycrystalline (10) semiconductor resistor, or an amorphous and polycrystalline composite semiconductor resistor. However, ^ can be used such as resistivity Other switching elements of the diode. The guiding element includes: a crystallized, low-resistivity polycrystalline 1¥ semiconductor diode. y can convert the semiconductor resistor material from the initial first resistivity state to a different resistivity. State; then 'after applying an appropriate electrical pulse, it can be returned to the ~th resistivity state. For example, the first state may be higher than the second state: the resistivity state. Or the 'second state' may be lower than the state of the first resistivity centroid. A memory unit can have two or more data states and can be programmable or rewritable at one time. It is pointed out that the inclusion of a diode between the conductors in the memory unit allows the body to be formed in a highly dense cross-point memory array. In the preferred embodiment of the present invention, a polycrystalline and/or amorphous semiconductor memory device is then formed from the handleless diode and resistor y. 132477.doc 200908205 Figure 2 illustrates a memory cell 2 formed in accordance with a preferred embodiment of the present invention. The bottom conductor 12 is formed of a conductive material (e.g., tungsten) and extends in the first direction. A barrier and an adhesive layer can be included in the bottom conductor 12. The memory cell 2 contains a multi-turn semiconductor diode 4. The diode 4 preferably has a bottom: a heavily doped n-type region; an intrinsic region that has not been intentionally doped; and a top heavily doped germanium region, but the orientation of the diode can be reversed. Such a diode (regardless of its orientation) will be referred to as a p-i_n diode. The memory unit also contains one or more conductive "decoupler" layers 6, and amorphous and/or multi-turn semiconductor resistors 8. The order of the elements in unit 2 can be reversed, and resistor 8 can Located at the bottom of the cell and the diode 4 can be located at the top of the cell. Furthermore, the cell 2 can be arranged horizontally rather than vertically with respect to the substrate. The top conductor 16 can be in the same manner as the bottom conductor: 12 and be of the same material as the bottom conductor 12. Formed and extended in a second direction different from the first direction. The polycrystalline semiconductor diode 4 is vertically disposed between the bottom conductor 12 and the top conductor 16. The polycrystalline semiconductor diode 4 is preferably low resistivity The state is formed. Preferably, the device 8 is formed in a high resistivity state. The memory cell can be formed over a suitable substrate, for example, above a single crystal wafer. Figure 3 shows the formation in the intersection. Also pointing to a portion of the memory hierarchy of such a device in the array, wherein cell 2 is placed between bottom conductor 12 and top conductor 16. As shown in Figures 2 and 3, the diode and resistor preferably have a general body. The shape is cylindrical. Multiple The memory layer can be stacked on the substrate to form a highly dense monolithic three dimensional array. 〇 Preferably, the 6 memory unit 2 does not include any additional active devices, such as transistors or capacitors. However, if necessary, the memory unit 2 may contain 132477.doc -10- 200908205 optional passive devices, such as fuses, anti-melting materials. The memory unit may also contain a surrounding diode: a storage material or a phase material (as will be described below) and other optional layers. The insulation of the resistor is discussed herein, and the semiconducting nature region will be unintentionally doped. However, those skilled in the art should understand that the domain is described as It may include a low concentration of P-type or n-type dopants. The mass = diffusion to the temporary f~ J i # near region = to the local domain, or may be attributed to the π from the earlier deposition during deposition尜 尜 沉积 沉积 。 。 应 应 应 应 应 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质 本质, Shi Xi wrong alloy or some - other semi-conductive The material does not mean that this region does not contain any dopants, nor does it imply that such regions have better electrical neutrality. ^ W memory cells contain read/write memory cells, such as rewritable memory As will be explained in more detail below, the resistor 8 acts by switching from the first resistivity state to a second resistivity state different from the first resistivity in response to the applied bias voltage (i.e., pulse). Read/write components of the memory cell. 'In this discussion, the transition from a higher resistivity 'unstylized state to a lower resistivity, stylized state is called a set transition, which is subject to a set current, a set voltage, or The effect of the pulse is set; and the reverse transition from a lower resistivity, stylized state to a higher resistivity, unprogrammed state is referred to as a reset transition 'which is affected by the reset current, reset voltage, or reset pulse. The higher resistivity, unprogrammed state corresponds to the "1" memory state, while the lower resistivity, stylized state corresponds to the "0" memory state. 132477.doc 11 200908205 can be made by applying appropriate electrical pulses The resistivity of the @ n-doped polycrystalline or microcrystalline semiconductor material (eg, yttrium) varies between the enthalpy of the enthalpy. Typically, it is applied to the diode under forward bias. The set pulse that switches the self-suppressing resistivity state of the semiconductor material of the resistor to the lower thunderbolt low resistivity state will have the same semiconductor material white flash + basket material from the lower power p and the rate state The reset pulse switched to the higher resistivity state is lower than the reset pulse amplitude (voUage ampUtude) and will have a pulse width longer than the reset pulse. By selecting an appropriate voltage, it is possible to look at the broadcaster and J. Forming or resetting the semiconductor material of the resistor without switching the resistivity state of the diode. Preferably, the current flows through the diode in the forward direction, that is, applying a forward bias For setting the resistor 8 And resetting the switch. One or more conventional drive circuits connected to the electrodes 12, 16 can be used to apply an electrical pulse to the read/write switching resistor to the device 8 for programming and reading the memory unit 2. Thus, In use, the read/write switching resistor element 8 of the memory cell 2 switches from a first resistivity state to a second resistivity state different from the first resistivity state in response to the applied electrical pulse. The application of the second electrical pulse can switch the read/write switching resistor element 8 from the second resistivity state back to the first resistivity state and/or to the third resistivity state different from the first and second resistivity states. 'However, the diode guiding element 4 does not respond to the first applied electrical pulse from the first resistivity state (four) to the second resistivity state. For example, the 'diode guiding element 4 may not respond to Formed by a low resistivity state in which an electrical pulse is applied, and the resistor element 8 is formed in response to a high resistance state that is changed in response to the applied electrical pulse. Thousands 132477.doc 200908205 Memory will be described in more detail below Unit includes a metal-lithium layer having a C49 phase, such as a Shihuahua layer, a distorted titanium layer, or a Titanium-titanium telluride layer, which is in contact with the crystal layer template for the semiconductor diode 4 (d) Stallizati Qn ~ (d), which makes the diode in a low resistivity state. Without wishing to be bound by a particular theory, the low resistivity of the salt diode is due to the polycrystalline semiconductor material that is in contact with the crystal template by crystallization. Large grain size. The salt is in a low resistivity state, and the polar body (such as 'contact with the lithographic template by crystallization" will not switch in response to applying a forward bias on the diode. In the highest resistivity state, in contrast, resistor 8 is preferably formed without contact with the telluride template and is not shaped & relatively in a relatively high resistivity state. Therefore, the resistor 8 can be switched to a lower resistivity state by applying a forward bias to one of the poles and the resistors in series. U.S. Patent Application Serial No. 1 1/148,530, to Herner et al., June 1986, ’’Nonvolatile Memory Cell 〇perating by

Increasing Order in Polycrystalline Semiconductor Material&quot; and Herder's U.S. Patent Application Serial No. 10/954,510 &quot;Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide&quot; All of them, and both are incorporated herein by reference) describe that the crystallization of polycrystalline germanium adjacent to a suitable telluride affects the properties of the polycrystalline spine. Certain metal halides, such as cobalt telluride and titanium telluride, have a lattice structure that is very close to the lattice structure of germanium. When the amorphous or microcrystalline granules are crystallized and contacted with one of these arsenic compounds, during the crystallization period 132477.doc 200908205, the crystal lattice of the Si Xi compound provides a template for the cerium, and the defects are relatively small. Sa7 will be highly ordered when the 匕 匕 σ σ 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 It is called 'Reading the smelting, # + 菔夂 菔夂 菔夂 菔夂 后 二 二 二 = = = = = = = = = = = = ^ 实施 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The resistivity state of the material, which is detected by the memory unit when it is applied to read the voltage (between the top conductor 16 and the bottom conductor 12) (at the top J ^ core) It is distinguished by the electric &quot;IL. Preferably, there is at least a difference of at least two times between the read current flowing in any unique data state and the read current flowing in any different unique data state. Ground test the difference between these states. In the lower electric (four) resistor settings In the state, the read current through the memory cell is higher than that in the higher resistivity resistor + the dry charge I. In the state, the memory is read by the memory cell: the memory cell can be used once. Stylized unit or rewritable memory unit' and may have two, two, four his m Λ ▲ 0, u a 1u four or more unique data states. The unit may be in its order in any order. Any of the states are transitioned to any of their data states. Examples of writing, reading, and erasing memory cells are provided in U.S. Application Serial No. 11/496,986, filed on Jul. 31, 2006. It is a part of the continuation application of US Application No. 1 1/237,167, filed on September 28, 2005, and all of the applications in US Application No. 11/693,845, filed on March 30, 2007 The full text of the case 132477.doc -14 - 200908205 is hereby incorporated by reference. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI>

Switching the memory cells between the two (four) (four) states Γ = 上 上 上 These settings and reset steps can be repeated processes. If it is: the difference between the currents in the neighboring state (four) state is better than at least "selling multiples' in many embodiments 'best for 3 times, 5 times, 1 〇 larger multiples The current range is established for each data state to be distinguished. However, in some cases, the fact may be: after applying an electrical pulse, the read current is not within the desired range; that is, the resistivity of the semiconductor material of the resistor is higher or lower than the intended resistivity. status. After applying an electrical pulse to cut the memory cell to the desired state of the data slice, it is advisable to take the memory unit to determine if the desired data is obtained (4). If (4) is to the desired data state, an additional pulse is applied. The or additional pulses may have an amplitude (voltage or current) that is higher or lower than the original pulse or a pulse width that is longer or shorter than the original pulse. After the additional set pulse, the unit is read again and then the set or reset pulse is applied as appropriate until the read current is within the desired range. In a two-terminal device (such as a memory unit including a diode and a resistor), it is helpful if it can be read to verify the setting or reset, and if necessary, to make adjustments. An exemplary method of fabricating a δ-recallant early element will be described in detail for the fabrication of a single memory level. Stackable Additional Memory Levels&apos; These additional memory levels are each formed integrally above the memory level below it. In this embodiment, the polycrystalline and/or amorphous semiconductor 132477.doc • 15-200908205 bulk resistor will act as a switchable memory component and the diode 豸 will act as a component. Turning to Figure 4a, the formation of the memory begins with the substrate 1〇〇. The substrate 1 can be any semiconductor substrate known in the art, such as single crystal, 矽, 锗-锗 or 矽·锗·carbon ιν·ινκ, m_Vt, π·νιια a layer of insects on the substrate, or any other semi-conductive or non-semiconducting material. The substrate may include an integrated circuit fabricated therein. An insulating layer 102 is formed on the substrate 100. The insulating layer 102 may be yttrium oxide, nitrided @'face dielectric film, Si-C-O-H film' or any other suitable material. '' A first conductor 2 is formed on the substrate and the insulator (i.e., the lower electrode 12 is shown in Fig. 2). The adhesive layer 104 may be included between the insulating layer 1〇2 and the conductive layer 1〇6 to help the conductive layer 1〇6 adhere to the insulating layer 1〇2. If the overlying conductive layer is tungsten, titanium nitride is preferably used as the adhesive layer 1〇4. The next layer to be deposited is the conductive layer 1〇6. Conductive layer 1 6 may comprise any electrically conductive material known in the art, such as a crane or other material including buttons, titanium, copper, melamine or alloys thereof. Once all of the layers that will form the conductor rails have been deposited, any suitable masking and closing process is used to pattern and (4) the layers to form substantially: row, substantially coplanar conductors (in Figure 4a). Shown in cross section). In an embodiment, the photoresist is deposited, the photoresist is patterned by photolithography and (4) the layers, and then the photoresist is removed using standard process techniques. The conductor 200 can alternatively be formed by a damascene process. Next, a dielectric 132477.doc -16 - 200908205 (four) 08 is deposited on the conductor rail 200 and between the conductor rails 2〇〇. Dielectric material 108 can be any known electrically insulating material such as oxidized oxide, nitrite or nitrous oxide. In the preferred embodiment, ruthenium dioxide is used as the dielectric material 1 〇 8. = After removing the excess dielectric material just above the conductor strip 200, thereby exposing the top of the conductor rail 200 separated by the dielectric material 108, and • snagging the substantially flat surface (10). The resulting structure is shown in the figure. Such removal of the dielectric overfill to form a flat surface 1〇9 can be performed by any process known in the art wipes, such as chemical mechanical planarization (CMP) or (d), which can be advantageously used. Described in the US application No. ι〇/883, 4ΐ7 &quot;Nonselective Unpatterned Etchback to Expose Buried, by Ragh Uram et al.

Patterned Features,, and the application is incorporated herein by reference. At this stage, a plurality of substantially parallel first conductors have been formed at a first level above the substrate 100. Next, turn to Figure 4b, forming a vertical (J-pillar) on the finished conductor rail 2〇〇 (to save space, the substrate _ is not shown in Figure 4b; it will be assumed), in the conductor rail After the planarization, the barrier layer is deposited as a first layer. Any suitable material may be used in the barrier layer, including titanium oxynitride or a combination of such materials. In the preferred embodiment, 'nitridation is used. Titanium is used as the barrier layer. In the case where the barrier layer is nitrided, the barrier layer can be deposited in the same manner as the adhesive layer described earlier. Next, a semiconductor material to be patterned into a pillar is deposited. The semiconductor material can be a stone.夕, 锗, 锗夕锗 alloy or other suitable semiconductor or semiconductor. 132477.doc 200908205 gold. For the sake of simplicity, this description will refer to semiconductor materials as 矽, but it should be understood that 'skilled practitioners may alternatively choose this Any of the other suitable materials. Preferably, the semiconductor material is deposited in a relatively high resistivity amorphous or polycrystalline (including microcrystalline) state.

In a preferred embodiment, the post comprises a semiconductor junction diode. The term junction diode is used herein to refer to a non-ohmic conductive property having two terminal electrodes, and is made at the -electrode-type semiconducting material and at the other electrode by an n-type semiconducting material. a semiconductor device. Examples include: a p-type semiconductor material having a contact and (iv) a ρ_η diode of a semiconductor material and a "diode (such as a Zener diode); and a diode "in a pin diode, An intrinsic (undopped) semiconductor material is interposed between the P-type semiconductor material and the n-type semiconductor material. The bottom heavily doped region 112 can be formed by any deposition and doping methods known in the art. The germanium is deposited and then doped, but it is preferred to dope the germanium in situ by depositing a donor gas that supplies n-type dopant atoms (eg, phosphorus) during deposition. The region ι 2 is preferably between about 10 uni thick and about 80 nm thick. The intrinsic layer 114 can be formed by any method known in the art. The layer 114 can be #, 锗, or any of ♦ or erroneous An alloy having a thickness of between about 110 nm and about 330 nm, preferably about 2 〇〇 η π. Referring to Figure 4b, the just deposited semiconductor layer 114 and ι 2 can be patterned along with the underlying barrier layer 110. And the money is engraved to form the pillar 3〇〇. The pillar 300 should be The same distance and approximately the same width as the lower conductor 2GGA, so that each pillar 300 is formed on the conductor 2〇〇. The misalignment of 132477.doc -18· 200908205 can be tolerated. Detailed description may also delay post 300 patterning and etching 'up to additional steps in the device fabrication process. Columns 30 may be formed using any suitable masking and etching process. For example, standard photolithography techniques may be used. Depositing, patterning, and etching the photoresist, and then removing the photoresist. Alternatively, a hard mask of some other material (eg, hafnium oxide) may be formed over the stack of semiconductor layers (with anti-reflection on the bottom) Coating (BARC), followed by patterning and etching the hard mask. Similarly, a dielectric anti-reflective coating (DARC) can be used as a hard mask. Chen's US application for application on May 5, 2003 Case No. 1/728, 436 &quot;Photomask Features with Interior Nonprinting Window

Using Alternating Phase Shifting" or Chen's US Application No. ίο/g 153 12 &quot;Photomask Features with Chromeless Nonprinting Phase Shifting Window" (both of which are the assignee of this Act) The photolithography technique described in and incorporated herein by reference may be advantageously utilized to perform any photolithography step used in the formation of an array of simons in accordance with embodiments of the present invention. The distance and width between the columns 300 can be changed as necessary. In a preferred embodiment, the spacing between the columns (distance from the center of a column to the center of the next column) is about 300 nm, and the width of the column varies between about 1 〇〇 nm and about 15 〇 nm. In another preferred embodiment, the spacing between the columns is about 260 nm' and the width of the columns varies between about 90 nm and 130 nm. In general, the post preferably has a generally cylindrical shape with a circular or substantially circular cross-section of 132477.doc -19·200908205 having a direct control of 250 nm or less. The "component" has a substantially circular cross-sectional area L which is the total length for all lengths of the long dimension of 5.5% long (through the cross-section == obtained) = 彡The cross section of the edge. The straight edge (4) will not be &quot;straight&quot; on the molecular level '^ and may have minor irregularities; related to this = the degree of rounding' ^ U.S. Patent No. 6,952,030.

A dielectric material 108 is deposited on the semiconductor pillar 300 and between the semiconductor pillars to fill the gap between the semiconductor pillars 3 (9). Dielectric material 108 can be any known electrically insulating material such as oxygen cut, nitride nitride or oxynitride. In the preferred embodiment t, dioxotomy is used as the insulating material. The dielectric material over the pillars 300 is then removed to expose the top of the pillars 3 separated by the dielectric material 108, leaving a substantially flat surface. Such removal of the dielectric overfill can be performed by any process known in the art, such as CMp or etch back. The insulating layer 8 is planarized such that it surrounds the semiconductor region of the pillar 300. Ion implantation is performed after CMp or etch back to form a heavily doped p-type top region 116. The p-type dopant is preferably boron or BF&gt;2. This implantation step completes the formation of the diode 1 i j as shown in Figure 4b (the same diode is numbered 4 in Figure 2). Alternatively, region 116 may be deposited as a layer on layer 114 prior to the column patterning step rather than being implanted into layer 114. The resulting structure shown in Figure 4b is also shown schematically in Figure 5a. Figures 5b to 5d illustrate other arrangements of the diode structure. In Fig. 5a and Fig. 34477.doc • 20-200908205 diode, the bottom region is heavily doped n-type 矽), and the top region 116 is Ρ+. In the diode of Figures 5c and 5d, the bottom region (1) is and the top region H6 is N+. In Fig. 5a and Fig. 5c, the middle region ι4 is Ν·, and in Figs. 5b and 5d, the intermediate region 114 is p_. The intermediate region may be intentionally slightly doped 'or it may be essential or unintentionally doped. Uninterrupted areas will never be fully electrically neutral and will always have defects or contaminants&apos; which behave as if they were slightly n-doped or p-doped. Such a diode can be considered to be a p_i_n diode. Therefore, it can be described as the body, P+/P-/N+, N+/N-/P+4N+/P_/p+ diodes. Turning to Figure 4c', an optional insulating oxide, nitride or oxynitride layer 118 can then be formed over the heavily doped region &quot;6. As will be described below, layer 118 will be reduced during the formation of titanium layer 124 (but typically not other metal fragment layers). Alternatively, layer 118 can be omitted. For example, by oxidizing the top of the heavily doped region i 16 at about 600 C to about 850 C for about 2 seconds to about two minutes to form a between about 1 nm and about 5 nm. Cerium oxide 'to grow the optional cerium oxide layer&quot;8. Preferably, the oxide layer &quot;8 is also formed by exposing the wafer to about _degrees of about one minute in a 3 oxygen atmosphere. Layer 118 can alternatively be deposited. Next, a layer 12 of metal forming the ceramsite is deposited. For this purpose, the formation of the best metal of the object includes Qin or recorded. This example will describe the use of titanium for layer 120, although it should be understood that other materials may be used. Titanium layer 120 is deposited to any suitable thickness, e.g., between about 1 nm and about 20 nm, preferably between about i 〇 nm and about 15 Å, and most preferably about 1 〇 nm. In order to prevent oxidation of the titanium layer 12, a titanium nitride layer 122 (preferably about 30 nm thick) is deposited 132477.doc • 21 - 200908205. Layers 12 and 122 can be deposited by any conventional method (e.g., by sputtering).

(for example) in nitrogen at about 6 〇〇 it is about 8 〇〇. Annealing is performed between turns for about 10 seconds to about two minutes, preferably between about 65 degrees and about 75 degrees, and most preferably about 670 degrees for about 20 seconds. Annealing is used to restore oxide layer 118 and to cause titanium layer 12 to react with heavily doped region 116, wherein annealing causes titanium layer 120 to overlap with heavily doped region 116 to form titanium telluride. The oxide layer 118 is substantially completely reduced between the titanium layer 120 and the germanium of the heavily doped region 116. If the oxide layer 沉积 8 is deposited instead of the grown oxide layer U8, the remainder of the oxide layer 118 (over the top of the semiconductor pillar 3 ’ over the dielectric filler 丨 08) will remain. As in the self-aligned salicide process of S, the titanium nitride layer 122 and the unreacted titanium may be stripped in the selective wet etching, thereby leaving each formed in the junction diode. The titanium telluride layer 124 (shown in the figure) in the disc-shaped region at the top. Thereafter, a plurality of decoupler conductive layers 6 (shown in Figure 2) are deposited on the telluride layer 124, such as a new titanium nitride layer. "The unreacted titanium layer 120 portion and the titanium nitride capping layer 122' are not removed after the formation of the Sihuahua (four) 124, but are left in the device to act as the decoupler conductive layer 6. In the preferred real (d), the 'in the annealing' is formed by the titanium feature 124 package 3 C49 phase dreaming titanium. Right for the large or small size of the feature to maintain the annealing temperature at 700 ° C, or if the annealing The temperature is maintained at a degree [above but the feature size is 0.25 μm or less. For an annealing temperature of 700 ° C or higher, 'the C49 phase is obtained. The diameter of the diode is preferably 132477.doc • 22· 200908205 0.25 microns or less to form a C49 phase of titanium telluride. Since the lattice of this phase matches the amorphous germanium during the crystallization process, this phase is desirable. In contrast, larger features (greater than 0.25 microns) Size) will allow titanium telluride to terminate in C54 phase during the subsequent annealing above 700 ° C. Even if the C54 phase provides low resistivity (this is highly desirable for integrated circuit manufacturers), the C54 phase will not The same good lattice matching is provided during the crystallization process of amorphous germanium or polycrystalline germanium. Therefore, C49 phase titanium telluride allows maximum enhancement of grain growth by acting as a crystal template for the semiconductor material for the diode and thus Low dipole Electrical resistivity. As indicated, in this example, it is assumed that titanium is used in the layer 120 of the metal forming the telluride, but other materials including cobalt may alternatively be used. Thus, the titanium telluride layer 14 may alternatively be some sort Other tellurides, such as ruthenium. In a preferred embodiment, the junctional diode is as amorphous as deposited, and is crystallized to form a large grain, low resistivity polysilicon that is in contact with the vaporized layer 124. Crystallization may occur during the formation of the telluride 124 and/or during a separate crystallization anneal after completion of the memory cell. Depending on the desired degree of crystallization, it may be above about 600 〇C (such as 650. (3 to 85). A separate crystallizing anneal at a temperature of (:) lasts for a few minutes or longer (such as 2 minutes to 24 mils). Lower temperatures can be used for tantalum and niobium diode materials. Telluride layer 124 is used for lowering The impedance of the surface diode is advantageous, but may not be required in a completed device. In an alternative embodiment, the vaporization layer may be removed after the formation of the vaporization layer on the junction diode. The or such After the electrical decoupler layer 12〇, 122 and/or 124, 132477.doc -23- 200908205 is patterned/patterned into the semiconductor material of the resistor 8. Will: the thickness of the case: the semiconductor material of the resistor 8 It can be from _nm to about 4. Column °, about 20 (10) thick. The semiconductor material can be 矽, 锗, 矽 or other suitable semiconductor or semiconductor alloy. For the sake of simplicity, the semiconductor material will be called (4), but it should be understood Those skilled in the art may alternatively select such other suitable materials to be; tB #4· - A 。. Preferably Ο half = Γ resistive amorphous or polycrystalline (including microcrystalline) state Come to sink = conductor material. Preferably, the semiconductor material is deposited during crystallization annealing such as nitriding, 'connecting to the crystallization template material 124: l is broadly crystallized to a lower resistivity than the resistor 8, and the resistor 8 is larger than the LB material. Γ 'Resistance^ is not in contact with the crystalline template material 124. The material of the device 8 is preferably (but not necessarily) an intrinsic (unexcited) semiconductor 4 or a lightly doped semiconductor material (having a χΐ〇17(10), a ^-type dopant concentration) 4 resistor material is lightly ρ Any deposition and erbium known by the art are used. It is possible to deposit Shi Xiwan to form a resistance device to provide a Ρ-type or η-type dopant material:: It is better to pick up the pebbles at the scene during the accumulation of dreams. Atoms (examples of donor gas flow = map = = 6 and / or 8 layers of resistors to form column 3. The above graph is slaughtered into columns - I, described above for the diode 4 first micro two =:: the lower part of the light micro-step separation in the alternative embodiment, can be patterned in the same light lithography and sweet 132477.doc -24- 200908205 engraving step Depleteer 6 and resistor 8 layers are used to form pillars 300 in a patterning step. In this embodiment, 'delay pillar 3 lithography and etching steps are performed until a layer of resistors 8 is deposited. The formation and planarization of the dielectric material 108 is performed after 3 turns. If necessary, the deuteration step and/or the diode crystal annealing step for forming the lithofide 124 may be delayed until the portion including the resistor 8 is patterned. The entire column is 3 Å. In this case, the nitride layer 122 acts as a capping layer for forming the fragment layer 124 and acts as a decoupler layer 6 between the diode 4 and the resistor 8. 6 illustrates the δ-resonant unit of Yuancheng. The top conductor 4〇〇 (that is, the one shown in Figure 2) The portion electrode 16) can be formed in the same manner as the bottom conductor 2, for example, by depositing an adhesive layer 42 (preferably titanium nitride) and a conductive layer 422 (preferably tungsten) to form the top conductor. 400. The conductive layer 422 and the adhesion layer 420 are then patterned and etched using any suitable masking and etching technique to form a substantially parallel, substantially coplanar, perpendicular to the conductor 2: conductor 400 (shown in the figure) 6). In a preferred embodiment, the deposited light is patterned by photolithography and etching the layers, and then the green is removed using standard process techniques. If necessary, the adhesive layer can be attached to the pillars. 300 is patterned and may be located only on the post 3〇〇, and the conductive layer 422 3 contacts the strip of each of the adhesive layers on each of the posts 3. Next, on the conductor rail 4〇〇 A dielectric material is deposited between the conductor rails 4: (not shown). The dielectric material can be any known electrically insulating material, such as cerium nitride or oxynitride. In a preferred embodiment , using two emulsified enamel as the dielectric material. The formation of a body level. Additional memory layers 132477.doc • 25- 200908205 may be formed at this first memory level to form an integrated three-dimensional memory array. In some embodiments, at the memory level The common conductor. That is, the top conductor paste will serve as the bottom conductor of the next memory level: In other embodiments, an interlayer dielectric (not shown) is formed in Figure 6 - the memory level is flattened The surface of the interlayer dielectric, and the second memory level begins to be formed on the planarized interlayer dielectric without a common conductor.

The monolithic three dimensional memory array is one in which a plurality of memory levels are formed over a single substrate (such as a wafer) without an intervening substrate. The layers that form a memory layer are deposited or grown directly on one or more existing levels. In contrast, stacked memory is constructed by forming memory layers on separate substrates and bonding the layers of memory to each other, as described in US Patent No. 5,915,167 to Leedy. As disclosed in "Three dimensional structure memory", although the substrates may be thinned or removed from the memory layer prior to bonding, since the memory layers are initially formed on a separate substrate, such The memory is not a true monolithic three-dimensional memory array. The monolithic three-dimensional memory array is described in the following document: "Vertically stacked field programmable nonvolatile memory and method of fabrication" by J. hns〇n et al. "Vertically stacked field programmable nonvolatile memory and method of fabrication" by Johnson, U.S. Patent No. 6,420,215 &quot;Three Dimensional Memory Array and Method of 132477.doc -26- 200908205

Fabrication&quot;; US Application No. 10/095,962 &quot;Silicide-Silicon Oxide-Semiconductor Antifuse Device and Method of Making&quot;; June 27, 2002, applied for Vyvoda et al. U.S. Patent Application Serial No. 10/185,507 &quot;Electrically Isolated Pillars in Active Devices&quot;; U.S. Patent Application Serial No. l/44, No. 882, filed on May 19, 2003.

Rail Schottky Device and Method of Making&quot;; and Cleeves et al., US Patent Application Serial No. 10/728,451 &quot;Optimization of Critical Dimensions and Pitch of Patterned Features in and Above a Substrate&quot; These applications have been assigned to the assignee of the present invention and are incorporated herein by reference. One embodiment of the present invention has been described herein in the context of a monolithic three dimensional memory array formed on a substrate. The array includes at least one first memory level formed at a first height above the cover substrate and a second memory level formed at a second height different from the first height. In such a multi-layer array, three, four, eight or more memory levels can be formed over the lid substrate. Each memory level is formed integrally at the memory level below it. The memory cells formed in the monolithic three-dimensional memory array have stacked memory layers, but the cells can obviously also be formed in a two-dimensional array. An example of niobium is shown in which a vapor layer is formed on the junction diode, but those skilled in the art will appreciate that the vapor layer can be formed elsewhere: for example, beside or below the junction diode. Imagine many configurations. 132477.doc • 27· 200908205 In an alternative embodiment, a resistor 8 is formed below the diode 4 in the column 3〇〇. In this embodiment, the resistor 8 is formed on the lower portion (four). A depletion conductive layer 6 is formed on the resistor 4. The diode 4 is then formed on the depletion layer 1 . The telluride crystal template layer 124 can be formed in contact with a diode above or below the diode 4. An alternative method for forming a similar array (in which a mosaic is used and the shape is π. a conductor) is described in US Patent Application No. i 1/444,936 to Radigan et al., issued May 31, 2006, c〇nductive along “t〇 p

Patterned Features During Trench Etch, "This application has been assigned to the assignee of the present application and is incorporated herein by reference. The method of Radigan et al. is used instead to form an array according to the present invention. The detailed description describes only a few of the many forms that can be used in the present invention. Therefore, the detailed description is intended to be illustrative and not to be construed as a limitation. The entire disclosures of all patents, patent applications, and publications herein are hereby incorporated by reference in their entirety in the the the the the the the the the the the the the Figure 2 and Figure 6 are perspective views of a memory cell formed in accordance with a preferred embodiment of the present invention. Figure 3 is a perspective view of a portion of a memory hierarchy including the memory cell of Figure 2. Figures 4a through 4d illustrate the lateral cross-section of the formation of the memory 132477.doc • 28-200908205 layer formed in accordance with an embodiment of the present invention. Figures 5a to 5d are schematic side cross-sectional views illustrating an alternative embodiment of the present invention. ''1, [Major component symbol description] 2 Memory cell 4 Polycrystalline semiconductor diode, diode Body guiding element 6 conductive &quot;decoupler&quot; layer 8 amorphous and/or polycrystalline channel conductor resistance, read/write switching resistor element 12 bottom conductor, lower electrode 16 top conductor, upper electrode 100 substrate 102 Insulation layer 104 adhesion layer 106 conductive layer 108 dielectric material, insulating layer 109 flat surface 110 barrier layer 111 diode 112 bottom heavily doped region, semiconductor layer 114 essential layer, semiconductor layer, intermediate region 116 heavily doped p Type top region 118 layer, dioxide layer, oxide layer 120 to form a layer of metallization, titanium layer, conductive decoupling 132477.doc, 29-200908205 layer 122 It titanium layer, titanium nitride The cover layer, the conductive handle layer 124, the chopping layer, the crystallization feature, the crystal template material, the conductive decoupler layer, the vaporized crystal template layer 200, the first conductor, the conductor rail, the bottom conductor 300 Columns 400 Top Conductor, Conductor Rails 420 Adhesive Layer 422 Conductive Layer A Word Line B Bit Line S Selected Unit U1 Unselected Unit U2 Unselected Unit U3 Unselected Unit 132477.doc -30-

Claims (1)

200908205 ι· 2. 3. •, Patent Application Scope · A non-volatile memory device comprising: a semiconductor diode guiding element; and a semiconductor read/write switching element. Reading at least one conductive layer between the lead-in element and the 1 V ballast. The device of claim 2, where is the layer. The conductive layer comprises - titanium nitride. 4. The device of claim 2, wherein the guiding element and the collision/write switching element are arranged in series and share a body unit. And, at least the conductive layer comprises a non-volatile memory. 6. 6. One of the memory cells of the device of claim 4, for example, the device of the fifth item. And further comprising electrically contacting the non-volatile electrode and a second electrode. And wherein the read/write switching element comprises a resistor, such as the apparatus of claim 6, wherein: the read/write switching element comprises an amorphous Group IV semiconductor resistor, poly. a family of semiconductor resistors or a combination of amorphous and polycrystalline semiconductor resistors; the guiding element comprises a crystalline polycrystalline Group IV semiconductor diode; and the at least one electrically conductive layer is in contact with the guiding element Read/write switching elements. 8. The device of claim 7, wherein a layer of crystallized crystal template contacts the guiding member. The apparatus of claim 5, wherein the read/write cut is disposed in the first column of the first ray ... and the guide element 10 - in the column of the twist of the request item 5. The device of item 5, wherein the memory unit member is switched from a first electrical state i to a different one in response to an applied electrical pulse in response to a write electrical ma ϋ κ electrocardiographic pulse First rate status. The second resistance of the phantom and sheep state 11 ==1° of the skirt' where the guiding element does not respond to the applied K.J state. 4, switching from the first resistivity state to the second resistivity state 1 2, as in the device of claim U, 苴, 俗兮私' 1 wherein the guiding element is configured as - no response, two applied The electrical pulse changes the low resistivity state, and the read/write: component is configured to change to the resistivity state in response to the applied electrical pulse. ^, the device of item 12, wherein the __second electrical pulse is applied to switch the far-read/write switching element from the second resistivity state to the first-resistivity state. 14. A non-volatile a memory device comprising: a semiconductor diode guiding element; a semiconductor resistor read/write switching element; a conductive layer between the guiding element and the read/write switching element; - electrically contacting the guiding a first electrode of the lead element; and a second electrode electrically contacting the read/write switching element; wherein the read/write switching element, the at least one conductive layer, and the guiding element 132477.doc 200908205 are arranged in series a column between an electrode and the second electrode. 15. The device of claim 14, wherein: the device comprises an integral two-dimensional non-volatile memory device; the read/write switching element comprises an amorphous 1 ¥ a family semiconductor resistor, a polycrystalline Group IV semiconductor resistor or a combination of amorphous and polycrystalline semiconductor resistors, and the guiding element comprises a crystalline polycrystalline Group IV semiconductor diode; η the at least conductive layer In contact with the guide And the read/write switching element; and 'a germanide crystal template layer is in contact with the guiding element. 16. A non-volatile memory device comprising: a semiconductor diode guiding element; a semiconductor read/ Writing a switching element; a layer between the guiding element and the read/write switching element; and a power-storing member for switching the read/write state to a different from the first-resistance "The second resistivity of the first resistivity state is ~, the read/write switching element is from the first resistivity state. The 胄 丰 状态 state is switched to the device of claim 16, wherein the electrical pulse is derived from 嗲篦 φ ', in response to the applied state. The first resistivity state is switched to the second resistive response, 8. The device of claim 17... the W is - not 132477.doc 200908205 =: the applied electrical pulse changes one of the low resistivity shapes! Electricity:: Constructed as - in response to the applied state of the &lt;back resistivity state. Laughter 19 = device of claim 16, wherein the means for switching includes a driver. The driving circuit is configured to apply an electrical pulse to the read/write switching element 20== the expiration of the item 16, wherein the read/write switching element comprises a method of resistance, which comprises: The non-volatile memory device forms a semiconductor diode guiding element to form a semiconductor read/write switching element. 22. The method of claim 21 and the read/write switching element 23. The method layer of claim 22. And further comprising forming at least one electrically conductive layer between the guiding elements. And wherein the at least one conductive layer comprises a titanium nitride 24. The method of claim 22, and the read/write switching element memory unit. The guiding element, the at least one conductive layer are arranged in series and together comprise a non-volatile memory. The method of claim 24, further comprising forming a first electrode and a second electrode to make the first electrode And the second electrode is in electrical contact with the non-volatile memory unit. 26. The method of claim 25, wherein the read/write switching element comprises a resistor. 27. The method of claim 26, wherein: 132477.doc 200908205 The read/write switching element comprises an amorphous semiconductor resistor, a polycrystalline iv semiconductor resistor, or an amorphous and polycrystalline compound: 3S*^, the guiding element comprises a crystalline polycrystalline Group 1V semiconductor diode. The at least-conductive layer is in contact with the guiding element and the read/write switching element. 28. The method of claim 27, further comprising crystallizing the guiding element configured to contact the lithographic crystal template layer, the read/write switching element not contacting a lithographic template, such that After the crystallization step, the guiding element has a lower resistivity than the read/write switching element. 29. The method of claim 28, further comprising: patterning the read/write switching element, the at least-conducting layer, and the guiding element into a vertical pillar, wherein the vertical pillar is located at the first electrode and the first Between the two electrodes. The method of claim 25, wherein the read/write switching device of the memory unit switches from the _threshold state to the - in response to the applied electrical pulse. The first rate state of a resistivity state. The method of claim 3, wherein the guiding element is not switched from the first resistivity state to the second resistivity state in response to the applied, electrical pulse. 32. The method of claim 31 wherein - the second electrical pulse is applied to switch the read/write switching element from the second resistivity state to the resistivity state. 33. A method of fabricating a non-volatile memory device comprising: 132477.doc 200908205 forming a semiconductor diode guiding element; /writing at least one conductive layer between the switching elements; An electrode; and/or a second electrode of the switching element; [noon, the at least one conductive layer and a pillar between the guiding element electrode and the second electrode. 34. The method of claim 33, wherein: The / write switching element comprises an amorphous semiconductor resistor, polycrystalline, semiconductor resistor or a combination of amorphous and polycrystalline semiconductor resistors and the guiding element comprises a crystalline polycrystalline Group IV semiconductor diode And the conductive layer is in contact with the guiding element and the read/write switching element; and a vaporized crystal template layer is in contact with the guiding element. 35. The method of claim 34, wherein the method comprises: Forming the first electrode on the substrate; forming the semiconductor diode guiding element on the first electrode; forming a first conductive layer of titanium or cobalt on the diode guiding element; on the titanium or cobalt layer Forming a titanium nitride second conductive layer; forming the resistor read/write switching element; switching the diode guiding element, the first and second conductive layers, and the 132477.doc 200908205 resistor read/write switch The component is patterned into a pillar Annealing the device to form a layer of titanium or cobalt telluride by reacting the first conductive layer with the diode guiding element; and the diode in contact with the layer of titanium or cobalt telluride The body guiding element crystallizes such that the diode guiding element has a lower resistivity than the resistor read/write switching element; and the second electrode is formed on the resistor read/write switching element. 36. A method of operating a non-volatile memory device, comprising: providing a non-volatile memory cell comprising a semiconductor diode guiding component, a semiconductor read/write switching component, and At least one conductive layer between the lead element and the δ meta-read/write switching element; first, switching the read/write switching element from a first resistivity state to a second resistor different from the first resistivity state Rate state; and first switching the read/write switching element from the second resistivity state to the first resistivity state. 37. The method of claim 36, wherein the first switching step and the second switching step comprise applying a first electrical pulse and a second electrical pulse to the guiding element and the read/write switching element, respectively. The method of moon member 37, wherein the guiding member switches from the first resistivity state to the first resistivity state in response to the first and second applied electrical pulses. 39. The method of claim 38, wherein: the guiding element is configured to be in a low resistivity state without changing back to the second applied electrical pulse; I32477.doc 200908205 The read/write switching element is configured as a high resistivity state that changes in response to the first and second applied electrical pulses; and the first and second electrical pulses comprise a mutual Forward biased electrical pulses of different amplitudes. The method of claim 36, wherein the read/write switching element comprises a resistor. / 132477.doc