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WO2008152719A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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Publication number
WO2008152719A1
WO2008152719A1 PCT/JP2007/061978 JP2007061978W WO2008152719A1 WO 2008152719 A1 WO2008152719 A1 WO 2008152719A1 JP 2007061978 W JP2007061978 W JP 2007061978W WO 2008152719 A1 WO2008152719 A1 WO 2008152719A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
ferroelectric
metal
semiconductor device
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/061978
Other languages
English (en)
French (fr)
Inventor
Wensheng Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Priority to PCT/JP2007/061978 priority Critical patent/WO2008152719A1/ja
Priority to CN2007800532641A priority patent/CN101681883B/zh
Priority to JP2009519112A priority patent/JP5093236B2/ja
Publication of WO2008152719A1 publication Critical patent/WO2008152719A1/ja
Priority to US12/630,337 priority patent/US8102022B2/en
Anticipated expiration legal-status Critical
Priority to US13/332,522 priority patent/US8513100B2/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/684—Capacitors having no potential barriers having dielectrics comprising perovskite structures the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/891—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D44/00, e.g. integration of charge-coupled devices [CCD] or charge injection devices [CID

Landscapes

  • Semiconductor Memories (AREA)

Abstract

　配向性の良好な強誘電体膜を備える強誘電体キャパシタを形成する。 　所定の結晶面を優先配向させた第１の金属膜上に、アモルファスまたは微結晶の金属酸化膜を形成し（ステップＳ１，Ｓ２）、その後、ＭＯＣＶＤ法による強誘電体膜の形成を行う（ステップＳ３）。この強誘電体膜の形成時には、第１の金属膜上の金属酸化膜が還元されて第２の金属膜となり、その第２の金属膜上に強誘電体膜が形成される。アモルファスまたは微結晶の金属酸化膜は、強誘電体膜の形成時に均一に還元されやすく、その還元によって配向性の良好な第２の金属膜が得られ、第２の金属膜上には、配向性の良好な強誘電体膜が形成されるようになる。強誘電体膜の形成後は、その上に上部電極を形成する（ステップＳ４）。
PCT/JP2007/061978 2007-06-14 2007-06-14 半導体装置の製造方法および半導体装置 Ceased WO2008152719A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/061978 WO2008152719A1 (ja) 2007-06-14 2007-06-14 半導体装置の製造方法および半導体装置
CN2007800532641A CN101681883B (zh) 2007-06-14 2007-06-14 半导体装置的制造方法以及半导体装置
JP2009519112A JP5093236B2 (ja) 2007-06-14 2007-06-14 半導体装置の製造方法および半導体装置
US12/630,337 US8102022B2 (en) 2007-06-14 2009-12-03 Semiconductor device manufacturing method and semiconductor device
US13/332,522 US8513100B2 (en) 2007-06-14 2011-12-21 Semiconductor device manufacturing method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/061978 WO2008152719A1 (ja) 2007-06-14 2007-06-14 半導体装置の製造方法および半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/630,337 Continuation US8102022B2 (en) 2007-06-14 2009-12-03 Semiconductor device manufacturing method and semiconductor device

Publications (1)

Publication Number Publication Date
WO2008152719A1 true WO2008152719A1 (ja) 2008-12-18

Family

ID=40129336

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/061978 Ceased WO2008152719A1 (ja) 2007-06-14 2007-06-14 半導体装置の製造方法および半導体装置

Country Status (4)

Country Link
US (2) US8102022B2 (ja)
JP (1) JP5093236B2 (ja)
CN (1) CN101681883B (ja)
WO (1) WO2008152719A1 (ja)

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* Cited by examiner, † Cited by third party
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JP2011096818A (ja) * 2009-10-29 2011-05-12 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法

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JP4845937B2 (ja) * 2008-07-24 2011-12-28 株式会社東芝 スピンｍｏｓｆｅｔおよびこのスピンｍｏｓｆｅｔを用いたリコンフィギュラブル論理回路
CN102956640A (zh) * 2011-08-22 2013-03-06 大中积体电路股份有限公司 双导通半导体组件及其制作方法
US8962350B2 (en) * 2013-02-11 2015-02-24 Texas Instruments Incorporated Multi-step deposition of ferroelectric dielectric material
US9305998B2 (en) * 2013-02-11 2016-04-05 Texas Instruments Incorporated Adhesion of ferroelectric material to underlying conductive capacitor plate
JP2015149354A (ja) 2014-02-05 2015-08-20 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9721248B2 (en) 2014-03-04 2017-08-01 Bank Of America Corporation ATM token cash withdrawal
US10460367B2 (en) 2016-04-29 2019-10-29 Bank Of America Corporation System for user authentication based on linking a randomly generated number to the user and a physical item
US10268635B2 (en) 2016-06-17 2019-04-23 Bank Of America Corporation System for data rotation through tokenization
US12094923B2 (en) * 2022-01-31 2024-09-17 Kepler Computing Inc. Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices

Citations (1)

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JP2002110935A (ja) * 2000-10-04 2002-04-12 Matsushita Electric Ind Co Ltd 薄膜キャパシタ及びその製造方法

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EP0478799B1 (en) * 1990-04-24 1996-12-04 Ramtron International Corporation Semiconductor device having ferroelectric material and method of producing the same
JP3159255B2 (ja) 1998-09-16 2001-04-23 日本電気株式会社 強誘電体容量で用いる電極のスパッタ成長方法
JP2000236075A (ja) * 1999-02-12 2000-08-29 Sony Corp 誘電体キャパシタの製造方法および半導体記憶装置の製造方法
US6548343B1 (en) * 1999-12-22 2003-04-15 Agilent Technologies Texas Instruments Incorporated Method of fabricating a ferroelectric memory cell
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JP2002151656A (ja) 2000-11-14 2002-05-24 Toshiba Corp 半導体装置及びその製造方法
US20020117700A1 (en) * 2001-02-28 2002-08-29 Glex Fox Amorphous iridium oxide barrier layer and electrodes in ferroelectric capacitors
JP2003068991A (ja) 2001-08-23 2003-03-07 Fujitsu Ltd 半導体装置及びその製造方法
US6500678B1 (en) * 2001-12-21 2002-12-31 Texas Instruments Incorporated Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing
US6596547B2 (en) * 2001-12-21 2003-07-22 Texas Instruments Incorporated Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing
US6686236B2 (en) * 2001-12-21 2004-02-03 Texas Instruments Incorporated Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing
US6528328B1 (en) * 2001-12-21 2003-03-04 Texas Instruments Incorporated Methods of preventing reduction of irox during PZT formation by metalorganic chemical vapor deposition or other processing
US6635497B2 (en) * 2001-12-21 2003-10-21 Texas Instruments Incorporated Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing
JP4657545B2 (ja) 2001-12-28 2011-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
US20030176073A1 (en) 2002-03-12 2003-09-18 Chentsau Ying Plasma etching of Ir and PZT using a hard mask and C12/N2/O2 and C12/CHF3/O2 chemistry
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Patent Citations (1)

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JP2002110935A (ja) * 2000-10-04 2002-04-12 Matsushita Electric Ind Co Ltd 薄膜キャパシタ及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011096818A (ja) * 2009-10-29 2011-05-12 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JPWO2008152719A1 (ja) 2010-08-26
US8513100B2 (en) 2013-08-20
JP5093236B2 (ja) 2012-12-12
US20100078762A1 (en) 2010-04-01
CN101681883A (zh) 2010-03-24
CN101681883B (zh) 2011-07-06
US8102022B2 (en) 2012-01-24
US20120094398A1 (en) 2012-04-19

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