[go: up one dir, main page]

WO2002059970A3 - Mos transistor - Google Patents

Mos transistor Download PDF

Info

Publication number
WO2002059970A3
WO2002059970A3 PCT/DE2002/000177 DE0200177W WO02059970A3 WO 2002059970 A3 WO2002059970 A3 WO 2002059970A3 DE 0200177 W DE0200177 W DE 0200177W WO 02059970 A3 WO02059970 A3 WO 02059970A3
Authority
WO
WIPO (PCT)
Prior art keywords
mos transistor
cmos transistor
individual transistors
high frequency
particularly suitable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2002/000177
Other languages
German (de)
French (fr)
Other versions
WO2002059970A2 (en
Inventor
Andreas Dollinger
Herbert Koblmiller
Michael Mark
Martin Streibl
Volker Schultheiss
Martin Wendel
Guenter Hofer
Guenter Krasser
Josef Prainsack
Walter Schuchter
Wolfgang Stadler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2002059970A2 publication Critical patent/WO2002059970A2/en
Anticipated expiration legal-status Critical
Publication of WO2002059970A3 publication Critical patent/WO2002059970A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

The invention relates to a CMOS transistor (T) comprising a plurality of individual transistors (T1 Tn) which are connected in a parallel manner. Said individual transistors (T1- Tn) are respectively supplied with an additional series resistor (R). The above-mentioned circuit offers a protection against electrostatic re-charging combined with good high frequency properties of a CMOS transistor and is particularly suitable for analog circuits.
PCT/DE2002/000177 2001-01-25 2002-01-21 Mos transistor Ceased WO2002059970A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10103297.8 2001-01-25
DE10103297A DE10103297A1 (en) 2001-01-25 2001-01-25 MOS transistor

Publications (2)

Publication Number Publication Date
WO2002059970A2 WO2002059970A2 (en) 2002-08-01
WO2002059970A3 true WO2002059970A3 (en) 2003-08-07

Family

ID=7671699

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/000177 Ceased WO2002059970A2 (en) 2001-01-25 2002-01-21 Mos transistor

Country Status (2)

Country Link
DE (1) DE10103297A1 (en)
WO (1) WO2002059970A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4170210B2 (en) * 2003-12-19 2008-10-22 Ｎｅｃエレクトロニクス株式会社 Semiconductor device
DE102005039365B4 (en) 2005-08-19 2022-02-10 Infineon Technologies Ag Gate-controlled fin resistive element operating as a pinch - resistor for use as an ESD protection element in an electrical circuit and a device for protecting against electrostatic discharges in an electrical circuit
US11120864B2 (en) * 2019-12-09 2021-09-14 International Business Machines Corporation Capacitive processing unit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149033A2 (en) * 1983-12-22 1985-07-24 Texas Instruments Deutschland Gmbh Field-effect transistor with insulated gate electrode
US5157573A (en) * 1989-05-12 1992-10-20 Western Digital Corporation ESD protection circuit with segmented buffer transistor
EP0691683A2 (en) * 1994-07-06 1996-01-10 Deutsche ITT Industries GmbH Protection structure for integrated circuits
US5854504A (en) * 1997-04-01 1998-12-29 Maxim Integrated Products, Inc. Process tolerant NMOS transistor for electrostatic discharge protection
US6043969A (en) * 1998-01-16 2000-03-28 Vantis Corporation Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors
US6096609A (en) * 1998-01-13 2000-08-01 Lg Semicon Co., Ltd. ESD protection circuit and method for fabricating same using a plurality of dummy gate electrodes as a salicide mask for a drain

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149033A2 (en) * 1983-12-22 1985-07-24 Texas Instruments Deutschland Gmbh Field-effect transistor with insulated gate electrode
US5157573A (en) * 1989-05-12 1992-10-20 Western Digital Corporation ESD protection circuit with segmented buffer transistor
EP0691683A2 (en) * 1994-07-06 1996-01-10 Deutsche ITT Industries GmbH Protection structure for integrated circuits
US5854504A (en) * 1997-04-01 1998-12-29 Maxim Integrated Products, Inc. Process tolerant NMOS transistor for electrostatic discharge protection
US6096609A (en) * 1998-01-13 2000-08-01 Lg Semicon Co., Ltd. ESD protection circuit and method for fabricating same using a plurality of dummy gate electrodes as a salicide mask for a drain
US6043969A (en) * 1998-01-16 2000-03-28 Vantis Corporation Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors

Also Published As

Publication number Publication date
WO2002059970A2 (en) 2002-08-01
DE10103297A1 (en) 2002-08-22

Similar Documents

Publication Publication Date Title
US6262873B1 (en) Method for providing ESD protection for an integrated circuit
EP0852400A3 (en) A bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits
US8212604B2 (en) T switch with high off state isolation
CA2376410A1 (en) Cascode distributed amplifier
TW344140B (en) Integrated CMOS circuit arrangement and method for the manufacture thereof
WO2004030036A3 (en) A modular bipolar-cmos-dmos analog integrated circuit and power transistor technology
US20120007654A1 (en) System and method of transistor switch biasing in a high power semiconductor switch
DE60130146D1 (en) ESD PROTECTION
US7423472B2 (en) Power switching circuit
AU2002365724A1 (en) Esd protection circuit for use in rf cmos ic design
HK1046471A1 (en) Method of fabrication dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
WO1999021175A3 (en) Integrated circuit layout methods and layout structures
TW200723489A (en) Electrostatic discharge protection apparatus for high-voltage products
ATE405990T1 (en) MOS SWITCHING NETWORK
WO2002059970A3 (en) Mos transistor
WO2002027795A3 (en) Fully synthesisable and highly area efficient very large scale integration (vlsi) electrostatic discharge (esd) protection circuit
KR970072681A (en) An electrostatic protection circuit in a circuit in which the substrate bias is separated
DE69523292D1 (en) Integrated semiconductor circuit consisting of bipolar transistors and MOS transistors and associated manufacturing process
TW200605348A (en) Electrostatic protection circuit
DE60009080D1 (en) INTEGRATED GYRATOR CIRCUIT
WO2006071555A3 (en) Esd protection structure for i/o pad subject to both positive and negative voltages
KR950015754A (en) Semiconductor devices including capacitors between pads and ground pads near reference signal pads
WO2001048920A3 (en) Phase-compensated impedance converter
AU2001237483A1 (en) Mos transistor for high density integration circuits
KR960032678A (en) Semiconductor device with CMOS circuit and method of manufacturing the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP