WO2002059970A2 - Mos transistor - Google Patents

Abstract

The invention relates to a CMOS transistor (T) comprising a plurality of individual transistors (T1 Tn) which are connected in a parallel manner. Said individual transistors (T1- Tn) are respectively supplied with an additional series resistor (R). The above-mentioned circuit offers a protection against electrostatic re-charging combined with good high frequency properties of a CMOS transistor and is particularly suitable for analog circuits.

Description

description

MOS transistor

The present invention relates to a MOS transistor.

There is a need to protect high-frequency analog CMOS semiconductor circuits from electrostatic discharge, ESD, electrostatic discharge. ESD pulses, which can reach peak voltages of several 1000 volts, destroy unprotected CMOS semiconductor circuits.

With electrostatic discharge, various error mechanisms can lead to destruction in the semiconductor. The main error mechanisms are:

1. The breakthrough of a source bulk or drain bulk

Diffusion area, which forms a diode, in

Reverse.

2. A breakdown between the source and drain of a transistor.

3. The destruction of the gate oxide of the transistor.

To avoid mechanisms 1 and 2 in the case of an electrostatic discharge, it is desirable to ensure a homogeneous distribution of the discharge current caused by the electrostatic discharge over the entire loaded component.

It is already known to achieve the homogeneous current distribution of the discharge current by reducing the conductivity of the diffusion regions in the field effect transistor. In the case of salicide (self-aligned silicide) processes, this can be done by increasing the distance from the contact holes to the gate on the drain and / or source side and by blocking the salicide on the drain and source diffusion and over the transistor gate. Such a technological intervention in the manufacturing process is called salicide blocking and requires an additional mask and exposure level in the manufacturing process. In semiconductor technologies without salted diffusion, it is sufficient to increase the distance between the contact holes and the gate on the drain and / or source side. The active transistors that have a direct connection to a connection pad must be improved in this way with regard to ESD.

The process engineering or layout engineering measures described during production essentially have two negative effects on the high-frequency properties of the circuit:

1. An enlarged diffusion area inevitably leads to an increased transistor capacity. Any additional capacitance of the active transistor, for example driver, input transistor, etc., and of the component protecting it, has disadvantageous effects on the high-frequency properties.

2. Due to the manufacturing process, the conductivity of the gate connection of the transistor is reduced by the salicide blocking, which leads to a deterioration in the high-frequency properties of the transistor to an extent which severely limits the possibility of using such a protected element in high-frequency circuits.

The object of the present invention is to provide a MOS transistor which is protected against electrostatic discharges and which is suitable for use in high-frequency technology, in particular in analog circuits.

The object is achieved with a MOS transistor

zeltransistΩrs the voltage on all other individual transistors to an extent that leads to a breakdown of further individual transistors. Overall, this mechanism leads to the fact that the discharge current of an ESD pulse is ultimately distributed homogeneously over all individual transistors.

The required resistance value of the series resistors can be easily determined from the parameters trigger voltage, holding voltage and intrinsic ESD strength of an individual transistor. These parameters can easily be determined by simulations in the early stages of development.

Compared to a one-piece transistor, a parallel connection of a large number of individual transistors has an equally good or better ESD resistance. With regard to the high-frequency properties, in particular the noise properties, a transistor divided into a large number of individual transistors which are connected in parallel is significantly improved.

Another advantage of dividing the protective structure with the series resistors and the partial transistors into many small transistor fingers or transistor elements connected in parallel is that the unused area parts occurring in all circuit layouts can be filled with the small transistor elements. In contrast to the conventional, previously known ESD protection, the individual partial transistors and the discrete series resistors can be distributed over larger areas of the circuit layout according to the present principle. The different metal supply line resistances in the parallel connection and the sub-transistors play a subordinate role here if the resistance value of the series resistor is correctly selected. In this case, however, the achievable area utilization must be weighed against the high-frequency suitability of the circuit layout in individual cases. JL tt P>

LΠ O LΠ o LΠ o LΠ

lic-BlΩcking be formed. Since salicide blocking requires its own mask and exposure level, which is typically in the region of 3% of the total wafer costs, the wafer costs can be significantly reduced in a manufacturing process in the wafer production.

Overall, the present principle makes it possible to adapt CMOS transistors and other CMOS components with regard to ESD properties and high-frequency properties practically independently of one another.

In a preferred embodiment of the present invention, all series resistors of the CMOS transistor have the same resistance value. This leads to a particularly homogeneous current distribution in the event of a fault.

In a further preferred embodiment of the invention, the series resistors are connected between the source connections of the controlled sections and the source connections of the CMOS transistor. Such a CMOS transistor has an ESD-protected source connection overall.

In an alternative, preferred embodiment of the present invention, the series resistors are connected between the drain connections of the controlled sections and the drain connection of the CMOS transistor. This forms a CMOS transistor with a protected drain connection.

In principle, source and drain connections can be interchanged and can only be determined by external wiring of a CMOS transistor.

In a further preferred embodiment of the invention, the CMOS transistor has a plurality of second sub-transistors, a first sub-transistor and a second sub-transistor each Part transistor with their controlled paths form a series connection. Such a transistor can also be referred to as a cascaded transistor. Overall, a first partial transistor with a second partial transistor and a series resistor can form a series circuit, a large number of such series circuits being connected in parallel with one another.

In a further preferred embodiment of the invention, the resistance value of the series resistors is in a range from 100 to 300 Ω. By connecting many individual transistors in parallel, a series-effective series resistor of the CMOS transistor of only a few ohms or less is formed. As a result, the favorable high-frequency properties of the CMOS transistor are retained.

In a further preferred embodiment of the present invention, the individual transistors, that is to say first and second individual transistors, have a gate width which is in a range between 0.4 and 10 μm. A width of the individual transistors or fingers <10 μm ensures a homogeneous current distribution across the width of the individual transistor. The lower limit of 0.4 μm is currently a lower limit for technological reasons and can of course also be smaller in future technologies with a higher integration density.

In a further preferred embodiment of the present invention, the individual transistors each have a gate connection which is formed using salicide technology. As a result, particularly good high-frequency properties are achieved.

In a further preferred embodiment of the present invention, the series resistors are made of poly-silicon

Technology formed. To achieve particularly good high-frequency properties, the series resistors can be made of polysilicon technology. nic or in polysilicon with salicide blocking. The production of the series resistors without salicide leads to an increase in the sheet resistance of the polysilicon by typically 1 to 2 orders of magnitude, which leads to a smaller area requirement of the resistor and thus to a smaller chip area requirement of the CMOS transistor. Depending on the manufacturing technology provided, the series resistors can also be implemented by LDD implantation, in n-doped tubs or with metal / via / contact chains.

In a further preferred embodiment of the present invention, the individual transistors each have a gate connection contacted on both sides. As a result, the maximum distance to a contact hole drops to 0.2 to 2.5 μm and the corresponding resistance of the gate electrode drops to a few ohms. This enables very high cut-off frequencies, very low noise of the gate electrode and, overall, very good high-frequency suitability.

In general, salicide is understood to be a self-aligned silicide.

Further details of the invention are the subject of the subclaims.

The invention is explained in more detail below using several exemplary embodiments with reference to the drawings. Show it:

FIG. 1 shows a first exemplary embodiment of a CMOS transistor according to the invention with a protected source connection,

FIG. 2 shows an exemplary embodiment of the present invention with a protected drain connection, FIG. 3 shows an exemplary embodiment of the invention with a protected drain connection of cascaded transistors,

Figure 4 shows an exemplary embodiment of a transistor according to Figure 1 or 2 in a simplified

Layout,

FIG. 5 shows an exemplary embodiment of a CMOS transistor according to FIG. 3 on the basis of a simplified layout and

Figure 6 is a diagram for comparing the ESD strength with respect to the component width according to the present principle with different parameters.

FIG. 1 shows in the right half of the figure the equivalent circuit diagram of a CMOS transistor T with a control connection 1 designed as a gate connection for controlling a controlled path. The controlled path of the transistor T is coupled to connection nodes K1, K2. The controlled path of the transistor T comprises a drain terminal D which is connected to the first circuit node Kl and a source terminal S which is connected to the second circuit node K2 via an equivalent resistor R / n for protection against electrostatic discharge. The circuit diagram described, shown on the right in FIG. 1, is an equivalent circuit diagram of the CMOS transistor T, which is shown in the left half of FIG. 1 divided into individual, first sub-transistors.

The transistor T comprises first sub-transistors Tl, T2 ... Tn, which are connected in parallel with one another. All drain connections of the first partial transistors Tl to Tn are directly connected to one another in the first circuit node Kl. A series resistor R with one connection is connected to each source connection of the first partial transistors Tl to Tn, the further connections of the series resistors R being directly connected to one another in a second circuit node K2 are connected. The control connections of the partial transistors Tl to Tn, that is to say their gate connections, are connected to one another in the gate connection of the transistor T, which is designated as the first control input 1 of the transistor T. Accordingly, the first sub-transistors Tl to Tn form a parallel connection. The transistor widths of the individual transistors Tl to Tn can be added to determine the transistor width of the transistor T. With a number of n first partial transistors Tl to Tn, a resistance value for the equivalent resistance R / n in the equivalent circuit diagram results from the quotient of the resistance value of a series resistor R and the number n of the first partial transistors Tl to Tn. Overall, a CMOS transistor T is formed with a source connection protected from ESD pulses.

The resistance value of the individual series resistors R is in a range from 100 to 200 Ω. By connecting the plurality of first partial transistors in parallel, the circuit-technical effect of the series resistor R is reduced to a few ohms, so that the favorable high-frequency properties of the CMOS transistor T are retained.

The individual sub-transistors have a small gate width of <10 μm. This results in a homogeneous current flow over the entire width of a single finger of the transistor. This ensures improved ESD resistance. The gate width of the individual transistors or partial transistors is limited at the bottom by the technology.

The number n of the first partial transistors Tl to Tn can be, for example, in a range between 10 and 100. For example, the number n of the first partial transistors can be 64, which can be achieved by connecting 4 groups of 16 individual transistors in parallel.

FIG. 2 shows a further exemplary embodiment of a CMOS transistor T, which is likewise provided by a large number of parallel

LO LO to t P ¹ P ¹ Π O LΠ o Π o LΠ

DJ tQ er rt Φ E

& d d Φ & O P- P- O o Ω HS P- cn Hf P tQ a

Ω tr Ω Φ Φ d * ^ ιi tr P H Hi P-

H Φ φ H P d P- d Ω. d N CO DJ tΛ P P Ω Λ d Ω rt

Φ rt Ω Hf tr N P-

Hf Φ tr tQ PJ φ O

Φ co Hi φ ω P ¹ P- P

DJ Ω <3 P- rt iQ Φ

P ¹ tr <Φ DJ: H- ¹ d rt P

P- J Φ Hf tΛ Qi P cn P ¹ Hf rt d tQ Φ i

P- rt rt PJ P P- Φ φ d DJ d P- IQ 3 P cn

Hf P d co ⁽ Q P- er tQ cn Ω d Φ rt 3 er

DJ Ω Hi P-Q: φ

Hj tQ tr & P • d tQ cn

Φ d PJ P> Φ PJ P ¹ Ω

P- 3 P Hf • CO Hf P- tr o DJ: tQ ^ DJ Ω Hf rt tΛ o> -3 P- ¹ tr P-

, <cn O Hf P ¹ Φ Φ

Tj O Ω d PJ φ cn er

P- P Hf PP ¹ Φ iQ Ωi Ω cn tQ o P d co DJ φ P- Φ Ω Φ

Hi 0 tΛ 1 cn ω tr P d rt Ω PJ to Hf 3 d Ω tr tϋ

Ω P- P Hi DJ rt Hf

3 Φ rt Ωi cn P ¹ d P-

P- 1 rt PP rt Φ α 3 Φ tQ N d P- Hi P- rt cn P- tQ PP PJ rt Φ H- ¹ d

Φ Ω. Φ P- PP ⁾ cn c H (P iQ - ^

Ω α 1 Φ 0 3 tr H {s cn Φ d 0: d: DJ & Ω Hi rt tQ rt P- Ω cn tr cn H- ¹

N P H! Ω d: rt N P- rt 1 tr rt Φ d Ω

Φ s & N P Hf tr

3 d d rt • cn P tΛ Φ H3 a ö Ω tQ 3 φ Φ

Hi tr o P-DJ

P ⁾ P ¹ tQ P-CO P ¹

P- d: Φ P O rt P-

P cn 3 i d Hf cn

1 cn DJ: J P- φ tΛ tr Ω P φ

P P- φ cn Hf tτ | φ 1 P- d

P- Hi co P .1 1 tQ

LO LO to to P> P ¹

LΠ O LΠ o Lπ o LΠ

cn P- cn CO α CO tQ ►3 tr cn Ω- < ^| Q rt ESI «Ωi • ^ Φ cn er H3 rt rt FV cn Ω φ 5 ü

P- p PJ ^■ 8 o PJ P- Φ Φ P ¹ Φ φ Φ φ Φ φ d Ω Φ P * P- rt P- HS HS & Φ P P- Φ DJ P- DJ Φ

Ω 3 Φ φ φ tr P P- Hi N 3 Hf • Hf P DJ ω cn DJ O co PO cn P rt P Hf Hf tr Ό rt PP ¹ P- Hf er t Λ er pσ CO Φ td er Φ P Ω P co Ω rt rt Φ Φ DJ

O cn NN Ω o P- rt Φ Ω P- co bd Φ α P- cn 3 tr cn rt tr ^ Φ Ω P- 1 PP ¹ Ω

Φ P ¹ rt 1 1 P- PJ ⁽ Q i ^" cn P- N tr ^| QO P- P- cn P> P ¹ P- PJ to P Hf ω g

P- ^. HJ • ^ rt ds: PJ rt d P ¹ Φ Hh o ta cn d cn rt d φ rt & tQ φ O

P d PJ P- ¹ 1 Φ rt β d <p- Φ Hf P ¹ ^ O tΛ rt P- tΛ d «P cn Φ O φ FV d P- H3 cn Φ P ¹ Hf φ ω rt P Ω d Φ d P ¹ d er: O cn FV er P ¹ Ω 3 1

HS rt tQ tQ φ tu cn Ω HS Ω Φ φ P 3 CO cn Hf Φ er φ HS Ω P Φ H3 g tr Φ tQ ^► 3

<P- d P- ¹ P Ω Ω tu P- »tr cn ^ rt F 1 tQ φ P- Ω rt Φ P- cn tr 0 Hi <P> P- P ¹ P- Φ φ CO HJ P- Φ tr 0 Φ Ω φ DJ P oo φ Hi Hf ts • Φ rt Φ (t: P ω DJ

Hi rt Ω P Ω H {Φ tr P cn • <: O φ rt P P- 1 P ⁾ : φ Hf Φ Hf er O cn Ω P

Hi PJ <d tr Ω Φ tr P- PJ DJ φ Q P- cn P tQ Φ Hf α P φ er P- P- CO PJ tr tn

P- P ¹ Φ FV HJ d P Hf H- ¹ P ¹ P- d Φ P tQ Ω. Ω rt P- Φ td d cn tr Φ 3 DJ P-

PP ¹ H (Φ co O Hf Hf DJ rt o P rt Hf Φ Φ Ω. P tQ HS P φ P Hf P φ P ¹ cn tQ P- er P- P- tQ td Φ Ω s- P ¹ do • co cn <er α Φ Q. Φ φ rt to P- Ωi 3 Φ P rt rt

Φ P Φ rt P ¹ P- P- ^• g tr P- P ¹ P rt ö O P- P- Hf JP ω NP "P Φ P ¹ P Ω Φ O

Hi Φ ω P- φ P Hi φ tQ d td Hi H (tQ Hf φ er rt ^ PJ φ P cn Φ rt Hf d 3 _^ ω Ω-i NN Φ Φ FV P φ d PJ φ tQ rt α Φ <Φ Φ Φ P tQ Hf Φ

P Φ Φ P- tQ Φ P Hf cn cn <Ω. P- FV P- ≤ φ Φ d Hf P- O d P- d co d Φ Φ Φ cn tQ tQ 1 ω Φ H- ¹ N tQ PJ Ω O rt P d ^: CO O DJ Hf Φ rt P <P p - cn Hf rt t-3 Φ co rt 1 er rt Φ φ 3 tr PM Φ d 1 P φ L P- P- N z Hl Φ tQ β 0 Qi P rt Φ Φ 3

P- • M H3 P- Hi P- er φ DJ o P- Hi cn tr O P 3 P- rt H (Φ Φ M P p- DJ:

Φ P- φ P ¹ P ⁾ tQ Φ Hf <o P φ Ω Φ 3 P l P- Φ o tQ l 5ξ DJ ι-fd P- H- ¹ tΛ

HS P- ö P Ω Ω. P Φ P rt P- Φ P cn tr P P- cn cn φ P Ω Φ P P- P ω Φ P O rt

N P- N tr φ cn P s: Φ Φ Ώ 3 Ω rt. rt tQ $ Ω H! tr co cn Qi Φ Hf N rt Hf er P- φ Φ P rt P- o co P- P Hi IQ tr Φ Φ w tr tn CO DJ Ω P- Φ Φ P- rt Φ Φ DJ P-

Φ d P ¹ P- - cn Ω P- φ S, Φ H- ¹ P er Ω Φ rt rt tr cn Hf H (rt Φ d P ^| Q

P 3 <rt V rt tr Ω Φ <CO Hi P- 3 d Φ P- tr PP ⁾ h rt d: rt cn φ cn P rt Φ cn d P>

Hf tΛ Ω P LO

O: 1 OO PJ tr Hf o rt U3 DJ: φ P ¹ P Φ d rt O rt Hf Hi Hf P- Hf rt β Hi DJ PJ Hf ω P Hi P- Φ tΛ g rt d Ω P tsi Hi DJ O 3 o J PJ o

P- φ S P tu cn Φ rt N rt d σ Hi FV O <Φ ω O FV tQ rt cn P Φ p- rt P P rt

IQ Ω P- CO P- P Φ d PJ cn FV rt cn tτl O: o Ω ω o? D Φ cn Φ Ωi P- rt Hi co cn Ω rt tr Ωi P- φ tr P tQ P l> rt rt P - P 1 Hi LO φ FV t-3 rt Φ P- Ω Hf d

Φ P Φ cn Hi φ H3 • P ¹ id ω PJ tQ PH ω d <P s tö cn Φ Ω cn tr φ §

P P- Hf rt Ω. P- P ¹ Φ φ Hi P- P d Φ Hf P- <P Φ φ O P- P- FV rt P Hi

FV ω Q d tΛ P- Pd Hf φ Ω Ω. Hf P DJ Ωi O Ω. H Q- rt cn cn tQ 3 P Φ O d DJ

Ω rt Hf Hf rt er Ω cn P tr cn P Φ Hf φ er φ Φ Ω rt Φ P- Φ P Hf cn t3 tΛ tr tr P>: CO Ω P- P '~ rt S | J φ cn Hl tQ Hf to d cn P tr FV rt 3 Φ cn P> rt

P- Φ P tr cn cn Φ tQ α Φ P- P- ω Φ o P Qi 0 cn P dd Φ 3 <! P φ Φ Hi • d P cn rt CO td o • -3 «d PJ d Φ φ P- P ¹ er Φ tQ Φ P P- P» • -3 P- Ω 3 3 rt DJ φ rt DJ: Φ P - Φ Φ to tΛ er »d P- Hf P t-3 P- P- φ Ω. cn er P> rt P ^► 3 DJ: P Hf 0 P tr tJ SO P P- Φ Φ P cn Qi P ¹ co P

DJ: cn W rt ω cn Φ tΛ DJ Qi DJ Ω Hf Ωi Φ N • • P ¹ P- Qi P- P ¹ Φ rt ^ Φ

Ω rt rt Ω. P- o Φ Ω. cn Φ P Φ rt cn Φ rt 3 Φ Ωi er Φ> ^ tr Φ tr J Ωi cn Φ Φ P ¹ tr Hf Φ P. IN. ö H (rt cn Ωi. P P- P- H- ¹ P ¹

Φ P ¹ P- 3 P- d p- 3 Q rt P- Φ Hf 3 rt d Φ PJ Φ o φ cn Ω cn &

P P- φ cn P P- Hf tQ er <P ¹ P- tu N Hf Hf Hf P 3 tQ Hf ö Ω o tr • N

Ωi rt ⁽ Q rt rt Ωi td tQ DJ d Φ Q 3 rt d D ⁾ cn P- Φ Φ tr Ω M t-3 Φ DJ d Φ tu P- co P ¹ P Hi P- Hf φ - Hf P tu < P- rt cn <Hf DJ tr P- P ¹ Hf α tr

Hf IQ O Φ α P- cn co 3 P

$. P- tr tQ cn cn P- Ω cn PO H- ¹ DJ P cn P- h- ¹

Ω => Φ Φ Ω H φ 1 Ω P- Ό P- rt M Φ rt ^ P- P "Hf rt 3 Hf N rt P- ¹ N 3 φ tr OP Hf tr rt s co tr cn» P- Ωi Φ Φ co o cn α - O φ rt 5 ^» d rt Φ <! P- cn P

Φ φ Ω rt φ Φ P- H (Ω> d rt P- Hf Φ Φ Φ P d P ¹ φ rt Φ tr do Ω Hf Hf P- tr 5 ^» O Hf P Φ tr φ« OP cn φ PP ¹ P - tQ P rt Hf II

O: Hi P- Φ φ H- * d Φ Hf DJ co O DJ d Hf ιQ Φ P- Φ rt cn tQ Hi er tr tr Ω P 1 1 cn rt P Φ CO s: rt P Ωi rt φ d φ Hf t-3 P FV Φ FV cn DJ d φ DJ P »

Φ tr Ωi N P- P Φ PJ: Ωi Φ N P- PP 1 P ¹ Φ 1 P 1 PPP er cn

Hl P- 1 P- P Φ Hf 1 P tQ φ 3 Ω 1 1 Φ φ ti 1 1 Hf 1 P

results in specific resistance values. In alternative embodiments, the series resistor R or the series resistors R can, however, not only be formed in polysilicon or in polysilicon with salicide blocking, but also by LDD implantations, N-wells or metal / via / contact chains.

The gate width of the gate connections G according to FIG. 4 is approximately 0.4 to 10 μm. In contrast to that shown in FIG. 4, a further improvement can be achieved by contacting the gate electrodes on both sides. As a result, the maximum distance to a contact hole drops to approximately 0.2 to 2.5 μm, and the corresponding resistance of the gate electrode G drops to a few ohms. This means that very high cut-off frequencies of the transistor can be achieved in conjunction with low noise and excellent high-frequency suitability.

Further advantages of the transistor structure according to FIG. 4 lie in the homogeneous firing of all transistor fingers or individual transistors due to the series resistors R, the good transferability of the layout described from one chip factory (Fab) to another, the good use of space and the simple adaptability to it The parameters required depending on the application due to the possibility of almost independent adjustability of ESD strength and high-frequency properties.

FIG. 5 shows a possible, simplified layout for a transistor structure with cascaded transistors in accordance with FIG. 3. While in the layout in accordance with FIG. 4 the second connection contact K2 is ESD-protected, in the transistor layout in accordance with FIG. 5 the first connection contact K 1 is ESD-protected , Furthermore, the transistor structure has a second connection K2, which is unprotected from electrostatic discharges. As can be seen in FIG. 3, the

Transistor structure two control connections 1, 2. The transistor structure comprises 16 individual transistor groups, each LO LO to to P ¹ P>

Lπ o LΠ o Π o LΠ

N co tΛ P W tr s; P Ω rt cn Qi

P- ⁾ Φ P co φ φ P- tr Φ P- d

Φ P ¹ P α P- P- a

§ Φ P P

P ¹ p- 1 tΛ rt Ωi Ωi tQ er N rt φ rt s φ

PJ P- he P Φ § H d Ωi

Hf Qi Φ tΛ CO er Ωi o P d

1 cn rt Φ Φ P- co Cd Hf

P- td Ω Φ P- P- Hi Φ 1 P- Ω cn P ¹ tr P- tQ ► P er tr rt Q Hl P FV FV td td Hf N Φ

Ω P- Φ p- co P Φ P- α

FV Φ P P- Φ P σ P P-

P- er d rt P- N 1 cn rt Ωi Hl

P Φ co ^ P Φ P- Hf Φ Hi tQ P Hi φ P "Φ cn P P d

Φ Φ Q. P Φ CO rt P Φ cn

OP P- P- P ¹ rt O co P P-

Ωi Ω Φ H3 φ P- Hf P- 0 φ §: tr Hf 3 tQ Φ cn Ωi P

Hi Φ Φ P- P φ FV P rt P- cn

P- P P P φ O Φ tQ φ cn Ωi co rt P- er H (Φ

Hf φ Φ <P- Φ rt Φ Φ td er tr HS cn cn P co P-

O: P • d rt P Ω. Ω U φ tr d td Hi O er Φ tr P- 1 rt rt Ω co Ω Hf • d Hi ω Φ φ tr α cn rt Φ rt Φ

P 1 f: rt ω P ¹ P- • CO 3 d Φ P- er rt P- LΠ

Ω co 3

Ω s ^* Ω Hf P- O Φ «P- rt

P ⁾ tr P FV tr P d tQ rt φ d P rt s: * - Hf FV o

Φ rt tQ d Φ 3 <Φ P

1 N N Φ Hf P- P- Φ P-

^ d tQ Φ rt rt P- P rt P-

Ω co P- Φ P Φ Φ Ω

P DJ: P er - P N LΠ d P- rt rt Φ d O P i

P> N Ωi P P d P P d P Φ

FV Φ P- P φ P ¹ P er 1 rt P- Hi P- 3 rt br "P- Qi tr Cd

Ω cn Φ NP: P ¹

O tr r rt rt H! Φ P- -J P O

Ω φ H - P i tQ Ω tr Hl Qi to Ωi tr P- FV

1 g P- cn p- LΠ Φ P P- ⁽ Q P- s DJ PO Φ Hf d PP tΛ Qi T: Hi tQ < ⁽ Q ω P d tr cn 3 H3 s: Φ o rt P> P o • d Hi Φ tQ P <

P ⁾ p ^* tQ tr Φ P P- Φ Φ

P § co Φ N i P cn P Ωi Hf

Ωi φ tQ P- P CO Φ Φ er

P Φ s: Hi CO P- P Hf Φ

Φ 3 Φ P- co - 3 o

H (S p: cn rt Φ s: cn

1 P- 1 rt Ω O H- ¹ Φ φ φ Φ tr Hi 1 P- Hf φ 1 1 rt

The principle described is not limited to CMOS transistors. An analogous transfer to other semiconductor structures, such as diodes, is also within the scope of the described invention.

LIST OF REFERENCE NUMBERS

1 gate connection

2 gate connection 3 diffusion area

4 coupling area

5 characteristic

6 characteristic

7 characteristic curve 8 characteristic curve

D drain

Kl circuit node

K2 circuit node n number R series resistor

R / n equivalent resistance

S Source

T CMOS transistor

Tl to Tn first sub-transistor Tl 'to Tn' second sub-transistor

Claims

claims 1. MOS transistor (T) having - A control connection (1), - A first and a second load connection (Kl, K2), which are coupled to a controlled path of the transistor (T), - Several current paths connected in parallel, which are connected on the one hand to the first load connection (Kl) and on the other hand to the second load connection (K2), of which the Current paths each comprise a series circuit comprising the controlled path of a first partial transistor (Tl to Tn) and a series resistor (R) connected to it, and one control connection (G) each to the partial transistors (Tl to Tn), - The control connections (G) of the partial transistors (Tl to Tn) are connected to one another and to the control connection (1) of the transistor (T). 2. MOS transistor according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the series resistors (R) each have the same resistance values. 3. MOS transistor according to claim 1 or 2, so that the series resistors (R) between the source connections of the controlled sections (S) and the source-side, second load connection (K2) of the MOS transistor (T) are connected. 4. MOS transistor according to claim 1 or 2, so that the series resistors (R) are connected between the drain connections of the controlled sections (D) and the drain-side, first load connection (Kl) of the MOS transistor (T). 5. MOS transistor according to one of claims 1 to 4, since you rchgek characterized that the MOS transistor (T) in each current path has a second sub-transistor (Tl ', T2' to Tn '), with a first sub-transistor (Tl to Tn) and a second sub-transistor (Tl 'to T') with their controlled sections and with the series resistor form a series connection. 6. MOS transistor according to one of claims 1 to 5, that the resistance of the series resistors (R) is in a range from 100 to 300 Ω. 7. MOS transistor according to one of claims 1 to 6, so that the individual transistors have a gate width which is between 0.4 μm and 10 μm. 8. MOS transistor according to one of claims 1 to 7, so that the individual transistors (Tl to Tn, Tl 'to Tn') have a gate connection (G) which is formed using salicide technology. 9. MOS transistor according to one of claims 1 to 8, d a d u r c h g e k e n n z e i c h n e t that the series resistors (R) are polysilicon resistors. 10. MOS transistor according to one of claims 1 to 9, d a d u r c h g e k e n n z e i c h n e t that the individual transistors (Tl to Tn, Tl 'to Tn') have a gate connection contacted via two contact holes.