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WO2002059970A2 - Transistor mos - Google Patents

Transistor mos Download PDF

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Publication number
WO2002059970A2
WO2002059970A2 PCT/DE2002/000177 DE0200177W WO02059970A2 WO 2002059970 A2 WO2002059970 A2 WO 2002059970A2 DE 0200177 W DE0200177 W DE 0200177W WO 02059970 A2 WO02059970 A2 WO 02059970A2
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
mos transistor
connection
transistors
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2002/000177
Other languages
German (de)
English (en)
Other versions
WO2002059970A3 (fr
Inventor
Andreas Dollinger
Herbert Koblmiller
Michael Mark
Martin Streibl
Volker Schultheiss
Martin Wendel
Günter HOFER
Günter Krasser
Josef Prainsack
Walter Schuchter
Wolfgang Stadler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of WO2002059970A2 publication Critical patent/WO2002059970A2/fr
Anticipated expiration legal-status Critical
Publication of WO2002059970A3 publication Critical patent/WO2002059970A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Definitions

  • the present invention relates to a MOS transistor.
  • the main error mechanisms are:
  • the object of the present invention is to provide a MOS transistor which is protected against electrostatic discharges and which is suitable for use in high-frequency technology, in particular in analog circuits.
  • the required resistance value of the series resistors can be easily determined from the parameters trigger voltage, holding voltage and intrinsic ESD strength of an individual transistor. These parameters can easily be determined by simulations in the early stages of development.
  • a parallel connection of a large number of individual transistors has an equally good or better ESD resistance.
  • the high-frequency properties in particular the noise properties, a transistor divided into a large number of individual transistors which are connected in parallel is significantly improved.
  • lic-Bl ⁇ cking be formed. Since salicide blocking requires its own mask and exposure level, which is typically in the region of 3% of the total wafer costs, the wafer costs can be significantly reduced in a manufacturing process in the wafer production.
  • the present principle makes it possible to adapt CMOS transistors and other CMOS components with regard to ESD properties and high-frequency properties practically independently of one another.
  • all series resistors of the CMOS transistor have the same resistance value. This leads to a particularly homogeneous current distribution in the event of a fault.
  • the series resistors are connected between the source connections of the controlled sections and the source connections of the CMOS transistor.
  • CMOS transistor has an ESD-protected source connection overall.
  • the series resistors are connected between the drain connections of the controlled sections and the drain connection of the CMOS transistor. This forms a CMOS transistor with a protected drain connection.
  • source and drain connections can be interchanged and can only be determined by external wiring of a CMOS transistor.
  • the CMOS transistor has a plurality of second sub-transistors, a first sub-transistor and a second sub-transistor each Part transistor with their controlled paths form a series connection.
  • Such a transistor can also be referred to as a cascaded transistor.
  • a first partial transistor with a second partial transistor and a series resistor can form a series circuit, a large number of such series circuits being connected in parallel with one another.
  • the resistance value of the series resistors is in a range from 100 to 300 ⁇ .
  • the individual transistors that is to say first and second individual transistors, have a gate width which is in a range between 0.4 and 10 ⁇ m.
  • a width of the individual transistors or fingers ⁇ 10 ⁇ m ensures a homogeneous current distribution across the width of the individual transistor.
  • the lower limit of 0.4 ⁇ m is currently a lower limit for technological reasons and can of course also be smaller in future technologies with a higher integration density.
  • the individual transistors each have a gate connection which is formed using salicide technology. As a result, particularly good high-frequency properties are achieved.
  • the series resistors are made of poly-silicon
  • the series resistors can be made of polysilicon technology. nic or in polysilicon with salicide blocking.
  • the production of the series resistors without salicide leads to an increase in the sheet resistance of the polysilicon by typically 1 to 2 orders of magnitude, which leads to a smaller area requirement of the resistor and thus to a smaller chip area requirement of the CMOS transistor.
  • the series resistors can also be implemented by LDD implantation, in n-doped tubs or with metal / via / contact chains.
  • the individual transistors each have a gate connection contacted on both sides.
  • the maximum distance to a contact hole drops to 0.2 to 2.5 ⁇ m and the corresponding resistance of the gate electrode drops to a few ohms. This enables very high cut-off frequencies, very low noise of the gate electrode and, overall, very good high-frequency suitability.
  • salicide is understood to be a self-aligned silicide.
  • FIG. 1 shows a first exemplary embodiment of a CMOS transistor according to the invention with a protected source connection
  • FIG. 2 shows an exemplary embodiment of the present invention with a protected drain connection
  • FIG. 3 shows an exemplary embodiment of the invention with a protected drain connection of cascaded transistors
  • Figure 4 shows an exemplary embodiment of a transistor according to Figure 1 or 2 in a simplified
  • FIG. 5 shows an exemplary embodiment of a CMOS transistor according to FIG. 3 on the basis of a simplified layout
  • Figure 6 is a diagram for comparing the ESD strength with respect to the component width according to the present principle with different parameters.
  • FIG. 1 shows in the right half of the figure the equivalent circuit diagram of a CMOS transistor T with a control connection 1 designed as a gate connection for controlling a controlled path.
  • the controlled path of the transistor T is coupled to connection nodes K1, K2.
  • the controlled path of the transistor T comprises a drain terminal D which is connected to the first circuit node Kl and a source terminal S which is connected to the second circuit node K2 via an equivalent resistor R / n for protection against electrostatic discharge.
  • the circuit diagram described, shown on the right in FIG. 1, is an equivalent circuit diagram of the CMOS transistor T, which is shown in the left half of FIG. 1 divided into individual, first sub-transistors.
  • the transistor T comprises first sub-transistors Tl, T2 ... Tn, which are connected in parallel with one another. All drain connections of the first partial transistors Tl to Tn are directly connected to one another in the first circuit node Kl. A series resistor R with one connection is connected to each source connection of the first partial transistors Tl to Tn, the further connections of the series resistors R being directly connected to one another in a second circuit node K2 are connected.
  • the control connections of the partial transistors Tl to Tn that is to say their gate connections, are connected to one another in the gate connection of the transistor T, which is designated as the first control input 1 of the transistor T. Accordingly, the first sub-transistors Tl to Tn form a parallel connection.
  • the transistor widths of the individual transistors Tl to Tn can be added to determine the transistor width of the transistor T.
  • a resistance value for the equivalent resistance R / n in the equivalent circuit diagram results from the quotient of the resistance value of a series resistor R and the number n of the first partial transistors Tl to Tn.
  • a CMOS transistor T is formed with a source connection protected from ESD pulses.
  • the resistance value of the individual series resistors R is in a range from 100 to 200 ⁇ .
  • the individual sub-transistors have a small gate width of ⁇ 10 ⁇ m. This results in a homogeneous current flow over the entire width of a single finger of the transistor. This ensures improved ESD resistance.
  • the gate width of the individual transistors or partial transistors is limited at the bottom by the technology.
  • the number n of the first partial transistors Tl to Tn can be, for example, in a range between 10 and 100.
  • the number n of the first partial transistors can be 64, which can be achieved by connecting 4 groups of 16 individual transistors in parallel.
  • FIG. 2 shows a further exemplary embodiment of a CMOS transistor T, which is likewise provided by a large number of parallel
  • DJ cn W rt ⁇ cn ⁇ t ⁇ DJ Qi DJ ⁇ Hf ⁇ i ⁇ N • • P 1 P- Qi P- P 1 ⁇ rt ⁇ ⁇
  • the series resistor R or the series resistors R can, however, not only be formed in polysilicon or in polysilicon with salicide blocking, but also by LDD implantations, N-wells or metal / via / contact chains.
  • the gate width of the gate connections G according to FIG. 4 is approximately 0.4 to 10 ⁇ m.
  • a further improvement can be achieved by contacting the gate electrodes on both sides.
  • the maximum distance to a contact hole drops to approximately 0.2 to 2.5 ⁇ m, and the corresponding resistance of the gate electrode G drops to a few ohms. This means that very high cut-off frequencies of the transistor can be achieved in conjunction with low noise and excellent high-frequency suitability.
  • transistor structure according to FIG. 4 lie in the homogeneous firing of all transistor fingers or individual transistors due to the series resistors R, the good transferability of the layout described from one chip factory (Fab) to another, the good use of space and the simple adaptability to it The parameters required depending on the application due to the possibility of almost independent adjustability of ESD strength and high-frequency properties.
  • FIG. 5 shows a possible, simplified layout for a transistor structure with cascaded transistors in accordance with FIG. 3. While in the layout in accordance with FIG. 4 the second connection contact K2 is ESD-protected, in the transistor layout in accordance with FIG. 5 the first connection contact K 1 is ESD-protected , Furthermore, the transistor structure has a second connection K2, which is unprotected from electrostatic discharges. As can be seen in FIG. 3, the
  • Transistor structure two control connections 1, 2.
  • the transistor structure comprises 16 individual transistor groups, each LO LO to to P 1 P>

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un transistor CMOS (T) comportant une pluralité de transistors individuels (T1 à Tn) connectés en parallèle. Ces transistors individuels (T1 à Tn) sont chacun dotés d'une résistance série (R) supplémentaire. La connexion décrite associe une protection contre les décharges électrostatiques aux bonnes propriétés haute fréquence d'un transistor CMOS et elle est particulièrement adaptée aux connexions analogiques.
PCT/DE2002/000177 2001-01-25 2002-01-21 Transistor mos Ceased WO2002059970A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10103297.8 2001-01-25
DE10103297A DE10103297A1 (de) 2001-01-25 2001-01-25 MOS-Transistor

Publications (2)

Publication Number Publication Date
WO2002059970A2 true WO2002059970A2 (fr) 2002-08-01
WO2002059970A3 WO2002059970A3 (fr) 2003-08-07

Family

ID=7671699

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2002/000177 Ceased WO2002059970A2 (fr) 2001-01-25 2002-01-21 Transistor mos

Country Status (2)

Country Link
DE (1) DE10103297A1 (fr)
WO (1) WO2002059970A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1544918A3 (fr) * 2003-12-19 2009-04-01 NEC Electronics Corporation Dispositif semiconducteur avec élément ESD
US20210174858A1 (en) * 2019-12-09 2021-06-10 International Business Machines Corporation Capacitive processing unit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005039365B4 (de) 2005-08-19 2022-02-10 Infineon Technologies Ag Gate-gesteuertes Fin-Widerstandselement, welches als pinch - resistor arbeitet, zur Verwendung als ESD-Schutzelement in einem elektrischen Schaltkreis und Einrichtung zum Schutz vor elektrostatischen Entladungen in einem elektrischen Schaltkreis

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3346518C1 (de) * 1983-12-22 1989-01-12 Texas Instruments Deutschland Gmbh, 8050 Freising Feldeffekttransistor mit isolierter Gate-Elektrode
US5157573A (en) * 1989-05-12 1992-10-20 Western Digital Corporation ESD protection circuit with segmented buffer transistor
DE4423591C2 (de) * 1994-07-06 1996-08-29 Itt Ind Gmbh Deutsche Schutzstruktur für integrierte Schaltungen
US5854504A (en) * 1997-04-01 1998-12-29 Maxim Integrated Products, Inc. Process tolerant NMOS transistor for electrostatic discharge protection
KR100263480B1 (ko) * 1998-01-13 2000-09-01 김영환 이에스디 보호회로 및 그 제조방법
US6043969A (en) * 1998-01-16 2000-03-28 Vantis Corporation Ballast resistors with parallel stacked NMOS transistors used to prevent secondary breakdown during ESD with 2.5 volt process transistors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1544918A3 (fr) * 2003-12-19 2009-04-01 NEC Electronics Corporation Dispositif semiconducteur avec élément ESD
US20210174858A1 (en) * 2019-12-09 2021-06-10 International Business Machines Corporation Capacitive processing unit
US11120864B2 (en) * 2019-12-09 2021-09-14 International Business Machines Corporation Capacitive processing unit

Also Published As

Publication number Publication date
WO2002059970A3 (fr) 2003-08-07
DE10103297A1 (de) 2002-08-22

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