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WO1995011525A1 - COMPOSANT INTEGRE MONOLITHIQUE HAUTE TENSION A CANAL p - Google Patents

COMPOSANT INTEGRE MONOLITHIQUE HAUTE TENSION A CANAL p Download PDF

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Publication number
WO1995011525A1
WO1995011525A1 PCT/DE1994/001195 DE9401195W WO9511525A1 WO 1995011525 A1 WO1995011525 A1 WO 1995011525A1 DE 9401195 W DE9401195 W DE 9401195W WO 9511525 A1 WO9511525 A1 WO 9511525A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
gate
gate oxide
oxide
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE1994/001195
Other languages
German (de)
English (en)
Inventor
Neil Davies
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of WO1995011525A1 publication Critical patent/WO1995011525A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the invention relates to a monolithically integrated p-channel high-voltage component, in which the gate connection terminal has a gate oxide / field oxide stage pointing in the direction of a drain connection terminal.
  • the p-channel high-voltage component structure connected to the drain terminal from a highly doped p + region to a lower doped p To let the ⁇ pass over.
  • the p ⁇ range must lie below the gate oxide of the gate terminal.
  • this component it is necessary that the p ⁇ region lying under the gate oxide is sufficient impoverished, i.e. the number of positive charge carriers is reduced. This avoids a high electrical field strength between the p-region and the gate connecting terminal in the gate oxide.
  • the monolithically integrated p-channel high-voltage component with the features mentioned in claim 1 has the advantage that a structure can be created which has a high and stable lateral breakdown voltage through the use of doping profiles optimized for other purposes . Because a weakly doped n ⁇ region is incorporated within a weakly doped p ⁇ region of the p-channel high-voltage component structure of the drain connection terminal, this structure is tolerant of variations in the sheet resistance and against adjustment fault tolerances. In particular, it is very advantageously achieved that when a voltage is applied between the drain connecting terminal and a source connecting terminal of the monolithically integrated p-channel high-voltage component, the p ⁇ region below the n ⁇ region and the n ⁇ region become completely impoverished, i.e. the number of free charge carriers is reduced. This completely avoids a high electrical field strength between the p-structure of the drain terminal and the gate oxide of the gate terminal, since the voltage breakdown in the high-voltage component now takes place far away from the gate oxide.
  • FIG. 1 shows a sectional view of a p-channel high-voltage component
  • Figure 2 shows a further sectional view of a p-channel high-voltage component in another embodiment.
  • FIG. 1 shows a monolithically integrated p-channel high-voltage component, generally designated by 10, with a lateral high-voltage structure.
  • the component 10 is shown in section and only schematically.
  • the component 10 has a semiconductor layer 12 which has an n-structure 14.
  • n ⁇ structure 14 p-structures are embedded 16 and 18, which are connected to a drain terminal D and a source terminal S.
  • the p structure 16 of the drain D has a highly doped p + region 20, which merges into a lower doped p ⁇ region 22.
  • the p-structure 18 of the source S has a similar structure, but is not to be considered further here for the invention. It is also subdivided into a p + region 24 and a p ⁇ region 26.
  • the p ⁇ regions 22 and 26 are overlapped by a gate oxide 28 which is connected to a gate connecting terminal G.
  • the gate oxide 28 on the drain side has a gate oxide / field oxide 30.
  • the stage Gate ⁇ oxide / field oxide step 30 is designed such that a field oxide region located between the gate oxide 28 and the p region 22 ⁇ 32nd An n-region 34 designed as an island is arranged within the p-region 22.
  • the n ⁇ region 34 is designed such that it begins with the gate oxide / field oxide stage 30 and extends in the direction of drain D below the gate oxide 28.
  • the arrangement shown in Figure 1 performs the following function: If a voltage is applied between the drain terminal D and the source terminal S, the p ⁇ region 22 under the n ⁇ region 34, and the n ⁇ region 34 itself, become completely depleted. This reduction in the available free charge carriers ensures that a high electric field strength between the p-structure 16 and the gate oxide 28 is avoided. As a result of this depletion of charge carriers in the surface region of the p-structure 16, the voltage breakdown in the component 10 now takes place far from the gate oxide 28. The breakthrough will take place here at the point designated by 36 in FIG. Due to this deep breakdown, the resulting breakdown voltage is higher and more stable.
  • the forward resistance of the component 10 is mainly determined by the series resistance of the channel resistance, that is to say the n ⁇ structure 14 and the p ⁇ region 22 of the p structure 16.
  • the addition of the n ⁇ region 34 in the p ⁇ region 22 thus causes an increase in the forward resistance, since the current in the p ⁇ region 22 must flow below the n ⁇ region 34.
  • the deep breakdown prevents migration of charge carriers into the gate oxide 28, so that despite a higher possible breakdown voltage, the life of the gate oxide 28 is not influenced.
  • n-region 34 in such a way that even at a high voltage between the gate connection terminal G and the source connection terminal S an additional channel region is created on the surface of the n ⁇ region 34. This additional channel area then forms a parallel current path, which brings about a reduction in the drain series resistance.
  • FIG. 2 shows a further embodiment variant of a component 10, the same parts as in FIG. 1 being provided with the same reference symbols and not being explained again.
  • the n ⁇ region 34 is designed such that it extends laterally over the gate oxide / field oxide stage 30 of the gate oxide 28.
  • the fact that the n ⁇ region 34 is extended beyond the gate terminal G means that when a higher voltage is applied between the gate terminal G and the source terminal S there is no additional channel region on the surface of the n ⁇ Regions 34 can arise. This is particularly advantageous when a reduction in the drain series resistance is not desired.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un composant intégré monolithique, haute tension, à canal p, pourvu d'une borne de grille, qui présente un étage d'oxyde épais/d'oxyde de grille dirigé en direction d'une borne de drain. Ce composant comporte une tension de claquage latérale stable et élevée. Il est prévu d'intégrer une zone du type n faiblement dopée (34) à l'intérieur d'une zone du type p faiblement dopée (23) d'une structure du type p (16) de la borne de drain (D).
PCT/DE1994/001195 1993-10-22 1994-10-12 COMPOSANT INTEGRE MONOLITHIQUE HAUTE TENSION A CANAL p Ceased WO1995011525A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4336054A DE4336054A1 (de) 1993-10-22 1993-10-22 Monolithisch integriertes p-Kanal-Hochspannungs-Bauelement
DEP4336054.8 1993-10-22

Publications (1)

Publication Number Publication Date
WO1995011525A1 true WO1995011525A1 (fr) 1995-04-27

Family

ID=6500755

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1994/001195 Ceased WO1995011525A1 (fr) 1993-10-22 1994-10-12 COMPOSANT INTEGRE MONOLITHIQUE HAUTE TENSION A CANAL p

Country Status (2)

Country Link
DE (1) DE4336054A1 (fr)
WO (1) WO1995011525A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19536753C1 (de) * 1995-10-02 1997-02-20 El Mos Elektronik In Mos Techn MOS-Transistor mit hoher Ausgangsspannungsfestigkeit
KR100223927B1 (ko) * 1996-07-31 1999-10-15 구본준 전계 효과 트랜지스터 및 그 제조방법
DE19753468A1 (de) * 1997-12-02 1999-07-08 Siemens Ag PN-Übergang mit erhöhter Durchbruchspannung
WO2003017349A2 (fr) * 2001-08-17 2003-02-27 IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik Transistor dmos
US6670685B2 (en) * 2002-05-24 2003-12-30 Texas Instruments Incorporated Method of manufacturing and structure of semiconductor device with floating ring structure
CA2458992A1 (fr) * 2002-10-25 2004-04-25 Shindengen Electric Manufacturing Co., Ltd. Dmos a canal court lateral, methode de fabrication connexe et dispositif a semi-conducteurs

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110264A (en) * 1980-02-04 1981-09-01 Oki Electric Ind Co Ltd High withstand voltage mos transistor
DE3816002A1 (de) * 1987-05-27 1988-12-08 Int Rectifier Corp Hochleistungs-mos-feldeffekttransistor sowie integrierte steuerschaltung hierfuer
DE4020478A1 (de) * 1989-07-04 1991-01-17 Fuji Electric Co Ltd Mos halbleitervorrichtung
EP0557253A2 (fr) * 1992-02-18 1993-08-25 STMicroelectronics S.r.l. Transistor VDMOS avec une caractéristique de claquage améliorée

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110264A (en) * 1980-02-04 1981-09-01 Oki Electric Ind Co Ltd High withstand voltage mos transistor
DE3816002A1 (de) * 1987-05-27 1988-12-08 Int Rectifier Corp Hochleistungs-mos-feldeffekttransistor sowie integrierte steuerschaltung hierfuer
DE4020478A1 (de) * 1989-07-04 1991-01-17 Fuji Electric Co Ltd Mos halbleitervorrichtung
EP0557253A2 (fr) * 1992-02-18 1993-08-25 STMicroelectronics S.r.l. Transistor VDMOS avec une caractéristique de claquage améliorée

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
A. W. LUDIKHUIZE: "HIGH-VOLTAGE DMOS AND PMOS IN ANALOG IC S", TECHNICAL DIGEST OF THE INTERNATIONAL ELECTRON DEVICES MEETING, 1982 SAN FRANCISCO, CA DECEMBER 13-14-15, pages 81 - 84 *
PATENT ABSTRACTS OF JAPAN vol. 5, no. 181 (E - 083) 20 November 1981 (1981-11-20) *

Also Published As

Publication number Publication date
DE4336054A1 (de) 1995-04-27

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