WO1995011525A1 - SOLID-STATE p-CHANNEL HIGH-VOLTAGE COMPONENT - Google Patents
SOLID-STATE p-CHANNEL HIGH-VOLTAGE COMPONENT Download PDFInfo
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- WO1995011525A1 WO1995011525A1 PCT/DE1994/001195 DE9401195W WO9511525A1 WO 1995011525 A1 WO1995011525 A1 WO 1995011525A1 DE 9401195 W DE9401195 W DE 9401195W WO 9511525 A1 WO9511525 A1 WO 9511525A1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Definitions
- the invention relates to a monolithically integrated p-channel high-voltage component, in which the gate connection terminal has a gate oxide / field oxide stage pointing in the direction of a drain connection terminal.
- the p-channel high-voltage component structure connected to the drain terminal from a highly doped p + region to a lower doped p To let the ⁇ pass over.
- the p ⁇ range must lie below the gate oxide of the gate terminal.
- this component it is necessary that the p ⁇ region lying under the gate oxide is sufficient impoverished, i.e. the number of positive charge carriers is reduced. This avoids a high electrical field strength between the p-region and the gate connecting terminal in the gate oxide.
- the monolithically integrated p-channel high-voltage component with the features mentioned in claim 1 has the advantage that a structure can be created which has a high and stable lateral breakdown voltage through the use of doping profiles optimized for other purposes . Because a weakly doped n ⁇ region is incorporated within a weakly doped p ⁇ region of the p-channel high-voltage component structure of the drain connection terminal, this structure is tolerant of variations in the sheet resistance and against adjustment fault tolerances. In particular, it is very advantageously achieved that when a voltage is applied between the drain connecting terminal and a source connecting terminal of the monolithically integrated p-channel high-voltage component, the p ⁇ region below the n ⁇ region and the n ⁇ region become completely impoverished, i.e. the number of free charge carriers is reduced. This completely avoids a high electrical field strength between the p-structure of the drain terminal and the gate oxide of the gate terminal, since the voltage breakdown in the high-voltage component now takes place far away from the gate oxide.
- FIG. 1 shows a sectional view of a p-channel high-voltage component
- Figure 2 shows a further sectional view of a p-channel high-voltage component in another embodiment.
- FIG. 1 shows a monolithically integrated p-channel high-voltage component, generally designated by 10, with a lateral high-voltage structure.
- the component 10 is shown in section and only schematically.
- the component 10 has a semiconductor layer 12 which has an n-structure 14.
- n ⁇ structure 14 p-structures are embedded 16 and 18, which are connected to a drain terminal D and a source terminal S.
- the p structure 16 of the drain D has a highly doped p + region 20, which merges into a lower doped p ⁇ region 22.
- the p-structure 18 of the source S has a similar structure, but is not to be considered further here for the invention. It is also subdivided into a p + region 24 and a p ⁇ region 26.
- the p ⁇ regions 22 and 26 are overlapped by a gate oxide 28 which is connected to a gate connecting terminal G.
- the gate oxide 28 on the drain side has a gate oxide / field oxide 30.
- the stage Gate ⁇ oxide / field oxide step 30 is designed such that a field oxide region located between the gate oxide 28 and the p region 22 ⁇ 32nd An n-region 34 designed as an island is arranged within the p-region 22.
- the n ⁇ region 34 is designed such that it begins with the gate oxide / field oxide stage 30 and extends in the direction of drain D below the gate oxide 28.
- the arrangement shown in Figure 1 performs the following function: If a voltage is applied between the drain terminal D and the source terminal S, the p ⁇ region 22 under the n ⁇ region 34, and the n ⁇ region 34 itself, become completely depleted. This reduction in the available free charge carriers ensures that a high electric field strength between the p-structure 16 and the gate oxide 28 is avoided. As a result of this depletion of charge carriers in the surface region of the p-structure 16, the voltage breakdown in the component 10 now takes place far from the gate oxide 28. The breakthrough will take place here at the point designated by 36 in FIG. Due to this deep breakdown, the resulting breakdown voltage is higher and more stable.
- the forward resistance of the component 10 is mainly determined by the series resistance of the channel resistance, that is to say the n ⁇ structure 14 and the p ⁇ region 22 of the p structure 16.
- the addition of the n ⁇ region 34 in the p ⁇ region 22 thus causes an increase in the forward resistance, since the current in the p ⁇ region 22 must flow below the n ⁇ region 34.
- the deep breakdown prevents migration of charge carriers into the gate oxide 28, so that despite a higher possible breakdown voltage, the life of the gate oxide 28 is not influenced.
- n-region 34 in such a way that even at a high voltage between the gate connection terminal G and the source connection terminal S an additional channel region is created on the surface of the n ⁇ region 34. This additional channel area then forms a parallel current path, which brings about a reduction in the drain series resistance.
- FIG. 2 shows a further embodiment variant of a component 10, the same parts as in FIG. 1 being provided with the same reference symbols and not being explained again.
- the n ⁇ region 34 is designed such that it extends laterally over the gate oxide / field oxide stage 30 of the gate oxide 28.
- the fact that the n ⁇ region 34 is extended beyond the gate terminal G means that when a higher voltage is applied between the gate terminal G and the source terminal S there is no additional channel region on the surface of the n ⁇ Regions 34 can arise. This is particularly advantageous when a reduction in the drain series resistance is not desired.
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Monolithisch integriertes p-Kanal-Hochspannungs- BauelementMonolithically integrated p-channel high-voltage component
Die Erfindung betrifft ein monolithisch integrier¬ tes p-Kanal-Hochspannungε-Bauelement, bei dem die Gate-Anschlußklemme eine in Richtung einer Drain- Anschlußklemme weisende Gateoxid/Feldoxid-Stufe aufweist.The invention relates to a monolithically integrated p-channel high-voltage component, in which the gate connection terminal has a gate oxide / field oxide stage pointing in the direction of a drain connection terminal.
Stand der TechnikState of the art
Es ist bekannt, bei sogenannten lateralen monoli¬ thisch integrierten p-Kanal-Hochspannungs-Bauele- menten die an der Drain-Anschlußklemme angeschlos¬ sene p-Kanal-Hochspannungs-Bauelement-Struktur von einem hochdotierten p+-Bereich in einen niedrigeren dotierten p~-Bereich übergehen zu lassen. Der p~- Bereich muß dabei unterhalb des Gateoxids der Gate- Anschlußklemme liegen. Damit dieses Bauelement hochspannungsfahig ist, ist es notwendig, daß sich der unter dem Gateoxid liegende p~-Bereich genügend verarmt, das heißt die Zahl an positiven Ladungsträgern verringert ist. Hierdurch wird eine hohe elektrische Feldstärke zwischen dem p~-Bereich und der Gate-Anschlußklemme in dem Gateoxid ver¬ mieden. Sollte dieser weniger dotierte p~-Bereich nicht vorhanden sein, besteht die Gefahr, daß aus der p-Struktur heiße Ladungsträger in das Gateoxid gelangen und damit dessen Lebensdauer verringern bzw. gegebenenfalls dieses sogar zerstören. Um diese Beeinflussung des Gateoxids zu vermeiden, ist es bereits bekannt, die Gate-Anschlußklemme mit einer Gateoxid/Feldoxid-Stufe auszubilden, wobei der p~-Bereich der an das Drain angeschlossenen p- Struktur unterhalb des Feldoxids der Gate¬ oxid/Feldoxid-Stufe angeordnet ist. Hiermit wird einem unerwünschten Ladungsträgeraustausch zwischen der p-Struktur und der Gate-Anschlußklemme durch das Oxid entgegengewirkt, da das Feldoxid als zu¬ sätzliche Zwischenschicht zwischen beiden angeord¬ net ist. Hierbei ist jedoch nachteilig, daß es bei der Herstellung einer solchen lateralen Hoch¬ spannungs-Bauelemente-Struktur zu Justiertoleranzen zwischen dem p~-Bereich und der Gateoxid/Feldoxid- Stufe kommen kann. Um diese Toleranzen auszu¬ gleichen, ist man gezwungen, die Struktur so zu entwerfen, daß bei einem optimal justierten Bau¬ element der p~-Bereich relativ weit unter das Gateoxid diffundiert und damit in jedem Fall die Gateoxid/Feldoxid-Stufe der Gate-Anschlußklemme übergreift. Hierbei ist jedoch nachteilig, daß diese Struktur unter Berücksichtigung der Justierungen nur dann richtig funktioniert, wenn der p~-Bereich einen relativ hohen Schichtwider¬ stand besitzt. Dieser hohe Schichtwiderstand wirkt sich jedoch wiederum negativ auf die Kennlinien des p-Kanal-Hochspannungs-Bauelementes aus.It is known that in the case of so-called lateral monolithically integrated p-channel high-voltage components, the p-channel high-voltage component structure connected to the drain terminal from a highly doped p + region to a lower doped p To let the ~ pass over. The p ~ range must lie below the gate oxide of the gate terminal. In order for this component to be able to withstand high voltages, it is necessary that the p ~ region lying under the gate oxide is sufficient impoverished, i.e. the number of positive charge carriers is reduced. This avoids a high electrical field strength between the p-region and the gate connecting terminal in the gate oxide. If this less doped p ~ region is not present, there is a risk that hot charge carriers will enter the gate oxide from the p-structure and thus reduce its service life or possibly even destroy it. In order to avoid this influencing of the gate oxide, it is already known to design the gate connecting terminal with a gate oxide / field oxide stage, the p ~ region of the p structure connected to the drain below the field oxide of the gate oxide / field oxide Stage is arranged. This counteracts an undesired charge carrier exchange between the p-structure and the gate terminal by the oxide, since the field oxide is arranged as an additional intermediate layer between the two. However, it is disadvantageous here that adjustment tolerances between the p-region and the gate oxide / field oxide stage can occur during the production of such a lateral high-voltage component structure. In order to compensate for these tolerances, it is necessary to design the structure in such a way that, in the case of an optimally adjusted component, the p ~ region diffuses relatively far below the gate oxide and thus in any case the gate oxide / field oxide stage of the gate Terminal overlaps. However, it is disadvantageous that this structure only functions properly when taking the adjustments into account if the p ~ region has a relatively high layer resistance. However, this high sheet resistance in turn has a negative effect on the characteristics of the p-channel high-voltage component.
Weiterhin ist bekannt, die Struktur des Hochspan¬ nungsbauelementes mit einem sogenannten εelbst- justierenden LOCOS Prozeß herzustellen. Dadurch, daß hier die p~-Diffusion an der Gateoxid/Feldoxid- Stufe selbstjustiert ist, das heißt der p~-Bereich nicht mehr weit unter das Gateoxid reichen muß, ist es möglich, einen niedrigeren p~-Schichtwiderstand zu verwenden. Hierbei ist jedoch nachteilig, daß dieser niedrigere p~-Schichtwiderstand mit den An¬ forderungen anderer Bauelemente, die mit der gleichen p~-Diffusion hergestellt werden, nicht kompatibel ist.It is also known to produce the structure of the high-voltage component using a so-called self-adjusting LOCOS process. Because the p ~ diffusion at the gate oxide / field oxide stage is self-adjusted here, that is to say the p ~ region no longer has to extend far below the gate oxide, it is possible to use a lower p ~ layer resistance. However, it is disadvantageous here that this lower p ~ layer resistance is not compatible with the requirements of other components which are produced with the same p ~ diffusion.
Vorteile der ErfindungAdvantages of the invention
Das monolithisch integrierte p-Kanal-Hochspannungs- Bauelement mit den im Anspruch 1 genannten Merk¬ malen hat demgegenüber den Vorteil, daß eine Struktur geschaffen werden kann, die durch die Verwendung von für andere Zwecke optimierte Dotierungsprofile eine hohe und stabile laterale Durchbruch-Spannung aufweist. Dadurch, daß inner¬ halb eines schwach dotierten p~-Bereiches der p- Kanal-Hochspannungs-Bauelement-Struktur der Drain- Anschlußklemme ein schwach dotierter n~-Bereich eingebracht ist, ist diese Struktur tolerant gegen Variationen im Schichtwiderstand und gegen Justier- fehlertoleranzen. Insbesondere wird sehr vor¬ teilhaft erreicht, daß beim Anlegen einer Spannung zwischen der Drain-Anschlußklemme und einer Source- Anschlußklemme des monolithisch integrierten p- Kanal-Hochspannungs-Bauelementes der p~- Bereich unter dem n~-Bereich und der n~-Bereich selbst vollständig verarmen, das heißt die Zahl der freien Ladungsträger reduziert wird. Hierdurch wird eine hohe elektriεche Feldstärke zwischen der p- Struk¬ tur der Drain-Anschlußklemme und dem Gateoxid der Gate-Anschlußklemme vollkommen vermieden, da der Spannungsdurchbruch in dem Hochspannungs-bauelement nunmehr weit entfernt von dem Gateoxid stattfindet.The monolithically integrated p-channel high-voltage component with the features mentioned in claim 1 has the advantage that a structure can be created which has a high and stable lateral breakdown voltage through the use of doping profiles optimized for other purposes . Because a weakly doped n ~ region is incorporated within a weakly doped p ~ region of the p-channel high-voltage component structure of the drain connection terminal, this structure is tolerant of variations in the sheet resistance and against adjustment fault tolerances. In particular, it is very advantageously achieved that when a voltage is applied between the drain connecting terminal and a source connecting terminal of the monolithically integrated p-channel high-voltage component, the p ~ region below the n ~ region and the n ~ region become completely impoverished, i.e. the number of free charge carriers is reduced. This completely avoids a high electrical field strength between the p-structure of the drain terminal and the gate oxide of the gate terminal, since the voltage breakdown in the high-voltage component now takes place far away from the gate oxide.
Weitere vorteilhafte Ausgestaltungen der Erfindung ergeben sich aus den übrigen in den Unteranεprüchen genannten Merkmalen.Further advantageous refinements of the invention result from the other features mentioned in the subclaims.
Zeichnungdrawing
Die Erfindung wird nachfolgend in Ausführungs¬ beispielen anhand der zugehörigen Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below in exemplary embodiments with reference to the associated drawings. Show it:
Figur 1 eine Schnittdarstellung eines p-Kanal- Hochspannungs-Bauelementes und1 shows a sectional view of a p-channel high-voltage component and
Figur 2 eine weitere Schnittdarstellung eines p- Kanal-Hochspannungs-Bauelement in einer anderen Ausführung.Figure 2 shows a further sectional view of a p-channel high-voltage component in another embodiment.
Beschreibung der Ausführungsbeispiele Figur 1 zeigt ein allgemein mit 10 bezeichnetes mo¬ nolithisch integriertes p-Kanal-Hochspannungs-Bau- element mit einer lateralen Hochspannungsstruktur. Das Bauelement 10 ist im Schnitt und lediglich schematisch dargestellt. Das Bauelement 10 weist eine Halbleiterschicht 12 auf, die eine n~-Struktur 14 beεitzt. In die n~-Struktur 14 sind p-Strukturen 16 und 18 eingebettet, die mit einer Drain- Anschlußklemme D bzw. einer Source-Anschlußklemme S verbunden sind. Die p-Struktur 16 des Drains D besitzt einen hoch dotierten p+-Bereich 20, der in einen niedriger dotierten p~-Bereich 22 übergeht. Die p-Struktur 18 der Source S ist ähnlich auf¬ gebaut, jedoch hier für die Erfindung nicht weiter zu betrachten. Sie untergliedert sich ebenfalls in einen p+-Bereich 24 und einen p~-Bereich 26. Die p~ -Bereiche 22 und 26 werden von einem Gateoxid 28 übergriffen, das mit einer Gate-Anschlußklemme G verbunden ist. Das Gateoxid 28 besitzt drainseitig eine Gateoxid/Feldoxid-Stufe 30. Die Gate¬ oxid/Feldoxid-Stufe 30 ist dabei so ausgelegt, daß sich zwischen dem Gateoxid 28 und dem p~-Bereich 22 ein Feldoxidbereich 32 befindet. Innerhalb des p~- Bereiches 22 ist ein als Insel ausgebildeter n~-Be- reich 34 angeordnet. Der n~-Bereich 34 ist dabei so ausgebildet, daß er mit der Gateoxid/Feldoxid-Stufe 30 beginnt und sich in Richtung Drain D unterhalb des Gateoxids 28 erstreckt.Description of the embodiments FIG. 1 shows a monolithically integrated p-channel high-voltage component, generally designated by 10, with a lateral high-voltage structure. The component 10 is shown in section and only schematically. The component 10 has a semiconductor layer 12 which has an n-structure 14. In the n ~ structure 14 p-structures are embedded 16 and 18, which are connected to a drain terminal D and a source terminal S. The p structure 16 of the drain D has a highly doped p + region 20, which merges into a lower doped p ~ region 22. The p-structure 18 of the source S has a similar structure, but is not to be considered further here for the invention. It is also subdivided into a p + region 24 and a p ~ region 26. The p ~ regions 22 and 26 are overlapped by a gate oxide 28 which is connected to a gate connecting terminal G. The gate oxide 28 on the drain side has a gate oxide / field oxide 30. The stage Gate¬ oxide / field oxide step 30 is designed such that a field oxide region located between the gate oxide 28 and the p region 22 ~ 32nd An n-region 34 designed as an island is arranged within the p-region 22. The n ~ region 34 is designed such that it begins with the gate oxide / field oxide stage 30 and extends in the direction of drain D below the gate oxide 28.
Die in Figur 1 gezeigte Anordnung übt folgende Funktion aus: Wenn zwischen der Drain-Anschlußklemme D und der Source-Anschlußklemme S eine Spannung angelegt wird, verarmt der p~-Bereich 22 unter dem n~-Be- reich 34, und der n~-Bereich 34 selbst, voll¬ ständig. Durch diese Reduzierung der vorhandenen freien Ladungsträger wird erreicht, daß eine hohe elektrische Feldstärke zwischen der p-Struktur 16 und dem Gateoxid 28 vermieden wird. Durch diese Verarmung von Ladungsträgern im Oberflächenbereich der p-Struktur 16 findet nun der Spannungs¬ durchbruch in dem Bauelement 10 weit von dem Gateoxid 28 statt. Der Durchbruch wird hier an der in Figur 1 mit 36 bezeichneten Stelle stattfinden. Durch diesen tiefliegenden Durchbruch ist die daraus resultierende Durchbruchspannung höher und stabiler. Dies resultiert darauε, da der Durch¬ laßwiderstand des Bauelementes 10 hauptsächlich durch den Serienwiderstand des Kanalwiderstands, also der n~-Struktur 14 und des p~-Bereiches 22 der p-Struktur 16 bestimmt wird. Das Hinzufügen des n~- Bereiches 34 in dem p~-Bereich 22 verurεacht somit ein Ansteigen des Durchlaßwiderstands, da der Strom in dem p~-Bereich 22 unterhalb des n~-Bereichs 34 fließen muß. Durch den tiefliegenden Durchbruch wird insbesondere ein Abwandern von Ladungsträgern in das Gateoxid 28 vermieden, so daß trotz einer höheren möglichen Durchbruchspannung die Lebens¬ dauer des Gateoxids 28 nicht beeinflußt wird. Zu der in Figur 1 gezeigten Variante ist eε auch möglich, den n~-Bereich 34 so auszubilden, daß auch bei einer hohen Spannung zwischen der Gate- Anschlußklemme G und der Source-Anschlußklemme S ein zusätzliches Kanalgebiet auf der Oberfläche des n~-Bereiches 34 entsteht. Dieses zusätzliche Kanal¬ gebiet bildet dann einen parallelen Strompfad, der eine Verringerung des Drainserienwiderεtandes be¬ wirkt.The arrangement shown in Figure 1 performs the following function: If a voltage is applied between the drain terminal D and the source terminal S, the p ~ region 22 under the n ~ region 34, and the n ~ region 34 itself, become completely depleted. This reduction in the available free charge carriers ensures that a high electric field strength between the p-structure 16 and the gate oxide 28 is avoided. As a result of this depletion of charge carriers in the surface region of the p-structure 16, the voltage breakdown in the component 10 now takes place far from the gate oxide 28. The breakthrough will take place here at the point designated by 36 in FIG. Due to this deep breakdown, the resulting breakdown voltage is higher and more stable. This results from the fact that the forward resistance of the component 10 is mainly determined by the series resistance of the channel resistance, that is to say the n ~ structure 14 and the p ~ region 22 of the p structure 16. The addition of the n ~ region 34 in the p ~ region 22 thus causes an increase in the forward resistance, since the current in the p ~ region 22 must flow below the n ~ region 34. The deep breakdown prevents migration of charge carriers into the gate oxide 28, so that despite a higher possible breakdown voltage, the life of the gate oxide 28 is not influenced. In addition to the variant shown in FIG. 1, it is also possible to design the n-region 34 in such a way that even at a high voltage between the gate connection terminal G and the source connection terminal S an additional channel region is created on the surface of the n ~ region 34. This additional channel area then forms a parallel current path, which brings about a reduction in the drain series resistance.
In der Figur 2 ist eine weitere AusführungsVariante eines Bauelementes 10 gezeigt, wobei gleiche Teile wie in Figur 1 mit gleichen Bezugszeichen versehen sind und nicht nochmals erläutert werden. In der hier gezeigten Variante ist der n~-Bereich 34 so ausgebildet, daß er εich lateral über die geεa te Gateoxid/Feldoxid-Stufe 30 des Gateoxids 28 er¬ streckt. Dadurch, daß der n~-Bereich 34 über die Gate-Anεchlußklemme G hinaus verlängert ist, wird erreicht, daß bei Anlegen einer höheren Spannung zwischen der Gate-Anεchlußklemme G und der Source- Anschlußklemme S kein zusätzliches Kanalgebiet auf der Oberfläche des n~-Bereicheε 34 entstehen kann. Dieε iεt inεbesondere dann vorteilhaft, wenn eine Verringerung des Drainserienwiderstandes nicht er¬ wünscht ist. FIG. 2 shows a further embodiment variant of a component 10, the same parts as in FIG. 1 being provided with the same reference symbols and not being explained again. In the variant shown here, the n ~ region 34 is designed such that it extends laterally over the gate oxide / field oxide stage 30 of the gate oxide 28. The fact that the n ~ region 34 is extended beyond the gate terminal G means that when a higher voltage is applied between the gate terminal G and the source terminal S there is no additional channel region on the surface of the n ~ Regions 34 can arise. This is particularly advantageous when a reduction in the drain series resistance is not desired.
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE4336054A DE4336054A1 (en) | 1993-10-22 | 1993-10-22 | Monolithically integrated p-channel high-voltage component |
| DEP4336054.8 | 1993-10-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1995011525A1 true WO1995011525A1 (en) | 1995-04-27 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE1994/001195 Ceased WO1995011525A1 (en) | 1993-10-22 | 1994-10-12 | SOLID-STATE p-CHANNEL HIGH-VOLTAGE COMPONENT |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE4336054A1 (en) |
| WO (1) | WO1995011525A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19536753C1 (en) * | 1995-10-02 | 1997-02-20 | El Mos Elektronik In Mos Techn | MOS transistor with high output withstand voltage |
| KR100223927B1 (en) * | 1996-07-31 | 1999-10-15 | 구본준 | Field effect transistor and manufacture thereof |
| DE19753468A1 (en) * | 1997-12-02 | 1999-07-08 | Siemens Ag | PN junction with increased breakdown voltage |
| WO2003017349A2 (en) * | 2001-08-17 | 2003-02-27 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | Dmos transistor |
| US6670685B2 (en) * | 2002-05-24 | 2003-12-30 | Texas Instruments Incorporated | Method of manufacturing and structure of semiconductor device with floating ring structure |
| CA2458992A1 (en) * | 2002-10-25 | 2004-04-25 | Shindengen Electric Manufacturing Co., Ltd. | Lateral short-channel dmos, method of manufacturing the same, and semiconductor device |
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|---|---|---|---|---|
| JPS56110264A (en) * | 1980-02-04 | 1981-09-01 | Oki Electric Ind Co Ltd | High withstand voltage mos transistor |
| DE3816002A1 (en) * | 1987-05-27 | 1988-12-08 | Int Rectifier Corp | HIGH PERFORMANCE MOS FIELD EFFECT TRANSISTOR AND INTEGRATED CONTROL CIRCUIT THEREFOR |
| DE4020478A1 (en) * | 1989-07-04 | 1991-01-17 | Fuji Electric Co Ltd | MOS SEMICONDUCTOR DEVICE |
| EP0557253A2 (en) * | 1992-02-18 | 1993-08-25 | STMicroelectronics S.r.l. | VDMOS transistor with improved breakdown characteristics |
-
1993
- 1993-10-22 DE DE4336054A patent/DE4336054A1/en not_active Withdrawn
-
1994
- 1994-10-12 WO PCT/DE1994/001195 patent/WO1995011525A1/en not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56110264A (en) * | 1980-02-04 | 1981-09-01 | Oki Electric Ind Co Ltd | High withstand voltage mos transistor |
| DE3816002A1 (en) * | 1987-05-27 | 1988-12-08 | Int Rectifier Corp | HIGH PERFORMANCE MOS FIELD EFFECT TRANSISTOR AND INTEGRATED CONTROL CIRCUIT THEREFOR |
| DE4020478A1 (en) * | 1989-07-04 | 1991-01-17 | Fuji Electric Co Ltd | MOS SEMICONDUCTOR DEVICE |
| EP0557253A2 (en) * | 1992-02-18 | 1993-08-25 | STMicroelectronics S.r.l. | VDMOS transistor with improved breakdown characteristics |
Non-Patent Citations (2)
| Title |
|---|
| A. W. LUDIKHUIZE: "HIGH-VOLTAGE DMOS AND PMOS IN ANALOG IC S", TECHNICAL DIGEST OF THE INTERNATIONAL ELECTRON DEVICES MEETING, 1982 SAN FRANCISCO, CA DECEMBER 13-14-15, pages 81 - 84 * |
| PATENT ABSTRACTS OF JAPAN vol. 5, no. 181 (E - 083) 20 November 1981 (1981-11-20) * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4336054A1 (en) | 1995-04-27 |
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