DE19753468A1 - PN junction with increased breakdown voltage - Google Patents

Description

The invention relates to a semiconductor component, in particular a PN junction with increased breakdown voltage, as well as a Method for producing a semiconductor region, the one desired conductivity type and a desired average Has dopant concentration.

PN transitions, i.e. the meeting of a P-manager Semiconductor region with an N-conducting semiconductor region, play with almost all active electronic components ne important role. Many parameters of the active components are contained directly by the properties of them the PN transitions. For example, the Breakdown voltage of an N-channel DMOS power transistor in the essentially from the breakdown voltage of the between the P- conducting channel area ("P-Body") and the N-conducting drain offers arranged PN transition.

The goal of many developments is therefore the properties a PN transition so that the desired Result parameters of the active components. Was in particular and it is the goal of many developments that breakthrough chip increase of a PN transition.

Fig. 1 shows a schematic representation of a PN transition according to the prior art. A P-type semiconductor region 2 is generated in an N-type semiconductor region 1 by P + doping. For this purpose, a mask 3 , for example a paint mask, which has an opening 4 above the semiconductor region 2 is used . At the interface 5 between the two semiconductor regions, a PN junction 7 is formed , which has a space charge zone 6 arranged around this interface 5 and an electric field E.

If the PN junction 7 is now operated in the reverse direction, ie a positive voltage is applied to the N-conducting region 1 , the space charge zone 6 increases and the field E is strengthened. If the field strength exceeds a critical value, charge carriers can be generated in the space charge zone 6 by shock ionization, which ultimately leads to a so-called "avalanche breakthrough". The voltage at which the field strength exceeds the critical value is called the breakdown voltage.

To increase the breakdown voltage, so-called "field rings"("floating field rings") are seen in the prior art ( FIG. 2). These are further P + -doped semiconductor regions, which are arranged in the vicinity of a PN junction. If the PN junction 7 is operated in the reverse direction, the additional semiconductor region 8 increases the space charge zone 6 , as a result of which the field strength within the space charge zone 6 is reduced. Accordingly, a larger voltage can now be applied to the PN junction 7 before an avalanche breakdown occurs. To generate the further P + -doped semiconductor region 8 , an additional opening 9 is usually provided in the mask 3 , which serves to produce the semiconductor region 2 .

In a finished component, the additional P + -doped semiconductor region 8 does not have its own connections, so that it is only in contact with the N-conducting semiconductor region 1 . Therefore, charges can accumulate in the semiconductor region 8 , which cannot flow away due to the PN junction between the semiconductor region 1 and the semiconductor region 8 . This ultimately leads to the fact that the electrical potential of this semiconductor region 8 cannot be determined.

The fact that the electrical potential of the semiconductor region 8 is not fixed, however, has negative effects on the electrical parameters of the component in which the PN junction 7 is integrated once.

The invention is therefore based on the object Increase the break voltage of a PN junction so that negative Effects on other parameters largely avoided the.

This task is performed by the semiconductor device according to the patent Claim 1 solved. Further advantageous embodiments, Embodiments and aspects of the present invention ben from the subclaims, the description and the enclosed drawings.

According to the invention, a semiconductor component with a P- conductive area and an N-type area, which coexist are in contact along an interface so that a PN junction with a space arranged around this interface charge zone is formed, provided. The invention According semiconductor device is characterized in that in the P-type region and / or in the N-type region at least one further area is provided, which the same conductivity type as the surrounding area and one has lower conductivity than the surrounding area or is intrinsic and which of the interface between the P-type region and the N-type region so spaced  is arranged that when the PN transition in the reverse direction be is driven, the space charge zone around the interface the white area before the breakdown voltage of the PN Transition is reached.

In contrast to the field rings according to the prior art the further area according to the invention sits in the same direction skill type like the surrounding area. So there will be none additional PN transitions that lead to unwanted La lead collections. The fact that further area according to the invention has a lower conductivity as the surrounding area, however, is the wider area able, similar to the field rings according to the state of the art Technology to enlarge the space charge zone around the PN junction Change if the PN junction is operated in the reverse direction. By enlarging the space charge zone decreases the electric field within the space charge zone. Dement speaking, a greater voltage can now be applied to the PN junction be created before an avalanche breakthrough occurs.

The further area is preferably adjacent to the locations the interface between the P-type region and the N- conductive area, where the interface the has the greatest curvature. At the points where the border surface has the greatest curvature, the electrical reaches Field in the space charge zone for an avalanche breakdown critical field strength fastest. Therefore it is an advantage if the space charge zone is just in the vicinity of this Digits through the further areas according to the invention ßert, so that the electric field within the Raumla zone is reduced.  

The further area according to the invention is spaced from Interface between the P-type region and the N-type Area arranged, d. H. the wider area touches the border do not area. The further area is preferably outside the Space charge zone arranged when no external voltage on the PN transition is created. Such an arrangement of the wide Ren area has the advantage that an increase in the electrical resistance of the PN junction when the PN junction is in Forward direction is operated, is largely avoided.

According to an advantageous embodiment of the invention ß semiconductor component is the conductivity further Area by at least one order of magnitude, preferably at least at least two orders of magnitude, smaller than the conductivity of the surrounding area.

The P-type area and the N-type area are below doped differently, it is preferred if the white tere area is arranged in the weakly doped area.

It is further preferred if the further area is adjacent is arranged to the surface of the surrounding area.

According to an advantageous embodiment of the invention ß semiconductor component is the further area below arranged an insulation layer. It is further preferred if a conductive layer is attached over the insulation layer is arranged, whose distance to the surface of the further Ge surrounding area with increasing distance from the PN Transition gets bigger. Due to charges in the conductive layer The expansion of the Space charge zone are affected. So you can choose suitable te charges in the conductive layer and the invention  other areas reinforce each other in their effect and increase the breakdown voltage of the PN junction.

In addition, it is preferred if the wider area is the PN transition surrounds in a ring.

According to another aspect of the present invention a method for producing a semiconductor region, the ei a desired conductivity type and a desired average re dopant concentration provided.

A simple method for producing a semiconductor region with a desired conductivity type has already been described in connection with FIG. 1. There, the P-type semiconductor region 2 was generated by means of the mask 3 and a P + doping. If several different areas, which are to have different dopings and different conductivity types, are now to be generated, then according to this method, a separate mask and doping, for example a separate ion implantation, is necessary for each area. In particular, the generation of the further area in the semiconductor component according to the invention would thus require its own mask technology and doping. A semiconductor device according to the invention produced by a conventional method is therefore significantly more expensive than a PN junction according to the prior art.

It is therefore another object of the present invention a simple and inexpensive method for generating egg nes semiconductor region that has a desired conductivity type and a desired average dopant concentration one has to provide.  

This object is achieved by the method according to claim 10 solved. Further advantageous embodiments, Ausgestaltun conditions and aspects of the present invention result from the dependent claims, the description and the enclosed Drawings.

According to the invention, a method for producing a semiconductor region, which has a desired conductivity type and a desired effective dopant concentration, is provided at a predetermined dopant flux density and doping time. The method according to the invention comprises the steps:

• a) a semiconductor region is provided which a Initial doping with dopants of a first conductive type and has an output conductivity.
• b) a mask is provided over the semiconductor region, which has a plurality of openings so that part of the Surface of the semiconductor region covered and part of the Surface of the semiconductor region is not covered,
• c) a dopant of a second, opposite guide Ability type with the given dopant flux density and in the predetermined doping time in the semiconductor Ge introduced,

where the ratio of the covered surface to that is not covered surface of the semiconductor region is selected so that produces the desired effective dopant concentration and a semiconductor region with one opposite the out reduced conductivity arises.  

The inventive method takes advantage of the fact that the manufacture of an integrated circuit multiple dotie tion of the semiconductor substrate must be made to different components with the desired properties to be able to generate. The number remains for cost reasons however, the different doping is narrowly limited.

The inventive method now uses a pre given doping with a predetermined dopant flux density and doping time, which is required, for example, to generate a P or N-tub is used at another location to generate egg nes additional semiconductor region. So with just one egg ner doping two (or more) different semiconductor gene offer with a different doping. In this way, the wider field of the invention Semiconductor component simple and cost-saving without additional be made doping.

The distances between the openings in the mask are preferred chooses to create a coherent semiconductor region, where the difference between dopant concentration maximum and the minimum dopant concentration within the half area is less than 3 orders of magnitude.

It is further preferred if the distances are more adjacent Openings in the mask are each smaller than the diffusion length ge of the dopant are selected in the semiconductor region.

The openings in the mask are preferably in a chess board-like patterns arranged.

It is further preferred if the dopant is replaced by a Diffusion from the gas phase or from a doping layer or  through an ion implantation with subsequent dopant activation is introduced into the semiconductor region.

The invention is based on the figures of the drawing shown in more detail. Show it:

Fig. 1 and 2 are schematic representations of PN junctions, according to the prior art

3a and 3b are a schematic representation. OF INVENTION a to the invention the semiconductor device,

FIGS. 4 and 5 is a schematic representation of a method according to the Invention, and

Fig. 6 is a schematic plan view of the mask used in Fig. 5.

Fig. 3a shows an application of the semiconducting terbauelements invention in a DMOS transistor arrangement. An N-type semiconductor region 13 is arranged, for example, epitaxially over a P-type semiconductor material 10 of any orientation. The semiconductor region 13 is contacted by an N-conductive zone 12 of high conductivity (“buried layer”) with a low tube shape. The low-resistance zone 12 is connected to the surface of the arrangement by an N-type deep diffusion region 27 of high conductivity, which is in contact with the drain terminal 23 of the DMOS transistor arrangement.

Furthermore, a P-type semiconductor region 14 is arranged in the N-type semiconductor region 13 . A PN junction 17 , which has a space charge zone 16 , thus results at the interface 15 of the two semiconductor regions. The P-type semiconductor region 14 is also contacted by the N-type semiconductor region 22 , which is in contact with the source terminal 24 of the DMOS transistor arrangement.

Between the source terminal 24 and the drain terminal 23 of the DMOS transistor arrangement, an insulation 26 , for example a Locos isolation, is arranged. Furthermore, an insulating oxide layer 28 (“gate oxide”) is arranged on the surface of the arrangement and a conductive layer 29 (“gate”) is arranged above the oxide layer 28 .

On the surface of the N-type semiconductor region 13 , a further region 18 is provided in the semiconductor region 13 , which is also N-type but has a conductivity that is three orders of magnitude lower than that of the semiconductor region 13 . The further region 18 is arranged adjacent to the positions 30 of the interface between the P-type region 14 and the N-type region 13 , at which the interface 15 has the greatest curvature. Furthermore, the wide re region 18 is arranged below or adjacent to the transition from the oxide layer 28 to the insulation 26 .

Fig. 3a shows the semiconductor device according to the invention in a state in which no external voltages are applied to the semiconductor device according to the invention. It is known that the further semiconductor region 18 is so spaced from the PN junction 17 that it is arranged outside of the space charge zone 16 in this state.

FIG. 3b shows semiconductor device according to the invention in a state in which a positive voltage to the drain terminal 23 are applied. This has the consequence that the PN junction 17 is operated in the reverse direction. It can be seen that the further semiconductor region 18 is so spaced from the PN junction 17 that it is arranged in this state within the enlarged space charge zone 16 ver. Accordingly, the further region 18 is arranged so spaced from the interface 15 between the P-type region 14 and the N-type region 13 that the space charge zone 16 reaches the further region 18 before the breakdown voltage of the PN junction 1 is reached.

Due to the fact that the further region 18 according to the invention has a lower conductivity than the surrounding region 13 , the further region 18 is able, like the field rings according to the prior art, to enlarge the space charge zone 16 by the PN junction 17 when the PN junction 17 is operated in the reverse direction. By increasing the space charge region 16, the electric field is reduced in the space charge zone nerhalb sixteenth Accordingly, a larger voltage can now be applied to the PN junction 17 before an avalanche breakdown occurs.

Furthermore, by means of the further region 18 according to the invention, the location at which the avalanche breakdown occurs can be moved deeper into the semiconductor region 13 . In a conventional DMOS transistor, the avalanche breakdown often begins near the surface below the oxide layer 28 . As a rule, an avalanche breakdown does not destroy the DMOS transistor. However, the fast electrons generated during the avalanche breakdown can damage the oxide layer 28 . This has the consequence that the electrical parameters of the DMOS transistor change, which in turn has a negative effect on the integrated circuit, of which the DMOS transistor is a component. , Especially at the transition area of insulation 26 to the oxide layer 28 can easily men kom in damage to the oxide layer 28 there is formed slightly thinner in this region, the oxide layer 28 due to the so-called "white ribbon" effect .

Through the further semiconductor region 18 , the location at which the avalanche breakdown begins is moved deeper into the semiconductor region 13 . The avalanche breakdown now begins below the P-type semiconductor region 14 between the P-type semiconductor region 14 and the N-type zone 12 of high conductivity ("buried layer"). In this way, damage to the oxide layer 28 can be significantly reduced. Accordingly, the electrical parameters of the DMOS transistor remain practically unchanged even after an avalanche breakdown.

A new and cost-effective method for producing the further semiconductor region 18 is described below. FIGS. 4 and 5 show a schematic representation of egg nes inventive method.

An N-type semiconductor region 13 is arranged epitaxially above a P-type semiconductor material 10 of any orientation. This N-type semiconductor region 13 has an output doping and an output conductivity. An N-type zone 12 of high conductivity ("buried lay er") is provided between the semiconductor region 13 and the P-type semiconductor material 10 . Above the N-conductive zone 12 high conductivity (on the left side of FIG. 4), a device according to the invention, here a DMOS transistor, is provided below. On the right side of FIG. 4, CMOS transistors are produced which are used to control the DMOS transistor. To manufacture the CMOS transistors, it is necessary to implant a so-called "P-well" in the semiconductor region 13 . Due to the desired properties of the CMOS transistors, this P-well implant has a predetermined dopant flux density and doping time. By the process according to the invention described below, this P-well implantation is used to generate the further semiconductor regions 18 in the region of the later DMOS transistor.

For this purpose, a resist mask 31 is applied to the structure shown in FIG. 4. The paint mask 31 has the openings 32 and 33 . The opening 32 serves to generate the P-well, while the openings 33 serve to generate the further semiconductor region 18 . The openings 33 in the resist mask 31 are arranged so that part of the surface of the future semiconductor region 18 is covered and part of the surface of the late semiconductor region 18 is not covered. As a result, the amount of dopant that is introduced into the later semiconductor region 18 is reduced compared to the amount of dopant that is introduced into the later P-well. The ratio of the covered surface to the uncovered surface of the later semiconductor region is selected so that the desired effective dopant concentration and thus the desired reduced conductivity is generated.

The dopant is now implanted into the semiconductor region 13 through the openings 32 and 33 . A heat treatment follows, through which the dopant diffuses out and is thus activated. The heat treatment can be carried out immediately after the animal implantation or only later in the course of further process steps, for example the generation of the deep diffusion region 27 (FIGS . 3a and 3b).

The dopant flux density and doping time of the dopant implantation are selected so that in the area of the P-well 36 the dopant introduced outweighs the existing doping of the N-type semiconductor region 13 . Accordingly, a P-type well 36 is formed with a conductivity suitable for the CMOS transistors. On the side of the DMOS transistor, the ratio of the covered surface to the uncovered surface of the semiconductor region 18 is selected such that the amount of dopant introduced is insufficient to outweigh the existing doping of the N-type semiconductor region 13 . Thus, the further semiconductor region 18 is still N-type, but it has a lower conductivity than the surrounding N-type semiconductor region 13 . As a borderline case, the amount of dopant introduced can be chosen such that the amount of dopant introduced and the doping already present cancel each other out, so that a semiconductor region 18 with an intrinsic conductivity arises.

As seen from Fig. 5, the spacing of the apertures 33 is smaller than the diffusion length of the introduced into the semiconductor region 13 dopant. This creates a coherent semiconductor region 18 with a not completely homogeneous dopant distribution. In practice, however, the fluctuations in the dopant concentration are negligible.

In the following, the deep diffusion region 27 , the P-type semiconductor region 14 , the N-type semiconductor region 22 , the insulation 26 , the oxide layer 28 (“gate oxide”) and the conductive layer 29 (“gate”) are produced so that the structure shown in Figs. 3a and 3b is formed.

FIG. 6 shows a schematic top view of the mask used in FIG. 5. The mask 31 shown in FIG. 6 has an opening 32 which serves to produce the P-tub 36 . In addition, the mask 31 has openings 33 , which serve to generate the further semiconductor region 18 . The openings 33 are arranged like a checkerboard, the distance between two adjacent openings being smaller than the diffusion length of the introduced dopant.

Claims (14)

1. Semiconductor component with a P-type region ( 14 ) and an N-type region ( 13 ), which are in contact with one another along an interface ( 15 ), so that a PN junction ( 17 ) with one around this interface ( 15 ) angeordne th space charge zone ( 16 ) is formed, characterized in that in the P-type region ( 14 ) and / or in the N-type region ( 13 ) at least one further region ( 18 ) is provided which has the same conductivity type as the surrounding area and has a lower conductivity than the surrounding area or is intrinsic and which is so spaced from the interface ( 15 ) between the P-type region ( 14 ) and the N-type region ( 13 ) that when the PN junction ( 17 ) is operated in the reverse direction, the space charge zone ( 16 ) around the interface ( 15 ) reaches the further region ( 18 ) before the breakdown voltage of the PN junction ( 17 ) is reached. 2. Semiconductor component according to claim 1, characterized in that the further region ( 18 ) adjacent to the locations of the interface ( 15 ) between the P-type region ( 14 ) and the N-type region ( 13 ) is arranged, at which the boundary surface ( 15 ) has the greatest curvature. 3. Semiconductor component according to claim 1 or 2, characterized in that the further region ( 18 ) outside the space charge zone ( 16 ) is arranged when no external voltage is applied to the PN junction ( 17 ). 4. Semiconductor component according to one of claims 1 to 3, characterized in that the conductivity of the further region ( 18 ) is at least ei ne order of magnitude, preferably at least two orders of magnitude, smaller than the conductivity of the surrounding area. 5. Semiconductor component according to one of claims 1 to 4, characterized in that the P-type region ( 14 ) and the N-type region ( 13 ) are doped to different extents and that the further region ( 18 ) is arranged in the weakly doped region is. 6. Semiconductor component according to one of claims 1 to 5, characterized in that the further region ( 18 ) is arranged adjacent to the surface of the surrounding area. 7. Semiconductor component according to one of claims 1 to 6, characterized in that the further region ( 18 ) is arranged below an insulation layer ( 26 , 28 ). 8. A semiconductor device according to claim 7, characterized in that a conductive layer ( 29 ) is arranged above the insulation layer ( 26 , 28 ), the distance from the surface of the region ( 18 ) surrounding the further region was from the PN junction with increasing Ab ( 17 ) gets bigger. 9. Semiconductor component according to one of claims 1 to 8, characterized in that the further region ( 18 ) gives the PN junction ( 17 ) in a ring shape. 10. A method of producing a semiconductor region having a desired conductivity type and a desired effective dopant concentration at a predetermined dopant flux density and doping time, the method comprising the following steps:

• a) a semiconductor region is provided which has an initial doping with dopants of a first conductivity type and an initial conductivity.
• b) a mask is provided above the semiconductor region, which has a multiplicity of openings, so that part of the surface of the semiconductor region is covered and part of the surface of the semiconductor region is not covered,
• c) a dopant of a second, opposite conductivity type is introduced into the semiconductor region with the predetermined dopant flux density and in the predetermined doping time,

wherein the ratio of the covered surface to the uncovered surface of the semiconductor region is selected so that the desired effective dopant concentration is generated and a semiconductor region with a reduced conductivity compared to the output conductivity is formed. 11. The method according to claim 10, characterized in that the distances between the openings in the mask are chosen so that a coherent semiconductor region arises, the Difference between dopant concentration maximum and the Minimum dopant concentration within the semiconductor area is less than 3 orders of magnitude. 12. The method according to claim 10 or 11, characterized in that  the distances between adjacent openings in the mask less than the diffusion length of the dopant in the half leader area are selected. 13. The method according to any one of claims 10 to 12, characterized in that the openings in the mask in a checkerboard pattern are arranged. 14. The method according to any one of claims 10 to 13, characterized in that the dopant by diffusion from the gas phase or from a doping layer or by ion implantation subsequent dopant activation in the semiconductor region is introduced.