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SG10201903205RA - Method of forming a low-k layer and method of forming a semiconductor device - Google Patents

Method of forming a low-k layer and method of forming a semiconductor device

Info

Publication number
SG10201903205RA
SG10201903205RA SG10201903205RA SG10201903205RA SG 10201903205R A SG10201903205R A SG 10201903205RA SG 10201903205R A SG10201903205R A SG 10201903205RA SG 10201903205R A SG10201903205R A SG 10201903205RA
Authority
SG
Singapore
Prior art keywords
forming
providing
source
layer
low
Prior art date
Application number
Inventor
Lee Sunyoung
Kang Minjae
Kim Se-Yeon
KIM Teawon
Tak Yong-Suk
Kim Sunjung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201903205RA publication Critical patent/SG10201903205RA/en

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    • C23C16/042Coating on selected surface areas, e.g. using masks using masks
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    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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Abstract

A method of forming a low-k layer includes forming a layer by providing a silicon source, a carbon source, an oxygen source, and a nitrogen source onto a substrate. The forming of the layer includes a plurality of main cycles, and each of the main cycles includes providing the silicon source, providing the carbon source, providing the oxygen source, and providing the nitrogen source, each of which is performed at least one time. Each of the main cycles includes sub-cycles in which the providing of the carbon source and the providing of the oxygen source are alternately performed. FIG. 1
SG10201903205R 2018-04-26 2019-04-10 Method of forming a low-k layer and method of forming a semiconductor device SG10201903205RA (en)

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JP7437362B2 (en) * 2021-09-28 2024-02-22 株式会社Kokusai Electric Semiconductor device manufacturing method, substrate processing equipment, substrate processing method and program

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CN110416061B (en) 2024-04-30
JP7256675B2 (en) 2023-04-12
JP2019192907A (en) 2019-10-31
CN110416061A (en) 2019-11-05
KR20190124509A (en) 2019-11-05

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