[go: up one dir, main page]

SG10201907414TA - Mask layout, semiconductor device and manufacturing method using the same - Google Patents

Mask layout, semiconductor device and manufacturing method using the same

Info

Publication number
SG10201907414TA
SG10201907414TA SG10201907414TA SG10201907414TA SG10201907414TA SG 10201907414T A SG10201907414T A SG 10201907414TA SG 10201907414T A SG10201907414T A SG 10201907414TA SG 10201907414T A SG10201907414T A SG 10201907414TA SG 10201907414T A SG10201907414T A SG 10201907414TA
Authority
SG
Singapore
Prior art keywords
manufacturing
semiconductor device
same
mask layout
layout
Prior art date
Application number
SG10201907414TA
Inventor
Hwan Kim Guk
Original Assignee
Magnachip Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magnachip Semiconductor Ltd filed Critical Magnachip Semiconductor Ltd
Publication of SG10201907414TA publication Critical patent/SG10201907414TA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816Aspects relating to the layout of the pattern or to the size of vias or trenches
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251Source or drain electrodes for field-effect devices
    • H10D64/258Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135Manufacturing their gate conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144Manufacturing their gate insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/378Contact regions to the substrate regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
SG10201907414TA 2019-03-29 2019-08-13 Mask layout, semiconductor device and manufacturing method using the same SG10201907414TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190037441A KR102288643B1 (en) 2019-03-29 2019-03-29 Mask layout, Semiconductor Device and Manufacturing Method using the same

Publications (1)

Publication Number Publication Date
SG10201907414TA true SG10201907414TA (en) 2020-10-29

Family

ID=72608028

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201907414TA SG10201907414TA (en) 2019-03-29 2019-08-13 Mask layout, semiconductor device and manufacturing method using the same

Country Status (5)

Country Link
US (5) US11018010B2 (en)
KR (1) KR102288643B1 (en)
DE (1) DE102019131091A1 (en)
SG (1) SG10201907414TA (en)
TW (2) TWI890035B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102274813B1 (en) * 2020-02-27 2021-07-07 주식회사 키 파운드리 A Manufacturing Method of Semiconductor Device Using Gate-Through Implantation
US11222955B2 (en) * 2020-04-22 2022-01-11 Wolfspeed, Inc. Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices
CN116508135B (en) 2020-12-04 2024-06-04 安普莱西娅有限责任公司 LDMOS with self-aligned body and mixed source
US11527607B2 (en) * 2020-12-14 2022-12-13 Vanguard International Semiconductor Corporation Integrated circuits using guard rings for ESD systems
KR102260150B1 (en) 2021-01-20 2021-06-03 위더맥스(주) System of implementing spare cell logic circuit and creating layout for enhancing the efficiency of engineer change order and method thereof
CN115224022B (en) * 2021-04-15 2025-08-22 世界先进积体电路股份有限公司 semiconductor devices
TW202429716A (en) * 2023-01-06 2024-07-16 聯華電子股份有限公司 Edmos and fabricating method of the same
TWI881759B (en) * 2024-03-21 2025-04-21 華邦電子股份有限公司 Input/output driver

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US6476449B1 (en) * 2001-09-05 2002-11-05 Winbond Electronics Corp. Silicide block for ESD protection devices
JP3939205B2 (en) 2002-06-18 2007-07-04 浜松ホトニクス株式会社 Laser processing apparatus, laser processing temperature measuring apparatus, laser processing method, and laser processing temperature measuring method
JP2005109389A (en) 2003-10-02 2005-04-21 Sanyo Electric Co Ltd Semiconductor device and manufacturing method thereof
TWI368327B (en) * 2005-01-17 2012-07-11 Samsung Electronics Co Ltd Optical mask and manufacturing method of thin film transistor array panel using the optical mask
FR2893763A1 (en) * 2005-11-21 2007-05-25 St Microelectronics Sa NON-VOLATILE MEMORY ELEMENT
WO2009081867A1 (en) * 2007-12-20 2009-07-02 Asahi Kasei Emd Corporation Semiconductor device and method for manufacturing semiconductor devicedispositif à semi-conducteurrs et procédé de fabrication d'un dispositif à semi-conducteurs
KR100976793B1 (en) * 2007-12-31 2010-08-20 주식회사 동부하이텍 Manufacturing method of MOS transistor
KR100990599B1 (en) * 2008-05-30 2010-10-29 주식회사 하이닉스반도체 Method of manufacturing semiconductor device and semiconductor device manufactured accordingly
JP5465958B2 (en) * 2009-09-01 2014-04-09 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP5582030B2 (en) * 2010-12-28 2014-09-03 富士通セミコンダクター株式会社 MOS transistor and manufacturing method thereof
US20120205744A1 (en) * 2011-02-10 2012-08-16 O Kenneth K Body contact structure for a semiconductor device
JP5834520B2 (en) 2011-06-15 2015-12-24 富士通セミコンダクター株式会社 Semiconductor device manufacturing method and semiconductor device
US9293460B2 (en) * 2012-08-24 2016-03-22 Texas Instruments Incorporated ESD protection device with improved bipolar gain using cutout in the body well
KR101467703B1 (en) 2013-10-10 2014-12-02 매그나칩 반도체 유한회사 semiconductor device and manufacturing method thereof
US10276596B2 (en) * 2014-08-06 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Selective polysilicon doping for gate induced drain leakage improvement
US11164970B2 (en) * 2014-11-25 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Contact field plate
KR102378211B1 (en) * 2015-06-23 2022-03-25 삼성디스플레이 주식회사 Mask and fabrication method of display device by using the mask
US10224407B2 (en) * 2017-02-28 2019-03-05 Sandisk Technologies Llc High voltage field effect transistor with laterally extended gate dielectric and method of making thereof
CN109638010B (en) * 2017-10-09 2021-09-14 联华电子股份有限公司 Radio frequency switching device and manufacturing method thereof

Also Published As

Publication number Publication date
KR20200115951A (en) 2020-10-08
US11830740B2 (en) 2023-11-28
US20240290621A1 (en) 2024-08-29
TW202326291A (en) 2023-07-01
US12288691B2 (en) 2025-04-29
TW202036156A (en) 2020-10-01
US20210242024A1 (en) 2021-08-05
US12020939B2 (en) 2024-06-25
US20240047214A1 (en) 2024-02-08
KR102288643B1 (en) 2021-08-10
US11018010B2 (en) 2021-05-25
DE102019131091A1 (en) 2020-10-01
US20200312666A1 (en) 2020-10-01
US20230005748A1 (en) 2023-01-05
TWI890035B (en) 2025-07-11
TWI799628B (en) 2023-04-21

Similar Documents

Publication Publication Date Title
SG10201907414TA (en) Mask layout, semiconductor device and manufacturing method using the same
SG11202011370VA (en) Reflective mask blank, reflective mask and manufacturing method thereof, and semiconductor device manufacturing method
SG11202106508PA (en) Reflective mask blank, reflective mask, and method for manufacturing semiconductor device
SG10202006561WA (en) Semiconductor device and method of fabricating the same
SG10201907458SA (en) Semiconductor device and method of manufacturing the same
SG11202101338UA (en) Reflective mask blank, reflective mask and method of manufacturing the same, and method of manufacturing semiconductor device
SG11202107980SA (en) Reflective mask blank, reflective mask and method of manufacturing the same, and method of manufacturing semiconductor device
PT3339023T (en) Laminate, method for manufacturing the laminate, semiconductor device, and method for manufacturing the semiconductor device
SG11202007975QA (en) Mask blank, phase shift mask, and method for manufacturing semiconductor device
SG10202004731SA (en) Semiconductor die, semiconductor wafer, semiconductor device including the semiconductor die and method of manufacturing the semiconductor device
SG11202004856XA (en) Reflective mask blank, reflective mask and method of manufacturing the same, and method of manufacturing semiconductor device
SG10201911900YA (en) Mask blank, method for manufacturing transfer mask, and method for manufacturing semiconductor device
SG10201905840VA (en) Semiconductor device and manufacturing method thereof
SG11202109240PA (en) Reflective mask blank, reflective mask and method of manufacturing the same, and method of manufacturing semiconductor device
SG11202109059SA (en) Mask blank, method for manufacturing transfer mask, and method for manufacturing semiconductor device
SG10201911724QA (en) Vertical semiconductor device and method for fabricating the vertical semiconductor device
SG10202103395QA (en) Mask blank, method for producing transfer mask and method for producing semiconductor device
SG11202110111YA (en) Semiconductor device having dolmen structure and method for manufacturing same
SG11202102270QA (en) Mask blank, transfer mask, and method of manufacturing semiconductor device
SG11202109419WA (en) Dry etching method, method for manufacturing semiconductor device, and etching device
SG11202111780XA (en) Semiconductor device manufacturing device and manufacturing method
SG11202002544SA (en) Mask blank, transfer mask, and method for manufacturing semiconductor device
SG11202009172VA (en) Mask blank, phase shift mask, and method for manufacturing semiconductor device
SG11202110115VA (en) Mask blank, method for manufacturing transfer mask, and method for manufacturing semiconductor device
SG11201910866XA (en) Semiconductor device and manufacturing method