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SG10201805091VA - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same

Info

Publication number
SG10201805091VA
SG10201805091VA SG10201805091VA SG10201805091VA SG10201805091VA SG 10201805091V A SG10201805091V A SG 10201805091VA SG 10201805091V A SG10201805091V A SG 10201805091VA SG 10201805091V A SG10201805091V A SG 10201805091VA SG 10201805091V A SG10201805091V A SG 10201805091VA
Authority
SG
Singapore
Prior art keywords
layer
semiconductor package
manufacturing
same
pads
Prior art date
Application number
SG10201805091VA
Inventor
Son Young-Hoon
Choi Jung-Hwan
Hyun Seok-hun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201805091VA publication Critical patent/SG10201805091VA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

OF THE DISCLOSURE A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer. FIG. 1A
SG10201805091VA 2017-06-23 2018-06-14 Semiconductor package and method of manufacturing the same SG10201805091VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20170079955 2017-06-23
KR1020180008955A KR102434988B1 (en) 2017-06-23 2018-01-24 Semiconductor package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
SG10201805091VA true SG10201805091VA (en) 2019-01-30

Family

ID=65021879

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201805091VA SG10201805091VA (en) 2017-06-23 2018-06-14 Semiconductor package and method of manufacturing the same

Country Status (4)

Country Link
JP (1) JP7011981B2 (en)
KR (1) KR102434988B1 (en)
SG (1) SG10201805091VA (en)
TW (1) TWI770200B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102509052B1 (en) * 2018-08-31 2023-03-10 에스케이하이닉스 주식회사 Stack package include bridge die
JP6621951B1 (en) * 2018-12-28 2019-12-18 長瀬産業株式会社 Manufacturing method of semiconductor device
US11892665B2 (en) 2019-01-23 2024-02-06 Panasonic Intellectual Property Management Co., Ltd. Colloidal crystal structure, and light-emitting device and lighting system using same
KR20210122287A (en) 2019-05-17 2021-10-08 양쯔 메모리 테크놀로지스 씨오., 엘티디. Cache program operation in 3D memory devices using static random access memory
KR102631812B1 (en) 2019-05-17 2024-01-30 양쯔 메모리 테크놀로지스 씨오., 엘티디. Three-dimensional memory device with static random access memory
US11393794B2 (en) 2019-10-17 2022-07-19 Micron Technology, Inc. Microelectronic device assemblies and packages including surface mount components
US12199068B2 (en) 2019-10-17 2025-01-14 Micron Technology, Inc. Methods of forming microelectronic device assemblies and packages
CN112687615B (en) 2019-10-17 2025-03-07 美光科技公司 Microelectronic device assembly, package and related methods
CN112687614B (en) 2019-10-17 2024-11-26 美光科技公司 Microelectronic device assembly and package including multiple device stacks and related methods
KR20240149904A (en) * 2023-04-03 2024-10-15 양쯔 메모리 테크놀로지스 씨오., 엘티디. Integrated package device, method for manufacturing the same and memory system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3524545B2 (en) 2002-01-23 2004-05-10 松下電器産業株式会社 Manufacturing method of circuit component built-in module
JP3888267B2 (en) 2002-08-30 2007-02-28 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP2004140037A (en) 2002-10-15 2004-05-13 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
JP2005347513A (en) 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof
KR100721353B1 (en) 2005-07-08 2007-05-25 삼성전자주식회사 Structure and Manufacturing Method of Chip Insert Intermediate Substrate, Wafer Level Stacking Structure and Package Structure of Heterogeneous Chip
JP4899603B2 (en) * 2006-04-13 2012-03-21 ソニー株式会社 Three-dimensional semiconductor package manufacturing method
WO2008120755A1 (en) * 2007-03-30 2008-10-09 Nec Corporation Circuit board incorporating functional element, method for manufacturing the circuit board, and electronic device
JP5249173B2 (en) 2009-10-30 2013-07-31 新光電気工業株式会社 Semiconductor device mounting wiring board and method for manufacturing the same
US20130154106A1 (en) 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
FR2985367A1 (en) 2011-12-29 2013-07-05 3D Plus METHOD FOR THE COLLECTIVE MANUFACTURE OF 3D ELECTRONIC MODULES COMPRISING ONLY VALID PCBS
CN103650136B (en) 2012-05-10 2017-05-24 松下知识产权经营株式会社 Three-dimensional integrated circuit having stabilization structure for power supply voltage, and method for manufacturing same
KR101672622B1 (en) * 2015-02-09 2016-11-03 앰코 테크놀로지 코리아 주식회사 Semiconductor device and manufacturing method thereof
US20160329299A1 (en) * 2015-05-05 2016-11-10 Mediatek Inc. Fan-out package structure including antenna
US9905551B2 (en) * 2015-06-09 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Method of manufacturing wafer level packaging including through encapsulation vias

Also Published As

Publication number Publication date
TWI770200B (en) 2022-07-11
KR20190000775A (en) 2019-01-03
KR102434988B1 (en) 2022-08-23
JP7011981B2 (en) 2022-01-27
JP2019009444A (en) 2019-01-17
TW201906129A (en) 2019-02-01

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