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SG10201803738UA - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
SG10201803738UA
SG10201803738UA SG10201803738UA SG10201803738UA SG10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA SG 10201803738U A SG10201803738U A SG 10201803738UA
Authority
SG
Singapore
Prior art keywords
dielectric layer
pad
chip
lower dielectric
region
Prior art date
Application number
SG10201803738UA
Inventor
Han Jung-Hoon
Kim Sungjin
Noh Junyong
Lim Heonjun
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201803738UA publication Critical patent/SG10201803738UA/en

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Classifications

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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer. FIG. 5B
SG10201803738UA 2017-07-26 2018-05-03 Semiconductor device SG10201803738UA (en)

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KR20190012307A (en) 2019-02-11
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JP7017992B2 (en) 2022-02-09
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