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WO2025159778A1 - Bloc de sortie pour matrice de multiplication vectorielle par matrice - Google Patents

Bloc de sortie pour matrice de multiplication vectorielle par matrice

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Publication number
WO2025159778A1
WO2025159778A1 PCT/US2024/024091 US2024024091W WO2025159778A1 WO 2025159778 A1 WO2025159778 A1 WO 2025159778A1 US 2024024091 W US2024024091 W US 2024024091W WO 2025159778 A1 WO2025159778 A1 WO 2025159778A1
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value
output
array
vector
current
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Hieu Van Tran
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority claimed from US18/624,034 external-priority patent/US20250238479A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions

Definitions

  • Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other.
  • Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning.
  • neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network.
  • the neurons at each level individually or collectively make a decision based on the received data from the synapses.
  • One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or graphics processing unit clusters. However, in 1 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low- precision analog computation.
  • CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.
  • Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference.
  • the non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns.
  • the neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs.
  • the first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region.
  • Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate.
  • Non-Volatile Memory Cells are well known.
  • U.S. Patent 5,029,130 (“the ’130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells.
  • Such a memory cell 210 is shown in Figure 2.
  • Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between.
  • Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14.
  • Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up 2 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 and over the floating gate 20.
  • the floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide.
  • Bitline 24 is coupled to drain region 16.
  • Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. [0010] Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal).
  • SSI source side injection
  • Table No.1 Operation of Flash Memory Cell 210 of Figure 2 WL BL SL Read 2-3V 0.6-2V 0V Erase ⁇ 11-13V 0V 0V 3 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 Program 1-2V 10.5- 9-10V 3 ⁇ A [0012]
  • Other split gate memory cell configurations which are other types of flash memory cells, are known.
  • Figure 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14.
  • WL word line
  • all gates are non-floating gates except floating gate 20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.
  • Table No. 2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No.2: Operation of Flash Memory Cell 310 of Figure 3 WL/SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V Erase -0.5V/0V 0V 0V/-8V 8-12V 0V Program 1V 0.1- 8-11V 4.5-9V 4.5-5V 1 ⁇ A [0014] Figure 4 depicts a three-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is identical to the memory cell 310 of Figure 3 except that memory cell 410 does not have a separate control gate.
  • the erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the Figure 3 except there is no control gate bias applied.
  • the programming operation also is done without the control gate bias, 4 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 and as a result, a higher voltage is applied on the source line during a program operation to compensate for a lack of control gate bias. [0015] Table No.
  • FIG. 3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations: Table No.3: Operation of Flash Memory Cell 410 of Figure 4 WL/SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V Erase -0.5V/0V 0V 11.5V 0V Program 1V 0.2- 4.5V 7-9V 3 ⁇ A [0016]
  • Figure 5 depicts stacked gate memory cell 510, which is another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of Figure 2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown).
  • the erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel 18 and the drain region 16, by the electrons flowing from the source region 14 towards to drain region 16 and read operation which is similar to that for memory cell 210 with a higher control gate voltage.
  • CHE channel hot electron
  • the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below.
  • continuous (analog) programming of the memory cells is provided.
  • the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells.
  • FIG. 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present examples. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.
  • a non-volatile memory array and associated circuitry used in a neural network is one type of computation-in- memory (CIM) engine or vector-by-matrix (VMM) multiplication system.
  • CCM computation-in- memory
  • VMM vector-by-matrix
  • 6 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 [0022]
  • S0 is the input layer, which for this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G and B, each pixel being 5-bit precision).
  • the synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model).
  • 3x3 pixel overlapping filters kernel
  • values for 9 pixels in a 3x3 portion of the image i.e., referred to as a filter or kernel
  • these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1.
  • the 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse.
  • This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values).
  • the process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.
  • layer C1 in the present example, there are 16 feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships that may or may not correspond to physical relationships – i.e., the arrays may or may not be oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification.
  • the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges
  • the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.
  • An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map.
  • the purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage.
  • the synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of 1 pixel.
  • the activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map.
  • An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3.
  • Each layer of synapses is implemented using an array, or a portion of an array, of non- volatile memory cells.
  • Figure 7 is a block diagram of an array that can be used for that purpose.
  • VMM array 32 includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in Figure 6) between one layer and the next layer.
  • VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33.
  • Input to VMM array 32 can be from the erase gate and wordline gate decoder 34 or from the control gate decoder 35.
  • Source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33.
  • Non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively 8 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer.
  • the non-volatile memory cell array 33 negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.
  • the output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution.
  • the differential summer 38 is arranged to perform summation of positive weight and negative weight.
  • the summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output.
  • the activation function block 39 may provide sigmoid, tanh, or ReLU functions.
  • the rectified output values of activation function block 39 become an element of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp 38 and activation function block 39 constitute a plurality of neurons.
  • the input is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a.
  • the converted analog inputs could be voltage or current.
  • the input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM array 32a.
  • the input conversion could also be done by an analog to analog (A/A) 9 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 converter to convert an external analog input to a mapped analog input to the input VMM array 32a.
  • VMM array 32a The output generated by input VMM array 32a is provided as an input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM array (hidden level 2) 32c, and so on.
  • the various layers of VMM array 32 function as different layers of synapses and neurons of a convolutional neural network (CNN).
  • CNN convolutional neural network
  • Each VMM array 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM arrays could utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays could utilize overlapping portions of the same physical non-volatile memory array.
  • the bitline or sourceline can be used as the output for the output neuron.
  • the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.
  • Other examples for VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated by reference herein. As described in that application. a sourceline or a bitline can be used as the neuron output (current summation output).
  • VMM array 1200 comprises a memory array 1203 of non-volatile memory cells, reference array 1201 of first non-volatile reference memory cells, and reference array 1202 of second non-volatile reference memory cells.
  • Reference arrays 1201 and 1202 serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1212 (partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3.
  • reference arrays 1301 and 1302 convert input current in the terminal BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells through multiplexors 1314) to be applied to the memory cells in the row direction.
  • the current output (neuron) is in the bit lines BL0 – BLN, where each bit line sums all currents from the non- volatile memory cells connected to that particular bitline.
  • Table No. 8 depicts operating voltages and currents for VMM array 1300.
  • VMM array 2200 the inputs INPUT0. ..., INPUTN are received on bit lines BL 0 , ... BL N , respectively, and the outputs OUTPUT 1 , OUTPUT 2 , OUTPUT 3 , and OUTPUT 4 are generated on source lines SL 0 , SL 1 , SL 2 , and SL 3 , respectively.
  • Figure 23 depicts neuron VMM array 2300, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • Figure 24 depicts neuron VMM array 2400, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on word lines WL 0 , ..., WL M , respectively, and the outputs OUTPUT 0 , ...
  • FIG. 25 depicts neuron VMM array 2500, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WLM, respectively, and the outputs OUTPUT0, ... OUTPUTN are generated on bit lines BL0, ..., BLN.
  • Figure 26 depicts neuron VMM array 2600, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTn are received on vertical control gate lines CG 0 , ..., CG N , respectively, and the outputs OUTPUT 1 and OUTPUT 2 are generated on source lines SL 0 and SL 1 .
  • Figure 27 depicts neuron VMM array 2700, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT N are received on the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, respectively, which are coupled to bit lines BL0, ..., BLN, respectively.
  • Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL 0 and SL 1 .
  • Figure 28 depicts neuron VMM array 2800, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WLM, and the outputs OUTPUT0, ..., OUTPUTN are generated on bit lines BL0, ..., BL N , respectively.
  • Figure 29 depicts neuron VMM array 2900, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on control gate lines CG0, ..., CGM.
  • Outputs OUTPUT0, ..., OUTPUTN are generated on vertical source lines SL0, ..., SLN, respectively, where each source line SLi is coupled to the source lines of all memory cells in column i.
  • Figure 30 depicts neuron VMM array 3000, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on control gate lines CG0, ..., CGM.
  • Outputs OUTPUT0, ..., OUTPUTN are generated on vertical bit lines BL0, ..., BL N , respectively, where each bit line BL i is coupled to the bit lines of all memory cells in column i.
  • LSTM Long Short-Term Memory
  • LSTM units often are used in neural networks.
  • LSTM allows a neural network to remember 19 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 information over predetermined arbitrary time intervals and to use that information in subsequent operations.
  • a conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM. VMMs are particularly useful in LSTM units.
  • Figure 14 depicts an example LSTM 1400.
  • LSTM 1400 in this example comprises cells 1401, 1402, 1403, and 1404.
  • Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c0.
  • Cell 1402 receives input vector x1, the output vector (hidden state) h0 from cell 1401 , and cell state c 0 from cell 1401 and generates output vector h 1 and cell state vector c 1 .
  • Cell 1403 receives input vector x 2 , the output vector (hidden state) h 1 from cell 1402, and cell state c1 from cell 1402 and generates output vector h2 and cell state vector c2.
  • Cell 1404 receives input vector x 3 , the output vector (hidden state) h 2 from cell 1403, and cell state c 2 from cell 1403 and generates output vector h 3 .
  • FIG. 15 depicts an example implementation of an LSTM cell 1500, which can be used for cells 1401, 1402, 1403, and 1404 in Figure 14.
  • LSTM cell 1500 receives input vector x(t), cell state vector c(t-1) from a preceding cell, and output vector h(t-1) from a preceding cell and generates cell state vector c(t) and output vector h(t).
  • LSTM cell 1500 comprises sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • LSTM cell 1500 also comprises tanh devices 1504 and 1505 to apply a hyperbolic tangent function to an input vector, multiplier devices 1506, 1507, and 1508 to multiply two vectors together, and addition device 1509 to add two vectors together.
  • Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.
  • Figure 16 depicts an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader’s convenience, the same numbering from LSTM cell 1500 is used in LSTM cell 1600.
  • Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each comprise multiple VMM arrays 1601 and activation function blocks 1602.
  • VMM arrays are particular useful in LSTM cells used in certain neural network 20 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 systems.
  • the multiplier devices 1506, 1507, and 1508 and the addition device 1509 are implemented in a digital manner or in an analog manner.
  • the activation function blocks 1602 can be implemented in a digital manner or in an analog manner.
  • An alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17.
  • sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM arrays 1701 and activation function block 1702) in a time-multiplexed fashion.
  • LSTM cell 1700 also comprises multiplier device 1703 to multiply two vectors together, addition device 1708 to add two vectors together, tanh device 1505 (which comprises activation function block 1702), register 1707 to store the value i(t) when i(t) is output from sigmoid function block 1702, register 1704 to store the value f(t) * c(t-1) when that value is output from multiplier device 1703 through multiplexor 1710, register 1705 to store the value i(t) * u(t) when that value is output from multiplier device 1703 through multiplexor 1710, and register 1706 to store the value o(t) * c ⁇ (t) when that value is output from multiplier device 1703 through multiplexor 1710, and multiplexor 1709.
  • LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602
  • LSTM cell 1700 contains one set of VMM arrays 1701 and activation function block 1702, which are used to represent multiple layers in the example of LSTM cell 1700.
  • LSTM cell 1700 will require less space than LSTM 1600, as LSTM cell 1700 will require 1/4 as much space for VMMs and activation function blocks compared to LSTM cell 1600.
  • LSTM units will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks.
  • GRU gated Recurrent unit
  • FIG. 18 depicts an example GRU 1800.
  • GRU 1800 in this example comprises cells 1801, 1802, 1803, and 1804.
  • Cell 1801 receives input vector x 0 and generates output vector h 0 .
  • Cell 1802 receives input vector x1, the output vector h0 from cell 1801 and generates output vector h1.
  • Cell 1803 receives input vector x2 and the output vector (hidden state) h1 from cell 1802 and generates output vector h 2 .
  • Cell 1804 receives input vector x 3 and the output vector (hidden state) h 2 from cell 1803 and generates output vector h 3 .
  • Additional cells can be used, and an GRU with four cells is merely an example.
  • Figure 19 depicts an example implementation of a GRU cell 1900, which can be used for cells 1801, 1802, 1803, and 1804 of Figure 18.
  • GRU cell 1900 receives input vector x(t) and output vector h(t-1) from a preceding GRU cell and generates output vector h(t).
  • GRU cell 1900 comprises sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from output vector h(t-1) and input vector x(t).
  • GRU cell 1900 also comprises a tanh device 1903 to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices 1904, 1905, and 1906 to multiply two vectors together, an addition device 1907 to add two vectors together, and a complementary device 1908 to subtract an input from 1 to generate an output.
  • FIG. 20 depicts a GRU cell 2000, which is an example of an implementation of GRU cell 1900.
  • GRU cell 2000 For the reader’s convenience, the same numbering from GRU cell 1900 is used in GRU cell 2000.
  • sigmoid function devices 1901 and 1902, and tanh device 1903 each comprise multiple VMM arrays 2001 and activation function blocks 2002.
  • VMM arrays are of particular use in GRU cells used in certain neural network systems.
  • the multiplier devices 1904, 1905, 1906, the addition device 1907, and the complementary device 1908 are implemented in a digital manner or in an analog manner.
  • the activation function blocks 2002 can be implemented in a digital manner or in an analog manner.
  • GRU cell 2000 (and another example of an implementation of GRU cell 1900) is shown in Figure 21.
  • GRU cell 2100 utilizes VMM arrays 2101 and 22 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 activation function block 2102, which when configured as a sigmoid function applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM arrays 2101 and activation function block 2102) in a time-multiplexed fashion.
  • GRU cell 2100 also comprises multiplier device 2103 to multiply two vectors together, addition device 2105 to add two vectors together, complementary device 2109 to subtract an input from 1 to generate an output, multiplexor 2104, register 2106 to hold the value h(t-1) * r(t) when that value is output from multiplier device 2103 through multiplexor 2104, register 2107 to hold the value h(t-1) *z(t) when that value is output from multiplier device 2103 through multiplexor 2104, and register 2108 to hold the value h ⁇ (t) * (1-z(t)) when that value is output from multiplier device 2103 through multiplexor 2104.
  • GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002
  • GRU cell 2100 contains one set of VMM arrays 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100.
  • GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 will require 1/3 as much space for VMMs and activation function blocks compared to GRU cell 2000.
  • GRU systems will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks.
  • the input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is used to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is used to convert output analog level into digital bits).
  • each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells).
  • the two blend memory cells two memory cells are used to implement a weight W as an average of two cells.
  • Figure 31 depicts VMM system 3100.
  • W+ lines half of the bit lines are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+
  • W- lines half of the bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3101 and 3102.
  • FIG. 32 depicts another example.
  • VMM system 3210 positive weights W+ are implemented in first array 3211 and negative weights W- are implemented in a second array 3212, second array 3212 separate from the first array, and the resulting weights are appropriately combined together by summation circuits 3213.
  • Figure 33 depicts VMM system 3300.
  • VMM system 3300 comprises array 3301 and array 3302.
  • Half of the bit lines in each of array 3301 and 3302 are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines in each of array 3301 and 3302 are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line 24 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 and a W- line, such as summation circuits 3303, 3304, 3305, and 3306.
  • each W value from each array 3301 and 3302 can be further combined through summation circuits 3307 and 3308, such that each W value is the result of a W value from array 3301 minus a W value from array 3302, meaning that the end result from summation circuits 3307 and 3308 is a differential value of two differential values.
  • W+ and W- might both range between 0 to 25 ⁇ A, meaning that the difference (W+) – (W-) can range between -25 ⁇ A and +25 ⁇ A, which might correspond to a digital output of -128 to +127 for the 2’s complement format or -127 to 127 for the 1’s complement format.
  • Neural networks perform a large volume of partial summations. What is needed is an output block for receiving differential weights stored in a VMM array and operating efficiently upon the differential data.
  • a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an output block coupled to the vector-by-matrix multiplication array, the output block comprising: a current-to-voltage converter to convert current received from a column of the vector-by-matrix multiplication array into a voltage; an analog-to-digital converter to convert the voltage into digital bits; and a configuration circuit to convert the digital bits into unsigned digital bits.
  • a method comprises receiving a sequence of N current values from a vector-by-matrix multiplication array; and generating an output equal to a sum of the N current values minus N*M, where M is 2 n-1 and n is a number of bits available for the output.
  • a method comprises receiving a first received value representing a first current received from a vector-by-matrix multiplication array; adding the first received value to a first stored value to generate a first interim value; generating a signed version of the first interim value equal to a difference between the first interim value minus 2 n-1 , where n is a number of bits available for an output; and storing the signed version of the first interim value as a second stored value.
  • a method comprises receiving a first current from a vector-by-matrix multiplication array; converting the first current into a first binary digital value; and converting the first binary digital value into a first 2’s complement value.
  • a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns, wherein a first non- volatile memory cell in the array contains a first number with a positive value and a second non- volatile memory cell in the array contains a second number with a negative value; and an output block coupled to the vector-by-matrix multiplication array to generate an output when (i) the first number and the second number are signed numbers, (ii) the first number and the second number are unsigned numbers, or (iii) the first number and the second number are 2’s complement numbers, wherein the output is the first number minus the second number.
  • Figure 1 is a diagram that illustrates an artificial neural network.
  • Figure 2 depicts a prior art split gate flash memory cell.
  • Figure 3 depicts another prior art split gate flash memory cell.
  • Figure 4 depicts another prior art split gate flash memory cell.
  • Figure 5 depicts another prior art split gate flash memory cell.
  • Figure 6 is a diagram illustrating the different levels of an example artificial neural network utilizing one or more non-volatile memory arrays.
  • Figure 7 is a block diagram illustrating a VMM system.
  • Figure 8 is a block diagram illustrates an example artificial neural network utilizing one or more VMM systems.
  • Figure 9 depicts another example of a VMM system.
  • Figure 10 depicts another example of a VMM system.
  • Figure 11 depicts another example of a VMM system.
  • Figure 12 depicts another example of a VMM system.
  • Figure 13 depicts another example of a VMM system.
  • Figure 14 depicts a prior art long short-term memory system.
  • Figure 15 depicts an example cell for use in a long short-term memory system.
  • Figure 16 depicts an example implementation of the cell of Figure 15.
  • Figure 17 depicts another example implementation of the cell of Figure 15.
  • Figure 18 depicts a prior art gated recurrent unit system.
  • Figure 19 depicts an example cell for use in a gated recurrent unit system.
  • Figure 20 depicts an example implementation t of the cell of Figure 19.
  • Figure 21 depicts another example implementation of the cell of Figure 19.
  • Figure 22 depicts another example of a VMM system.
  • Figure 23 depicts another example of a VMM system.
  • Figure 24 depicts another example of a VMM system.
  • Figure 25 depicts another example of a VMM system.
  • Figure 26 depicts another example of a VMM system.
  • Figure 27 depicts another example of a VMM system.
  • Figure 28 depicts another example of a VMM system.
  • Figure 29 depicts another example of a VMM system.
  • Figure 30 depicts another example of a VMM system.
  • Figure 31 depicts another example of a VMM system.
  • Figure 32 depicts another example of a VMM system.
  • Figure 33 depicts another example of a VMM system.
  • Figure 34 depicts a VMM system.
  • Figure 35A depicts an output block coupled to a VMM array.
  • Figure 35B depicts an example of an accumulator circuit.
  • Figure 36 depicts an output block coupled to a VMM array.
  • Figure 37 depicts an unsigned data mapping.
  • Figure 38 depicts a signed data mapping.
  • Figure 39 depicts an output generation method.
  • Figure 40 depicts an output generation method.
  • Figure 41 depicts an output generation method.
  • Figure 42 depicts an output generation method.
  • DETAILED DESCRIPTION OF THE INVENTION [00138]
  • Figure 34 depicts a block diagram of a VMM system 3400.
  • VMM system 3400 comprises VMM array 3401, row decoder 3402, high voltage decoder 3403, column decoders 3404, bit line drivers 3405, input circuit 3406, output circuit 3407, control logic 3408, and bias generator 3409.
  • VMM system 3400 further comprises high voltage generation block 3410, which comprises charge pump 3411, charge pump regulator 3412, and high voltage analog precision level generator 3413.
  • VMM system 3400 further comprises (program/erase, or weight tuning) algorithm controller 3414, analog circuitry 3415, control engine 3416 (that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), and test control logic 3417.
  • VMM array 3401 comprises non-volatile memory cells arranged into rows and columns.
  • the non-volatile memory cells can be split-gate flash memory cells such as of the type shown in Figures 2, 3, and 4 as memory cells 210, 310, 410, respectively, stacked-gate flash memory cells such as of the type shown in Figure 5 as memory cell 510, or another type of non-volatile memory cell.
  • the input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters.
  • the input circuit 3406 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions.
  • the input circuit 3406 may implement a temperature compensation function for input levels.
  • the input circuit 3406 may implement an activation function such as ReLU or sigmoid. 28 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 [00140]
  • the output circuit 3407 may include circuits such as an ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters.
  • the output circuit 3407 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid.
  • the output circuit 3407 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs.
  • the output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.
  • Figure 35A depicts output block 3500 coupled to VMM array 3401. As discussed above, each cell in VMM array 3401 can store a value.
  • Output block 3500 comprises a plurality of column circuits such as column circuit 3501.
  • each column in VMM array 3401 is coupled to a respective column circuit of the same structure as column circuit 3501.
  • Column circuit 3501 comprises column multiplexor 3502 (which may be a portion of a larger multiplexor along with other column multiplexors for one or more other columns), current-to-voltage converter 3503, analog- to-digital converter 3504, configuration circuit 3505, and accumulator circuit 3506.
  • column multiplexor 3502 receives current from a respective column in VMM array 3401 and routes it to current-to-voltage converter 3503, which converts the column current into a voltage.
  • Configuration circuit 3505 receives the digital value from the analog-to-digital converter 3504 and performs certain operations on the digital value to create a new digital value. For example, configuration circuit 3505 can generate either signed data or unsigned data and either binary data or 2’s complement data. Accumulator circuit 3506 performs summation and accumulation of the new digital value and a stored digital value, if one is present, and optionally performs a function on the data such as a sigmoid, tanh, or ReLU function.
  • the stored digital 29 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 value can be a digital value received from the same column during a previous operation (such as when inputs are applied to VMM array in a time-multiplexed fashion) or a digital value received from another column in VMM array during the same operation (which might be the case if accumulator circuit 3506 is shared by multiple columns). Data can be transferred between configuration circuit 3505 and accumulator 3506 numerous times as dictated by the operation. The output of output block 3500 is ultimately provided by configuration circuit 3505 or accumulator circuit 3506.
  • shifter 3551 which performs a shift function in response to the control signal EN_SHIFT provided by control engine 3416 in Figure 34 or another controller.
  • shifter 3551 can be used during a serial input mode in which one bit of a multi-bit activation input is applied to VMM array 3401 in Figure 35A during one read at a time and where EN_SHIFT is incremented for each bit.
  • the LSB (least significant bit) of the input bits is not shifted by shifter 3551, and is therefore provided to adder 3552 in the LSB position
  • the (LSB+1) input bit is shifted by shifter 3551 by 1-bit shift left, and is therefore provided to adder 3552 in the LSB+1 position
  • the (LSB+2) input bit is shifted by shifter 3551 by 2-bit shifts left, and is therefore provided to adder 3552 in the LSB+2 position, and so on, and where this shift operation is performed 8 times for an 8-bit activation input.
  • the output of shifter 3551, D1 is provided to adder 3552, which adds D1 to D2, which D2 is received from the output of accumulator register 3553, described below.
  • Adder 3552 is enabled by the control signal EN_ADD provided by control engine 3416 in Figure 34 or another controller.
  • the output of adder 3552 is provided to accumulator register 3553, which stores the output of adder 3552 and provides it back to adder 3552 as D2 for the next add operation, as described above.
  • ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 manner, the output of ADC 3504 or configuration circuit 3505can be added over a time period.
  • adder 3552 thus adds each the output components for the entire 8-bit activation input, with bits in the proper position due to the operations performed by shifter 3551.
  • a final output, DOUT is output from accumulator register 3553.
  • DOUT can be signed binary data, unsigned binary data, or 2’s complement data.
  • DOUT can be provided back to configuration circuit 3505 if additional operations are required.
  • Figure 36 depicts output block 3600 coupled to VMM array 3401.
  • Output block 3600 is an alternative to output block 3500 in Figure 35A.
  • Output block 3600 comprises a plurality of column circuits such as column circuit 3601.
  • each column in VMM array 3401 is coupled to a column circuit of the same structure as column circuit 3601.
  • Column circuit 3601 comprises column multiplexor 3602 (which may be a portion of a larger multiplexor along with other column multiplexors for one or more other columns), current-to-voltage converter 3603, analog-to-digital converter (ADC) 3604, and configuration circuit 3605.
  • column multiplexor 3602 receives current from a respective column in VMM array 3401 and routes it to current-to-voltage converter 3603, which converts the column current into a voltage.
  • the voltage output by current-to-voltage converter 3603, which is an analog voltage is received by analog-to-digital converter 3604, which converts the received analog voltage into a digital value.
  • the current from VMM array or the 31 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 difference in currents received from two columns can range between -25 ⁇ A and +25 ⁇ A.
  • Configuration circuits 3505 and 3605 map the received current or difference in current to a digital value using a look-up table or other mechanism. In this example, the digital value ranges between the binary equivalent of 0 and 255.
  • a digital value between 0-127 represents an actual negative number between -128 to -1 (corresponding to -25uA to 0-) and a digital value between 128-255 represents an actual positive number between 0 and 127 (corresponding to 0+ to 25uA).
  • Figure 38 depicts signed data mapping 3800, which shows an example of how configuration circuits 3505 and 3605 can generate signed digital data in response to the current received from VMM array 3401 or the difference in current received from two columns. In the example, shown, the current from VMM array or the difference in current can range between -25 ⁇ A and +25 ⁇ A.
  • Configuration circuits 3505 and 3605 map the received current to a digital value using a look-up table or other mechanism.
  • Figure 39 depicts output generation method 3900 performed by configuration circuit 3505 and accumulator circuit 3506 in Figure 35A to sum a plurality of values (such as values received over time from the same column or values received from different columns in the same array or different arrays) and to generate an unsigned output and optionally a signed output.
  • the system determines if all DOUTn values have been received and incorporated into the sum or if more are to be received and added (3903), by comparing the counter N to a maximum value. If no, then the method returns to operation 3901 and N is incremented. If yes, then the current version of DOUTu is the final result in unsigned form.
  • Operation 3903 can be performed, by example, by control engine 3416 in Figure 34 keeping track of the operations to be performed, and thereby controlling signals EN_SHIFT, EN_ADD and EN_STORE of Figure 35B.
  • Operations 3901 and 3904 can be performed by configuration circuit 3505 or operation 3902 can be performed by accumulator circuit 3506.
  • Figure 40 depicts output generation method 4000 performed by configuration circuits 3505 and 3605 in Figure 35A to sum a plurality of values (such as values received over time from the same column or values received from different columns in the same array or different arrays) using a 2’s complement format.
  • the configuration circuit 3505 converts an output, DOUTn, received from ADC 3504 or 3604 from binary form into 2’s complement form (4001).
  • the output DOUT from the ADC 3504 or 3604 is converted to 2’s complement form as follows:
  • FIG. 41 depicts method 4100 performed by configuration circuit 3505 and accumulator circuit 3506 in Figure 35A.
  • Method 4100 comprises: receiving a first received 33 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 value representing a first current received from a vector-by-matrix multiplication array (4101), e.g., receiving a digital value representation of the current after conversion to a voltage and conversion to a digital value by an ADC; adding the first received value to a first stored value to generate a first interim value (4102); generating a signed version of the first interim value equal to a difference between the first interim value minus 2 n-1 , where n is a number of bits available for an output (4103); storing the signed version of the first interim value as a second stored value (4104); if all input currents have been received, generating an output equal to the second stored value (4105); if all input currents have not been received, receiving a second received value representing a second current received from the vector-by-matrix multiplication array (4106) ,e.g., receiving a digital value representation of the current after conversion to
  • Figure 42 depicts method 4200 performed by configuration circuit 3505 and accumulator circuit 3506 in Figure 35A.
  • Method 4200 comprises: receiving a first current from a vector-by-matrix multiplication array (4201); converting the first current into a first binary digital value (4202), e.g., by converting the received first current to a voltage representing the receive first current and conversion of the voltage to a digital value by an ADC; converting the first binary digital value into a first 2’s complement value (4203), which optionally can comprise inverting the most significant bit of the first binary digital value to generate the first 2’s complement value; adding a first stored value to the first 2’s complement value to generate a first interim value (4204); storing the first interim value as a second stored value (4205); if all input current have been received, converting the second stored value from its 2’s complement value into binary form to generate an output (4206); if all input currents have not been received, receiving a second current from the vector-by-matrix multiplication array (4207); converting the 34 ACTIVE ⁇ 1608725686.1 Attorney Docket Number: 351913-980792 second
  • adjacent includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between)
  • mounted to includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between)
  • electrically coupled includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between. 35 ACTIVE ⁇ 1608725686.1

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Abstract

Dans un exemple, un système comprend : un réseau de multiplication vectorielle par matrice comprenant des cellules de mémoire non volatile agencées en rangées et en colonnes; et un bloc de sortie couplé au réseau de multiplication vectorielle par matrice comprenant : un convertisseur courant-tension destiné à convertir le courant reçu d'une colonne du réseau de multiplication vectorielle par matrice en une tension, un convertisseur analogique-numérique destiné à convertir la tension en bits numériques, et un circuit de configuration destiné à convertir les bits numériques en bits numériques non signés.
PCT/US2024/024091 2024-01-23 2024-04-11 Bloc de sortie pour matrice de multiplication vectorielle par matrice Pending WO2025159778A1 (fr)

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