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WO2024215350A1 - Moteur de calcul en mémoire analogique et moteur de calcul en mémoire numérique pour mettre en œuvre des opérations dans un réseau neuronal - Google Patents

Moteur de calcul en mémoire analogique et moteur de calcul en mémoire numérique pour mettre en œuvre des opérations dans un réseau neuronal Download PDF

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WO2024215350A1
WO2024215350A1 PCT/US2023/027757 US2023027757W WO2024215350A1 WO 2024215350 A1 WO2024215350 A1 WO 2024215350A1 US 2023027757 W US2023027757 W US 2023027757W WO 2024215350 A1 WO2024215350 A1 WO 2024215350A1
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digital
memory
engine
layer
computation
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Hieu Van Tran
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority claimed from US18/218,368 external-priority patent/US20240338177A1/en
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Priority to CN202380096489.4A priority Critical patent/CN120937080A/zh
Priority to KR1020257026616A priority patent/KR20250134117A/ko
Priority to TW113111113A priority patent/TW202445421A/zh
Publication of WO2024215350A1 publication Critical patent/WO2024215350A1/fr
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS

Definitions

  • Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons.
  • the connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience.
  • neural networks include a layer of multiple inputs.
  • the neurons at each level individually or collectively make a decision based on the received data from the synapses.
  • One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology.
  • the non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns.
  • the neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs.
  • the first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region.
  • Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate.
  • the plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs.
  • Non-Volatile Memory Cells are well known. For example, U.S.
  • Patent 5,029,130 (“the ’130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between. Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 2 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 18, and over a portion of the source region 14.
  • Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up and over the floating gate 20.
  • the floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide.
  • Bitline 24 is coupled to drain region 16.
  • Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal).
  • SSI source side injection
  • the floating gate 20 is positively charged (i.e., erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
  • Table No.1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations: Table No.1: Operation of Flash Memory Cell 210 of Figure 2 WL BL SL 3 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 Read 2-3V 0.6-2V 0V Erase ⁇ 11-13V 0V 0V Program 1-2V 10.5- 9-10V 3 ⁇ A
  • Other split gate memory cell configurations, which are other types of flash memory cells, are known.
  • Figure 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14.
  • WL word line
  • all gates are non-floating gates except floating gate 20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.
  • Table No.2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No.2: Operation of Flash Memory Cell 310 of Figure 3 WL/SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V Erase -0.5V/0V 0V 0V/-8V 8-12V 0V Program 1V 0.1- 8-11V 4.5-9V 4.5-5V 1 ⁇ A
  • Figure 4 depicts a three-gate memory cell 410, which is another type of flash memory cell.
  • Memory cell 410 is identical to the memory cell 310 of Figure 3 except that memory cell 4 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 410 does not have a separate control gate.
  • the erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the Figure 3 except there is no control gate bias applied.
  • the programming operation also is done without the control gate bias, and as a result, a higher voltage is applied on the source line during a program operation to compensate for a lack of control gate bias.
  • Table No.3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations: Table No.3: Operation of Flash Memory Cell 410 of Figure 4 WL/SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V Erase -0.5V/0V 0V 11.5V 0V Program 1V 0.2- 4.5V 7-9V 3 ⁇ A
  • Figure 5 depicts stacked gate memory cell 510, which is another type of flash memory cell.
  • Memory cell 510 is similar to memory cell 210 of Figure 2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown).
  • the erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel 18 and the drain region 16, by the electrons flowing from the source region 14 towards to drain region 16 and read operation which is similar to that for memory cell 210 with a higher control gate voltage.
  • CHE channel hot electron
  • Table No.4 depicts typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and program operations: Table No.4: Operation of Flash Memory Cell 510 of Figure 5 C G BL SL Substrate 5 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 Read 2-5V 0.6 – 2V 0V 0V Erase -8 to -10V/0V FLT FLT 8-10V / 15-20V Program 8-12V 3-5V 0V 0V The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide- silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (m
  • the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below.
  • continuous (analog) programming of the memory cells is provided. Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells.
  • FIG. 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present examples. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.
  • a non-volatile 6 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 memory array and associated circuitry used in a neural network is one type of computation-in- memory (CIM) engine or vector-by-matrix (VMM) multiplication system.
  • S0 is the input layer, which for this example is a 32x32 pixel RGB image with 5 bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being 5 bit precision).
  • the synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model).
  • 3x3 pixel overlapping filters kernel
  • values for 9 pixels in a 3x3 portion of the image i.e., referred to as a filter or kernel
  • these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1.
  • the 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse.
  • This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values).
  • the process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.
  • layer C1 in the present example, there are 16 feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships – i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification.
  • the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges
  • the second map (generated 7 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.
  • An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map.
  • the purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage.
  • the synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of 1 pixel.
  • the activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map.
  • An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3.
  • the synapses CB4 going from layer C3 to the output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 is connected to every neuron in layer S3.
  • the output at S3 includes 10 neurons, where the highest output neuron determines the class. This output could, for example, be indicative of an identification or classification of the contents of the original image.
  • Each layer of synapses is implemented using an array, or a portion of an array, of non- volatile memory cells.
  • Figure 7 is a block diagram of an array that can be used for that purpose.
  • VMM array 32 includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in Figure 6) between one layer and the next layer.
  • VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33.
  • Input to VMM array 32 can be from the erase gate and wordline gate decoder 34 or from the control gate decoder 35.
  • Source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33.
  • bit line decoder 36 can decode the output of the non- volatile memory cell array 33.
  • Bit line decoder 36 can decode the output of the non- volatile memory cell array 33.
  • Bit line decoder 36 can decode the output of the non- volatile memory cell array 33.
  • 8 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682
  • Non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer.
  • the non-volatile memory cell array 33 negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.
  • the output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution.
  • the differential summer 38 is arranged to perform summation of positive weight and negative weight.
  • the summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output.
  • the activation function block 39 may provide sigmoid, tanh, or ReLU functions.
  • non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp 38 and activation function block 39 constitute a plurality of neurons.
  • the input to VMM array 32 in Figure 7 can be analog level, binary level, or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).
  • Figure 8 is a block diagram depicting the usage of numerous layers of VMM arrays 32, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a.
  • the converted analog inputs could be voltage or current.
  • the input D/A conversion for the first layer could be done by using a function or a LUT (look up 9 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM array 32a.
  • the input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM array 32a.
  • A/A analog to analog converter to convert an external analog input to a mapped analog input to the input VMM array 32a.
  • the output generated by input VMM array 32a is provided as an input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM array (hidden level 2) 32c, and so on.
  • VMM array 32 function as different layers of synapses and neurons of a convolutional neural network (CNN).
  • Each VMM array 32a, 32b, 32c, 32d, and 32e can be a stand-alone, physical non-volatile memory array, or multiple VMM arrays could utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays could utilize overlapping portions of the same physical non-volatile memory array.
  • the example shown in Figure 8 contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e).
  • VMM array 900 depicts neuron VMM array 900, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 900 comprises memory array 901 of non-volatile memory cells and reference array 902 (at the top of the array) of non-volatile reference memory cells. Alternatively, another reference array can be placed at the bottom.
  • control gate lines such as control gate line 903, run in a vertical direction (hence reference array 902 in the row direction is orthogonal to control gate line 903)
  • erase gate lines such as erase gate line 904, run in a horizontal direction.
  • the inputs to VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array 900 emerges on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used.
  • each source line 10 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line.
  • the non-volatile memory cells of VMM array 900 i.e., the memory cells 310 of VMM array 900, may be configured to operate in a sub- threshold region.
  • Vg n*Vt*log [Ids/wp*Io] where, wp is w of a reference or peripheral memory cell.
  • wa w of each memory cell in the memory array.
  • Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell.
  • the threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias voltage, denoted Vsb, can be 11 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 modulated to compensate for various conditions, on such temperature.
  • a wordline or control gate can be used as the input for the memory cell for the input voltage.
  • a wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region.
  • the bitline or sourceline can be used as the output for the memory cell.
  • a memory cell such as a reference memory cell or a peripheral memory cell
  • a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage.
  • a wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region.
  • the bitline or sourceline can be used as the output for the output neuron.
  • the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.
  • 12 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682
  • Other examples for VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated by reference herein.
  • a sourceline or a bitline can be used as the neuron output (current summation output).
  • Figure 10 depicts neuron VMM array 1000, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses between an input layer and the next layer.
  • VMM array 1000 comprises a memory array 1003 of non-volatile memory cells, reference array 1001 of first non-volatile reference memory cells, and reference array 1002 of second non- volatile reference memory cells.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1014 (only partially depicted) with current inputs flowing into them.
  • the reference cells are tuned (e.g., programmed) to target reference levels.
  • the target reference levels are provided by a reference mini-array matrix (not shown).
  • Memory array 1003 serves two purposes. First, it stores the weights that will be used by the VMM array 1000 on respective memory cells thereof. Second, memory array 1003 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0 - BLN), which will be the input to the next layer or input to the final layer.
  • inputs i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3
  • memory array 1003 negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0 - BLN during a read (inference) operation.
  • the current placed on each of the bit lines BL0 - BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.
  • Table No.5 depicts operating voltages and currents for VMM array 1000.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected 13 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM Array 1000 of Figure 10 WL WL -unsel BL BL -unsel SL SL -unsel Read 1-3.5V -0.5V/0V 0.6-2V (Ineuron) 0.6V-2V/0V 0V 0V Erase ⁇ 5-13V 0V 0V 0V 0V 0V Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT
  • Figure 11 depicts neuron VMM array 1100, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 1100 comprises a memory array 1103 of non-volatile memory cells, reference array 1101 of first non-volatile reference memory cells, and reference array 1102 of second non-volatile reference memory cells. Reference arrays 1101 and 1102 run in row direction of the VMM array 1100.
  • VMM array is similar to VMM 1000 except that in VMM array 1100, the word lines run in the vertical direction.
  • the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation.
  • the current placed on each source line performs a summing function of all the currents from the memory cells connected to that particular source line.
  • Table No.6 depicts operating voltages and currents for VMM array 1100.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM Array 1100 of Figure 11 WL WL -unsel BL BL -unsel SL SL -unsel ⁇ 0.3-1V Read 1-3.5V -0.5V/0V 0.6-2V 0.6V-2V/0V (Ineuron) 0V SL-inhibit ( ⁇ 4- Erase ⁇ 5-13V 0V 0V 0V 0V 8V) Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT
  • Figure 12 depicts neuron VMM array 1200, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 1200 comprises a memory array 1203 of non-volatile memory cells, reference array 1201 of first non-volatile reference memory cells, and reference array 1202 of second non-volatile reference memory cells.
  • Reference arrays 1201 and 1202 serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1212 (only partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3.
  • Multiplexors 1212 each include a respective multiplexor 1205 and a cascoding transistor 1204 to ensure a constant voltage on the bitline (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation.
  • the reference cells are tuned to target reference levels.
  • Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200.
  • memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays 1201 and 1202 convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 – BLN, and will be the input to the next layer or input to the final layer.
  • the 15 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 memory array negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • VMM array 1200 implements uni-directional tuning for non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased, and the sequence of partial programming operations starts over.
  • Table No.7 depicts operating voltages and currents for VMM array 1200.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, reference array 1301 or first non-volatile reference memory cells, and reference array 1302 of second non-volatile reference memory cells.
  • EG lines EGR0, EG0, EG1 and EGR1 are run vertically while CG lines CG0, CG1, CG2 and CG3 and SL lines WL0, WL1, WL2 and WL3 are run horizontally.
  • VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate EG lines.
  • reference arrays 1301 and 1302 convert input current in the terminal BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells through multiplexors 1314) to be applied to the memory cells in the row direction.
  • the current output (neuron) is in the bit lines BL0 – BLN, where each bit line sums all currents from the non- volatile memory cells connected to that particular bitline.
  • Table No.8 depicts operating voltages and currents for VMM array 1300.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM Array 1300 of Figure 13 CG -unsel WL - BL - same CG - EG - SL - WL unsel BL unsel CG sector unsel EG unsel SL unsel 17 ACTIVE ⁇ 302955060.6
  • Attorney Docket Number: 351913-980682 -0.5V/ 0.6-2V Read 1.0-2V 0V (Ineuron) 0V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0V 0V Erase 0V 0V 0V 0V 0V 4-9V 0-2.6V 5-12V 0-2.6V 0V 0V -0.5V/ Vinh 4.5- Program 0.7-1V 0V 0.1-1uA (1-2V) 4-11V 0-2.6V 0-2.6V 4.5-5V 0-2.6V 5V 0-1V
  • Figure 22 depicts neuron VMM array 2200, which is particularly suited for memory cells 210 as
  • VMM array 2200 the inputs INPUT0. ..., INPUTN are received on bit lines BL 0 , ... BL N , respectively, and the outputs OUTPUT 1 , OUTPUT 2 , OUTPUT 3 , and OUTPUT 4 are generated on source lines SL 0 , SL 1 , SL 2 , and SL 3 , respectively.
  • Figure 23 depicts neuron VMM array 2300, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, INPUT 1, INPUT 2, and INPUT 3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and the outputs OUTPUT0, ... OUTPUTN are generated on bit lines BL0, ..., BLN.
  • Figure 24 depicts neuron VMM array 2400, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on word lines WL 0 , ..., WL M , respectively, and the outputs OUTPUT 0 , ...
  • FIG. 25 depicts neuron VMM array 2500, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WLM, respectively, and the outputs OUTPUT0, ... OUTPUTN are generated on bit lines BL0, ..., BLN.
  • Figure 26 depicts neuron VMM array 2600, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • FIG. 27 depicts neuron VMM array 2700, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTN are received on the gates of bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, respectively, which are coupled to bit lines BL0, ..., BLN, respectively.
  • Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.
  • Figure 28 depicts neuron VMM array 2800, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL 0 , ..., WL M , and the outputs OUTPUT 0, ..., OUTPUT N are generated on bit lines BL 0 , ..., BLN, respectively.
  • Figure 29 depicts neuron VMM array 2900, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on control gate lines CG 0 , ..., CG M .
  • Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical source lines SL 0 , ..., SL N , respectively, where each source line SL i is coupled to the source lines of all memory cells in column i.
  • Figure 30 depicts neuron VMM array 3000, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on control gate lines CG 0 , ..., CG M .
  • Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical bit lines BL 0 , ..., BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in column i.
  • 19 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 Long Short-Term Memory
  • the prior art includes a concept referred to as long short-term memory (LSTM).
  • LSTM units often are used in neural networks. LSTM allows a neural network to remember information over predetermined arbitrary time intervals and to use that information in subsequent operations.
  • a conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate.
  • FIG. 14 depicts an example LSTM 1400.
  • LSTM 1400 in this example comprises cells 1401, 1402, 1403, and 1404.
  • Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c 0 .
  • Cell 1402 receives input vector x 1 , the output vector (hidden state) h 0 from cell 1401 , and cell state c 0 from cell 1401 and generates output vector h 1 and cell state vector c1.
  • Cell 1403 receives input vector x2, the output vector (hidden state) h1 from cell 1402, and cell state c 1 from cell 1402 and generates output vector h 2 and cell state vector c 2 .
  • Cell 1404 receives input vector x 3 , the output vector (hidden state) h 2 from cell 1403, and cell state c 2 from cell 1403 and generates output vector h3. Additional cells can be used, and an LSTM with four cells is merely an example.
  • Figure 15 depicts an example implementation of an LSTM cell 1500, which can be used for cells 1401, 1402, 1403, and 1404 in Figure 14.
  • LSTM cell 1500 receives input vector x(t), cell state vector c(t-1) from a preceding cell, and output vector h(t-1) from a preceding cell, and generates cell state vector c(t) and output vector h(t).
  • LSTM cell 1500 comprises sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • LSTM cell 1500 also comprises tanh devices 1504 and 1505 to apply a hyperbolic tangent function to an input vector, multiplier devices 1506, 1507, and 1508 to multiply two vectors together, and addition device 1509 to add two vectors together.
  • Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.
  • 20 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682
  • Figure 16 depicts an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader’s convenience, the same numbering from LSTM cell 1500 is used in LSTM cell 1600.
  • Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each comprise multiple VMM arrays 1601 and activation function blocks 1602. Thus, it can be seen that VMM arrays are particular useful in LSTM cells used in certain neural network systems.
  • the multiplier devices 1506, 1507, and 1508 and the addition device 1509 are implemented in a digital manner or in an analog manner.
  • the activation function blocks 1602 can be implemented in a digital manner or in an analog manner.
  • An alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17.
  • sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM arrays 1701 and activation function block 1702) in a time-multiplexed fashion.
  • LSTM cell 1700 also comprises multiplier device 1703 to multiply two vectors together, addition device 1708 to add two vectors together, tanh device 1505 (which comprises activation function block 1702), register 1707 to store the value i(t) when i(t) is output from sigmoid function block 1702, register 1704 to store the value f(t) * c(t-1) when that value is output from multiplier device 1703 through multiplexor 1710, register 1705 to store the value i(t) * u(t) when that value is output from multiplier device 1703 through multiplexor 1710, and register 1706 to store the value o(t) * c ⁇ (t) when that value is output from multiplier device 1703 through multiplexor 1710, and multiplexor 1709.
  • LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602
  • LSTM cell 1700 contains one set of VMM arrays 1701 and activation function block 1702, which are used to represent multiple layers in the example of LSTM cell 1700.
  • LSTM cell 1700 will require less space than LSTM 1600, as LSTM cell 1700 will require 1/4 as much space for VMMs and activation function blocks compared to LSTM cell 1600.
  • LSTM units will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks.
  • Gated Recurrent Units An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell. Figure 18 depicts an example GRU 1800. GRU 1800 in this example comprises cells 1801, 1802, 1803, and 1804.
  • Cell 1801 receives input vector x 0 and generates output vector h 0 .
  • Cell 1802 receives input vector x 1 , the output vector h 0 from cell 1801 and generates output vector h1.
  • Cell 1803 receives input vector x2 and the output vector (hidden state) h1 from cell 1802 and generates output vector h 2 .
  • Cell 1804 receives input vector x 3 and the output vector (hidden state) h 2 from cell 1803 and generates output vector h 3 .
  • Additional cells can be used, and an GRU with four cells is merely an example.
  • Figure 19 depicts an example implementation of a GRU cell 1900, which can be used for cells 1801, 1802, 1803, and 1804 of Figure 18.
  • GRU cell 1900 receives input vector x(t) and output vector h(t-1) from a preceding GRU cell and generates output vector h(t).
  • GRU cell 1900 comprises sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from output vector h(t-1) and input vector x(t).
  • GRU cell 1900 also comprises a tanh device 1903 to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices 1904, 1905, and 1906 to multiply two vectors together, an addition device 1907 to add two vectors together, and a complementary device 1908 to subtract an input from 1 to generate an output.
  • Figure 20 depicts a GRU cell 2000, which is an example of an implementation of GRU cell 1900.
  • GRU cell 1900 For the reader’s convenience, the same numbering from GRU cell 1900 is used in GRU cell 2000.
  • sigmoid function devices 1901 and 1902, and tanh device 1903 each comprise multiple VMM arrays 2001 and activation function blocks 2002.
  • VMM arrays are of particular use in GRU cells used in certain neural network systems.
  • the multiplier devices 1904, 1905, 1906, the addition device 1907, and the 22 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 complementary device 1908 are implemented in a digital manner or in an analog manner.
  • the activation function blocks 2002 can be implemented in a digital manner or in an analog manner.
  • GRU cell 2000 and another example of an implementation of GRU cell 1900
  • GRU cell 2100 utilizes VMM arrays 2101 and activation function block 2102, which when configured as a sigmoid function applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM arrays 2101 and activation function block 2102) in a time-multiplexed fashion.
  • GRU cell 2100 also comprises multiplier device 2103 to multiply two vectors together, addition device 2105 to add two vectors together, complementary device 2109 to subtract an input from 1 to generate an output, multiplexor 2104, register 2106 to hold the value h(t-1) * r(t) when that value is output from multiplier device 2103 through multiplexor 2104, register 2107 to hold the value h(t-1) *z(t) when that value is output from multiplier device 2103 through multiplexor 2104, and register 2108 to hold the value h ⁇ (t) * (1-z(t)) when that value is output from multiplier device 2103 through multiplexor 2104.
  • GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002
  • GRU cell 2100 contains one set of VMM arrays 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100.
  • GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 will require 1/3 as much space for VMMs and activation function blocks compared to GRU cell 2000.
  • GRU systems will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient.
  • the examples described below therefore reduce the circuitry provided outside of the VMM arrays themselves.
  • the input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is used to convert digital bits to appropriate 23 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is used to convert output analog level into digital bits).
  • each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells).
  • two memory cells are used to implement a weight W as an average of two cells.
  • Figure 31 depicts VMM system 3100.
  • bit lines are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+
  • W- lines that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3101 and 3102.
  • FIG. 32 depicts another example.
  • VMM system 3210 positive weights W+ are implemented in first array 3211 and negative weights W- are implemented in a second array 3212, second array 3212 separate from the first array, and the resulting weights are appropriately combined together by summation circuits 3213.
  • Figure 33 depicts VMM system 3300.
  • VMM system 3300 comprises array 3301 and array 3302.
  • Half of the bit lines in each of array 3301 and 3302 are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines in each of array 3301 and 3302 are 24 ACTIVE ⁇ 302955060.6
  • Attorney Docket Number: 351913-980682 designated as W- lines that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3303, 3304, 3305, and 3306.
  • the W values from each array 3301 and 3302 can be further combined through summation circuits 3307 and 3308, such that each W value is the result of a W value from array 3301 minus a W value from array 3302, meaning that the end result from summation circuits 3307 and 3308 is a differential value of two differential values.
  • Each non-volatile memory cells used in the analog neural memory system can be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate.
  • Each floating gate can hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.
  • RESNET residual neural network
  • SUMMARY OF THE INVENTION Numerous examples are disclosed of a neural network comprising one or more analog computation-in-memory engines and one or more digital computation-in-memory engines. This 25 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 allows a digital CIM engine to be used in situations where a layer contains binary weights and not analog weights.
  • Figure 1 is a diagram that illustrates an artificial neural network.
  • Figure 2 depicts a prior art split gate flash memory cell.
  • Figure 3 depicts another prior art split gate flash memory cell.
  • Figure 4 depicts another prior art split gate flash memory cell.
  • Figure 5 depicts another prior art split gate flash memory cell.
  • Figure 6 is a diagram illustrating the different levels of an example artificial neural network utilizing one or more non-volatile memory arrays.
  • Figure 7 is a block diagram illustrating a VMM system.
  • Figure 8 is a block diagram illustrates an example artificial neural network utilizing one or more VMM systems.
  • Figure 9 depicts another example of a VMM system.
  • Figure 10 depicts another example of a VMM system.
  • Figure 11 depicts another example of a VMM system.
  • Figure 12 depicts another example of a VMM system.
  • Figure 13 depicts another example of a VMM system.
  • Figure 14 depicts a prior art long short-term memory system.
  • Figure 15 depicts an example cell for use in a long short-term memory system.
  • Figure 16 depicts an example implementation of the cell of Figure 15.
  • Figure 17 depicts another example implementation of the cell of Figure 15.
  • Figure 18 depicts a prior art gated recurrent unit system.
  • Figure 19 depicts an example cell for use in a gated recurrent unit system.
  • Figure 20 depicts an example implementation t of the cell of Figure 19.
  • Figure 21 depicts another example implementation of the cell of Figure 19.
  • Figure 22 depicts another example of a VMM system.
  • Figure 23 depicts another example of a VMM system.
  • Figure 24 depicts another example of a VMM system.
  • Figure 25 depicts another example of a VMM system.
  • Figure 26 depicts another example of a VMM system.
  • Figure 27 depicts another example of a VMM system.
  • Figure 28 depicts another example of a VMM system.
  • Figure 29 depicts another example of a VMM system.
  • Figure 30 depicts another example of a VMM system.
  • Figure 31 depicts another example of a VMM system.
  • Figure 32 depicts another example of a VMM system.
  • Figure 33 depicts another example of a VMM system.
  • Figure 34 depicts an analog computation-in-memory system.
  • Figure 35 depicts a digital computation-in-memory system.
  • Figure 36 depicts a hybrid system comprising analog computation-in-memory systems and digital computation-in-memory systems.
  • Figure 37 depicts an analog computation-in-memory engine.
  • Figure 38 depicts an example digital computation-in-memory engine.
  • Figure 39 depicts another example digital computation-in-memory engine.
  • Figure 40 depicts another example digital computation-in-memory engine.
  • Figure 41A depicts a multiply logic cell.
  • Figure 41B depicts a 2-bit adder logic cell.
  • Figure 41C depicts a digital CIM cell.
  • Figure 42 depicts another example digital computation-in-memory-engine.
  • Figure 43 depicts a shift and adder tree.
  • Figure 44 depicts another shift and adder tree.
  • Figure 45 depicts an example dynamic weight engine.
  • Figure 46 depicts another example dynamic weight engine.
  • Figure 47 depicts an integrating analog-to-digital converter.
  • Figure 48 depicts an integrating analog-to-digital converter.
  • Figures 49A and 49B depict output circuits comprising a current-to-voltage converter and an analog-to-digital converter.
  • Figure 50 depicts a method performed by the hybrid system of Figure 36.
  • 27 ACTIVE ⁇ 302955060.6
  • Figure 34 depicts a block diagram of an analog computation-in-memory (CIM) engine 3400.
  • CCM computation-in-memory
  • Analog CIM engine 3400 comprises VMM array 3401 (which also can be referred to as a neural network array), row decoder 3402, high voltage decoder 3403, column decoders 3404, bit line drivers 3405 (such as bit line control circuitry for programming), input circuit 3406, output circuit 3407, control logic 3408, and bias generator 3409.
  • Analog CIM engine 3400 further comprises high voltage generation block 3410, which comprises charge pump 3411, charge pump regulator 3412, and high voltage level generator 3413.
  • Analog CIM engine 3400 further comprises (program/erase, or weight tuning) algorithm controller 3414, analog circuitry 3415, control engine 3416 (that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), test control logic 3417, and static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data) or data in for programming (such as data in for a whole row or for multiple rows).
  • program/erase, or weight tuning algorithm controller 3414
  • analog circuitry 3415 that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation
  • test control logic 3417 test control logic 3417
  • SRAM static random access memory
  • VMM array 3401 comprises an array of non-volatile memory cells arranged into rows and columns, where the non-volatile memory cells are of the type shown in Figures 2, 3, 4, or 5 as memory cells 210, 310, 410, or 510, respectively, or are of other types known to persons of ordinary skill in the art.
  • the non-volatile memory cells are split-gate flash memory cells as in Figures 2, 3, or 4.
  • the non-volatile memory cells are stacked-gate flash memory cells as in Figure 5.
  • the input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, or digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, or logarithmic converter), PAC (pulse to analog level converter), or any other type of converter.
  • the input circuit 3406 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions.
  • the input circuit 3406 may implement a temperature compensation function for input levels.
  • the input circuit 3406 may implement an activation function such as a rectified linear activation function (ReLU) or sigmoid.
  • ReLU rectified linear activation function
  • Input circuit 3406 may store digital 28 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 activation data to be applied as, or combined with, an input signal during a program or read operation.
  • the digital activation data can be stored in registers.
  • Input circuit 3406 may comprise circuits to drive the array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers.
  • a DAC can be used to convert digital activation data into an analog input voltage to be applied to the array.
  • Output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, or a logarithmic converter), APC (analog to pulse(s) converter, or analog to time modulated pulse converter), or any other type of converter.
  • Output circuit 3407 may convert array outputs into activation data.
  • Output circuit 3407 may implement an activation function such as ReLU or sigmoid.
  • Output circuit 3407 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs.
  • Output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same over temperature.
  • Output circuit 3407 may comprise registers for storing output data.
  • Digital Computation-in-Memory Figure 35 depicts a block diagram of digital computation-in-memory (CIM) engine 3500.
  • Digital CIM engine 3500 contains many, but not all, of the components contained in analog CIM engine 3400.
  • Digital CIM engine 3500 comprises array 3501, row decoder 3502, column decoders 3504, bit line drivers 3505 (such as bit line control circuitry for programming), input circuit 3506, output circuit 3507, control logic 3508, and bias generator 3509.
  • Digital CIM engine 3500 further comprises algorithm controller 3514, analog circuitry 3515, control engine 3516, and test control logic 3517.
  • Array 3501 comprises an array of non-volatile memory cells arranged into rows and columns, where the non-volatile memory cells are of the type shown in Figures 2, 3, 4, or 5 as memory cells 210, 310, 410, or 510, respectively, or are of other types known to persons 29 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 of ordinary skill in the art.
  • the non-volatile memory cells are split-gate flash memory cells as in Figures 2, 3, or 4.
  • the non-volatile memory cells are stacked-gate flash memory cells as in Figure 5.
  • the input circuit 3506 may include circuits such as a DAC, DPC, AAC, PAC , or any other type of converter.
  • the input circuit 3506 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions.
  • the input circuit 3506 may implement a temperature compensation function for input levels.
  • the input circuit 3506 may implement an activation function such as ReLU or sigmoid.
  • Input circuit 3506 may store digital activation data to be applied as, or combined with, an input signal during a program or read operation. The digital activation data can be stored in registers.
  • Input circuit 3506 may comprise circuits to drive the array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers.
  • a DAC can be used to convert digital activation data into an analog input voltage to be applied to the array.
  • Output circuit 3507 may include circuits such as an ITV, ADC, AAC , APC , or any other type of converter.
  • Output circuit 3507 may convert array outputs into activation data.
  • Output circuit 3507 may implement an activation function such as ReLU or sigmoid.
  • Output circuit 3507 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs.
  • Output circuit 3507 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same over temperature.
  • Output circuit 3507 may comprise registers for storing output data.
  • digital CIM engine 3500 does not utilize any analog circuitry and operates purely in the digital domain.
  • input circuit 3506 and output circuit 3507 can be formed of purely digital logic circuits that operate in the digital domain and analog circuitry 3515 can be removed.
  • 30 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682
  • Hybrid System Comprising Analog Computation-in-Memory Engines, Digital Computation-in-Memory Engines, and Dynamic Weight Engines
  • Figure 36 depicts hybrid system 3600.
  • Hybrid system comprises analog CIM engines 3601, 3602, and 3604; digital CIM engines 3605 and 3607; digital computation engines 3606 and 3608; dynamic weight engine 3603; and system bus 3609.
  • the VMM systems described in Figures 9-13 and 22- 33 are examples of analog CIM engines.
  • the digital CIM engines 3605 and 3607 can store digital weights in non-volatile macros or chips.
  • Digital computation engines 3606 and 3608 are microprocessors, digital signal processors, or other digital computation engines such as GPU (graphic processing units), TPU (Tensor processing units), dedicated MAC (multiply-add-accumulate) units, dedicated SIMD (single instruction multiple data) processor, vector extension, etc.
  • Digital computation engines 3606 and 3608 can perform computations of integers or floating point numbers.
  • the digital computation engines 3606 and 3608 can use the weights from the VMM array in analog CIM engines or from a digital non-volatile memory macros or chips.
  • Dynamic weight engine 3603 is a device whose stored weights can be modified by changing a bias voltage or bias current without performing a separate erase or program operation. Since the weights can be modified without performing a separate erase or program operation, these weights are considered dynamic weights. The weights can be transferred from the VMM array in analog CIM engines or from a digital non-volatile memory macros or chips. Examples of dynamic weight engine 3603 are shown in Figures 45 and 46, in which a bias voltage is transferred into a gate of a transistor in a unit CIM array cell. The dynamic weight control and bias circuits are not shown.
  • Dynamic weight engine 3603, analog CIM engines 3601, 3602, and 3604, digital CIM engines 3605 and 3607, and digital computation engines 3606 and 3608 are coupled to system bus 3609, which enables all coupled devices to communicate with one another.
  • Microcontroller 3610, SRAM 3611, vector register 3612, and peripheral control and interface logic 3613 assist in certain functions and operations (such as controlling the access to SRAM 3611, controlling the data flow of various computation engines, controlling the communication between the internal system bus 3609 and an external bus, performing activation functions, performing read, erase, and program operations on non-volatile memory (NVM) or volatile memory (VM) , or performing weight transfer between computation engines, without limitation) in hybrid system 3600.
  • Figure 50 depicts an example method that can be performed by hybrid system 3600. First, the system performs vector-by-matrix multiplication operations in a first layer of a neural network using digital computation-in-memory engine 3605 or 3607 (5001).
  • the system performs vector-by-matrix multiplication operations in a second layer different than the first layer of the neural network using analog computation-in-memory engine 3601, 3602, or 3604 (5002).
  • the system transfers dynamic weights from dynamic weight engine 3603 to one or more of the analog computation-in-memory engine 3601, 3602, or 3604 and/or the digital computation-in-memory engine 3605 or 3607 (5003).
  • the system stores the dynamic weights in the analog computation-in-memory engine 3601, 3602, or 3604.
  • Figure 37 depicts a portion of an example of an analog CIM engine 3700. Here, two rows and four columns of non-volatile memory cells are shown.
  • the memory cells operate in the sub-threshold region and can store analog weights.
  • An activation input is provided to each selected row on the word line or control gate line, the memory cells in that row multiply those activation inputs by the stored analog weights and output a current representing that product in the bit line coupled to the column of each cell. Current is then summed up along the bitline (output line). The array output current is then converted by ADC circuits (not shown) to produce digital output bits.
  • the activation input can be provided as a pulse width (PW), as the output of a fixed bias 1-bit digital-to-analog converter, or as the output of an n-bit DAC.
  • PW pulse width
  • Other examples of a portions of an analog CIM engine are shown in Figures 9-13 and 22-33.
  • Portion of an analog CIM engine 3700 also can be used as an analog memory weight storage. In that event, a word of memory cells (e.g., 64 or 128 cells from a selected row) are selected and the output digital output bits from the ADC represents the weight values stored by the portion of analog CIM engine 3700.
  • Figure 38 depicts a portion of an example digital CIM engine 3800.
  • Portion of digital CIM engine 3800 comprises an array of current-based CIM SRAM memory cells 3801, 3802, 3803, and 3804 arranged into rows and columns.
  • CIM SRAM memory cell 3801 will be described in detail, and it is to be understood that the other CIM SRAM memory cells 3801 have the same design.
  • CIM SRAM memory cell 3801 if the weight stored in the SRAM is a “1,” then NMOS transistor 3816 is turned on, and the current NC passes from transistor 3815 to transistor 3817 toward bitline BL0. If the weight stored in the SRAM is a “0,” then NMOS transistor 3816 is turned off, and the current NC is blocked from passing from transistor 3815 to transistor 3817 toward the bitline BL0.
  • the current NC is the effective value of the stored weight in a CIM SRAM cell.
  • an input is applied to input line IN0.
  • SRAM memory cell 3801 performs a multiplication of the input on IN0 with the stored weight. If IN0 is a “1,” then NMOS transistor 3817 is turned on to pass the current NC (representing stored weight value) to the bitline BL0, and if IN0 is a “0,” then NMOS transistor 3817 is turned off and no current NC is passed to the bitline BL0. If the stored weight is a “1” and if the input on the input line is a “1”, then bit line BL0 will receive the current NC because NMOS transistors 3815, 3816, and 3817 are all on.
  • bit line BL0 will be disconnected from the current NC and will not contain any current attributable to SRAM memory cell 3801.
  • CIM SRAM memory cells 3802, 3803, and 3804 and other CIM SRAM memory cells in the digital CIM engine operate in the same manner as CIM SRAM memory cell 3801.
  • 33 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 This current can be converted into digital output bits by an ADC circuit or multi-bit sense amplifier circuit.
  • Figure 39 depicts a portion of another example digital CIM engine 3900.
  • Portion of digital CIM engine 3900 comprises an array of charge-based CIMSRAM memory cells 3901, 3902, 3903, and 3904 arranged into rows and columns.
  • CIM SRAM memory cell 3901 is representative of CIM SRAM memory cells 3902, 3903, and 3904 and other CIM SRAM memory cells in the digital CIM engine and its operation will now be described.
  • SRAM memory cell 3901 comprises inverters 3911 and 3912 forming a latch; NMOS transistors 3913, 3914, 3916, 3917, and 3918; and capacitor 3915.
  • An amount of charge (representing a weight value), Q, equal to C (the capacitance value of the capacitor) * Vdds (which is the supply voltage for the SRAM memory cell) is stored on the capacitor 3915 in an SRAM cell.
  • word line WL0 is asserted, which turns on NMOS transistors 3913 and 3914.
  • a “1” is stored in the latch by driving BLS0B high and BLS0 low, and a “0” is stored in the latch by driving BLS0 high and BLS0B low.
  • ENSB is asserted.
  • SRAM memory cell 3901 performs a multiplication of the input on IN0 with the stored weight. If IN0 is a “1,” then NMOS transistor 3917 is turned on, and if WLN0 is a “0,” then NMOS transistor 3917 is turned off.
  • bit lines of the digital CIM engine such as BL0 and BL1 will sum the charges of all SRAM memory cells connected to them, meaning that BL0 will contain the sum of all charges output by all SRAM memory cells in column 0, BL1 will contain the sum of all charges output by all SRAM memory cells in column 1, and so forth.
  • This summed charge can be converted into digital output bits by an ADC circuit such as those shown in Figures 44 and 46 below.
  • Figure 40 depicts a portion of another example digital CIM engine 4000.
  • Portion of digital CIM engine 4000 comprises sub-arrays of CIM digital cells, where each CIM digital cell stores a weight, w, of 1-bit.
  • sub-arrays 4010-11 and 4010-12 are shown in detail.
  • digital CIM engine 4000 comprises m sub-arrays (such as sub- arrays 4010-11, 4010-12, ..., 4010-1m in row 1).
  • digital CIM engine 4000 comprises n sub-arrays (such as sub-arrays 4010-11, ..., 4010-n1 in column 1).
  • Sub-array 4010-11 will now be described as an example. The discussion as to sub- array 4010-11 applies to the other sub-arrays as well.
  • Sub-array 4010-11 comprises an array of CIM digital cells, such as CIM digital cell 4001, arranged into rows and columns.
  • sub-array 4010-11 comprises four rows and four columns of CIM digital cells, but it is to be understood that sub-array 4010-11 and the other sub-arrays each could instead comprise any number of rows and columns according to the same principles discussed here, such as 8 rows and 8 columns to accommodate an 8-bit input and an 8-bit weight (meaning 1 bit is stored in each of 8 CIM digital cells, together storing an 8-bit weight) yielding a 16-bit output (since 8-bit input multiplied with 8-bit weight yields 16-bit output).
  • 8 rows and 8 columns to accommodate an 8-bit input and an 8-bit weight (meaning 1 bit is stored in each of 8 CIM digital cells, together storing an 8-bit weight) yielding a 16-bit output (since 8-bit input multiplied with 8-bit weight yields 16-bit output).
  • MUX block is used to enable the output from each sub-array 4010x into the main output bus DOUTx.
  • Digital CIM engine 4000 receives inputs for a plurality of rows.
  • sub- array 4010-11 receives inputs IN[0], IN[1], IN[2], and IN[3] on its four rows.
  • the 4-bit input is to multiplied with 4-bit weight W[3:0] stored in the each row.
  • Each digital cell such as digital cell 4001, receives an input on its port I1, multiplies the input by a 1-bit weight value (W) stored in the digital cell, and adds the resulting product with any data received on its port I2 from a digital cell located in a row above it along with any carryover bit received on its port CI from a neighboring digital cell located to its right in the same row.
  • Each CIM digital cell such as CIM digital cell 4001 comprises a memory device such as an SRAM cell, latch, or register for storing a weight, W.
  • Each digital cell such as CIM digital cell 4001 also comprises digital multiply and add logic. Inputs are received in digital form by each row of digital devices in the I1 port of each CIM digital cell.
  • the input received on port I1 is multiplied by the weight stored in the SRAM of the CIM digital cell and the results are then added and output on a column-by-column basis.
  • the output (O) of a particular CIM digital cell is provided as an input (I2) to the CIM digital cell located below that particular CIM digital cell in the same column, and the carry output (CO) from a particular CIM digital cell is provided as a carry input (CI) input to the CIM digital cell located to its left in the same row, as that cell represents a more significant bit than the particular CIM digital cell.
  • Multiplexor block 4020-11 is used to enable the output from sub-array 4010-11 into the main output bus DOUTx in response to enable signal EN0.
  • Figures 41A, 41B, and 41C depict example components that can be used in each CIM digital cell of Figure 40 such as CIM digital cell 4001.
  • multiply logic cell 4101 receives two inputs, I1 and I2, and outputs their product, O, according to the truth table shown in Table 9: 36 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682
  • Table No.9 Truth Table for Multiply Logic Cell 4101 I1 I2 O 0 0 0 0 1 0 1 0 0 1 1 1
  • 2-bit adder logic cell 4102 receives inputs I1 and I2, and carry input CI, and generates output O and carry output CO according to the truth table shown in Table No.10: Table No.10: Truth Table for 2-Bit Adder Logic Cell 4102 I1 I2 C1 O CO 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1
  • each digital CIM cell 4103 performs a one-bit-wise multiplication operation (W * I2) and adds the result to a received input (I1 and CI) to perform the vector-by-matrix multiplication operation using the stored digital value, W.
  • Figure 42 depicts a portion of another example digital CIM engine 4200.
  • Portion of digital CIM engine 4200 comprises an array of blocks, with each block comprising an array of multipliers and a shift and adder tree.
  • blocks 4210-11, 4210-12, 4210-21, and 4210-22 are shown in detail.
  • digital CIM engine 4200 comprises m 37 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 blocks (such as blocks 4210-11, 4210-12, ..., 4212-1m in row 1).
  • digital CIM engine 4200 comprises n blocks (such as blocks 4210-11, 4210-21, ..., 4210-n1 in column 1).
  • Block 4210-11 will now be described as an example. The discussion as to block 4210-11 applies to the other blocks as well.
  • Block 4210-11 comprises an array of multipliers, such as multiplier 4201, arranged in rows and columns.
  • block 4210-11 comprises four rows and four columns of multipliers, but it is to be understood that block 4210- 11 and all other blocks could instead any number of rows and columns according to the same principles discussed here, such as 8 rows and 8 columns to accommodate an 8-bit input and an 8- bit weight yielding a 16-bit output.
  • Digital CIM engine 4200 receives inputs for a plurality of rows.
  • block 4210-11 receives inputs IN[0], IN[1], IN[2], and IN[3] on its four rows.
  • Each multiplier such as multiplier 4201, receives an input and multiplies the input by a 1-bit weight (W) stored in the multiplier, and outputs the product.
  • W 1-bit weight
  • the products are provided to shift and adder tree 4202, which adds the products and performs a shift operation as appropriate to reflect the fact that each row (IN[0], IN[1], IN[2], and IN[3]) represents a different digit in the binary input (IN[3:0]). That is, IN[0] represents 2 0 , IN[1] represents 2 1 , IN[2] represents 2 2 , and IN[3] represents 2 3 .
  • Multiplexor block 4203 is used to enable the output from each block, such as block 4210-11, into the main output bus DOUTx in response to an enable signal, EN0.
  • the other blocks have similar multiplexor blocks.
  • Figures 43 depicts shift and adder tree 4300, which is an example of an implementation of shift and adder tree 4202 used in Figure 42.
  • Each multiplier such as multiplier 4201, in a block such as block 4210-11, will receive a 1-bit input, multiply it by a 1-bit weight, and output a 1-bit value provided to shift and adder tree 4202.
  • shift and adder tree 4300 receives 41-bit values, which it treats as a single 4-bit value arranged in the order corresponding to columns D3, D2, D1, and D0, respectively.
  • the 4-bit value for row 0 (which received input IN[0]) is X4-0, for row 1 (which received input IN[1]) is X4-1, for row 2 (which received input IN[2]) is X4-2, and for row 3 (which received input IN[3]) is X4-3.
  • Shift and adder 4301 first adds X4-0 with X4-1 (where it shifts the digits of X4-1 one digit to the left due to the fact that row 1 represents the value of the input digit to the left of row 38 ACTIVE ⁇ 302955060.6
  • Shift and adder 4302 then adds that 6-bit value with a shifted version of X4-2 (where X4-2 is shifted two digits), yielding a 7-bit value.
  • Shift and adder 4303 then adds that 7-bit value with X4-3 (where X4-3 is shifted three digits), yielding an 8-bit value, which represents the sum of the products received from the multipliers of the block.
  • Figures 44 depicts shift and adder tree 4400, which is an example of an implementation of shift and adder tree 4202 used in Figure 42.
  • Each multiplier such as multiplier 4201, in a block such as block 4210-11, will receive a 1-bit input, multiply it by a 1-bit weight, and output a 1-bit value provided to shift and adder tree 4202.
  • shift and adder tree 4400 receives 41-bit values, which it treats as a single 4-bit value arranged in the order corresponding to columns D3, D2, D1, and D0, respectively.
  • the 4-bit value for row 0 (which received input IN[0]) is X4-0
  • row 1 which received input IN[1]
  • row 2 which received input IN[2]
  • X4-2 for row 3 (which received input IN[3]) is X4-3.
  • Shift and adder 4401 first adds X4-0 with X4-1 (where it shifts the digits of X4-1 one digit to the left due to the fact that row 1 represents the value of the input digit to the left of row 0; for example, if X4-1 is 1010, the shifted version will be 10100), yielding a 6-bit value, X6.
  • Shift and adder 4302 then adds a shifted version of X4-2 (where X4-2 is shifted two digits) with a shifted version of X4-3 (where X4-3 is shifted three digits), yielding a 7-bit value, X7.
  • Dynamic weight engine 4500 comprises CIM dynamic weight cells 4501, 4502, 4503, and 4504, arranged into rows and columns.
  • CIM dynamic weight cell 4501 is representative of CIM dynamic weight cells 4502, 4503, and 4504 and other CIM memory cells in the dynamic weight engine and its operation will now be described.
  • CIM dynamic weight cell 4501 comprises NMOS transistors 4511, 4512, 39 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 4514, and 4515, and capacitor 4513.
  • CIM dynamic weight cell 4501 can store a weight that can be dynamically changed by modification of an input.
  • CIM dynamic weight cell 4501 is selected when WL0 and WBL0 are asserted. When WL0 is asserted, NMOS transistors 4511 and 4514 are turned on. When WBL0 is asserted, NMOS transistor 4512 are turned on.
  • a voltage, W, representing the weight applied by CIM dynamic weight cell 4501, is applied to WWL0 and is transferred to the gate of the NMOS transistor 4515, and stored by capacitor 4513 that is coupled between the gate of NMOS transistor 4515 and SL0, which is a source line for row 0.
  • NMOS transistor 4515 will draw current from bit line BL0, where the drawn current is a function of the voltage, W.
  • CIM dynamic weight cells 4502, 4503, 4504, and other CIM dynamic weight cells in the dynamic weight engine operate in the same manner as CIM dynamic weight cell 4501.
  • Dynamic weight engine 4600 comprises CIM dynamic weight cells 4601, 4602, 4603, and 4604, arranged into rows and columns.
  • CIM dynamic weight cell 4601 is representative of CIM dynamic weight cells 4602, 4603, and 4604 and other CIM dynamic weight cells in the dynamic weight engine and its operation will now be described.
  • CIM dynamic weight cell 4601 comprises NMOS transistors 4611, 4612, 4613, 4615, and 4616, and capacitor 4614.
  • CIM dynamic weight cell 4601 can store a weight that can be dynamically changed by modification of an input.
  • CIM dynamic weight cell 4601 is selected when WL0 and WBL are asserted. When WL0 is asserted, NMOS transistors 4611 and 4615 are turned on. When WBL is asserted, NMOS transistor 4613 is turned on.
  • a voltage, W, representing the weight applied by CIM dynamic weight cell 4601 is applied to WWL0 and is transferred to the gate of the NMOS transistor 4616, and stored by capacitor 4614 that is coupled between the gate of NMOS transistor 4616 and SL0, which is a source line for 40 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 row 0. NMOS transistor 4616 will draw current from bit line BL0, where the drawn current is a function of the voltage, W.
  • CIM dynamic weight cells 4602, 4603, 4604, and other CIM dynamic weight cells in the dynamic weight engine operate in the same manner as CIM dynamic weight cell 4601.
  • bit lines of the CIM dynamic weight engine such as BL0 and BL1 will sum the currents drawn by all CIM dynamic weight cells connected to them, meaning that BL0 will contain the sum of all currents drawn by all CIM dynamic weight cells in column 0, BL1 will contain the sum of all currents drawn by all CIM dynamic eight cells in column 1, and so forth.
  • This current can be converted into digital output bits by an ADC circuit such as those shown in Figures 47 and 49 below.
  • Figure 47 depicts an example integrating ADC 4700 used to convert charge stored in the cells of the portion of digital CIM engine 3900 in Figure 39 into digital pulses or digital output bits.
  • Integrating ADC 4700 converts an analog output charge (charge stored in the capacitor 4702 CINT) in a neuron output block into a digital pulse whose width varies in proportion to the magnitude of the analog output current in the neuron output block.
  • the capacitor 4702 represents all the capacitors from the selected CIM volatile SRAM memory cells being summed up (connected in parallel through pass transistor) in Figure 39.
  • the ADC 4700 comprises reference current 4707, op amp 4701, comparator 4704, AND gate 4740, and counter 4720. Charges of individual capacitors in the CIM volatile SRAM memory cells are summed up and then re-configured to be an integrating capacitor 4702 across the op amp 4701.
  • the reference current 4707 discharges the total stored charge in the integrating capacitor 4702, and counter 4720 generates pulses until the discharge is complete.
  • the pulses represent the digital output bits as shown in Figure 48.
  • Figure 48 depicts integrating ADC 4800 used to convert current received from one or more columns in analog CIM engine in Figure 37, digital CIM engine 3800 in Figure 38, dynamic weight engine 4500 in Figure 45, and dynamic weight engine 4600 in Figure 46 into digital pulses or digital output bits.
  • ADC 4800 converts a current, INEU, into a digital pulse, EC, whose width varies in proportion to the magnitude of the current.
  • An integrator comprising integrating op-amp 4801 41 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 and integrating capacitor 4802 integrates INEU 4806 versus a reference current, IREF, provided by current source 4807.
  • current source 4807 can comprise a bandgap filter with a temperature coefficient of 0 or with a temperature coefficient that tracks the neuron current, INEU.
  • a temperature coefficient that tracks INEU can be obtained from a lookup table (not shown) containing values determined during a testing phase.
  • switch 4808 is closed. Vout 4803 and the input to the negative terminal of operational amplifier 4801 then will become equal to VREF.
  • switch 4808 is opened, and switch S2 is closed, while switch S1 remains open, and during a fixed time period tref, the constant reference current IREF 4807 is up-integrated.
  • Vout rises, and its slope is reflective of the value of constant reference current IREF 4807.
  • switch S2 is opened, and switch S1 is closed, and during a period tmeas, neuron current I NEU 4806 is down integrated for a time period tmeas (during which period Vout falls), where tmeas is the time to down integrate Vout to VREF, as indicated by the output of comparator 4804 changing.
  • Output EC 4805 will be high when VOUT > VREFV and will be low otherwise.
  • EC 4805 therefore generates a pulse whose width reflects the period tmeas, which in turn is proportional to the current INEU 4806.
  • the output neuron current INEU 4806 is converted into a digital pulse EC 4805, where the width of digital pulse EC 4805 varies in proportion to the magnitude of output neuron current I NEU 4806.
  • tref is a time period equal to 1024 clock cycles.
  • the period tmeas varies from a period equal to 0 to 1024 clock cycles depending on the value of I NEU 4806 and the value of Iref.
  • the neuron current INEU 4806 affects the rate and slope of charging.
  • the output pulse EC 4805 can be converted into a series of pulses of uniform period for transmission to the next block of circuitry, such as the input block of CIM engine.
  • output EC 4805 is input into AND gate 4840 with reference clock 4841.
  • the output will be pulse series 4842 (where the frequency of the pulses in pulse series 4842 is the same as the frequency of clock 4841) during the period when VOUT > 42 ACTIVE ⁇ 302955060.6
  • Attorney Docket Number: 351913-980682 VREF Attorney Docket Number: 351913-980682 VREF.
  • the number of pulses is proportional to the period tmeas, which is proportional to the current I NEU 4806.
  • pulse series 4843 can be input to counter 4820, which will count the number of pulses in pulse series 4842 and will generate count value 4821, which is a digital count of the number of pulses in pulse series 4842, which is directly proportional to neuron current I NEU 4806.
  • Count value 4821 comprises a set of digital bits.
  • integrating ADC 4800 can convert neuron current INEU 4806 into a pulse where the width of the pulse is inversely proportionally to the magnitude of neuron current INEU 4806. This inversion can be done in a digital or analog manner, and converted into a series of pulses or digital bits for output to follow on circuitry.
  • Figure 49A depicts an example output circuit 4900 that can convert the array current into digital output bits.
  • the output circuit 4900 comprises current-to-voltage converter (ITV) 4901 and analog-to-digital converter (ADC) 4902.
  • the ITV 4901 converts the array current into a voltage which is then digitized by the ADC 4902.
  • the ADC 4902 can be a successive approximation (SAR) ADC.
  • Figure 49B depicts example output circuit 4950 comprising ITV 4951 that receives a differential input and generates a differential output and ADC 4952 that receives a differential input from the differential output of ITV 4951 and generates a single-ended digital output. Examples of implementations of current-to-voltage converters and analog-to-digital converters are described in U.S. Patent Application No.17/521,772, which is incorporated by reference herein.
  • analog and digital CIM engines can utilize NAND memory, resistive RAM (ReRAM), magnetic RAM (MRAM), or dynamic RAM (DRAM), without limitation.
  • ReRAM resistive RAM
  • MRAM magnetic RAM
  • DRAM dynamic RAM
  • adjacent includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between)
  • mounted to includes “directly mounted to” (no intermediate 43 ACTIVE ⁇ 302955060.6 Attorney Docket Number: 351913-980682 materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between)
  • electricalally coupled includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between. 44 ACTIVE ⁇ 302955060.6

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Abstract

Dans un exemple divulgué dans la présente invention, un système comprend un moteur de calcul en mémoire analogique pour mettre en œuvre des opérations dans une première couche dans un réseau neuronal et un moteur de calcul en mémoire numérique pour mettre en œuvre des opérations dans une seconde couche différente de la première couche dans le réseau neuronal. Le système comprend éventuellement un moteur de poids dynamique pour mettre en œuvre des opérations dans une troisième couche différente de la première couche et de la seconde couche dans le réseau neuronal.
PCT/US2023/027757 2023-04-10 2023-07-14 Moteur de calcul en mémoire analogique et moteur de calcul en mémoire numérique pour mettre en œuvre des opérations dans un réseau neuronal Pending WO2024215350A1 (fr)

Priority Applications (3)

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CN202380096489.4A CN120937080A (zh) 2023-04-10 2023-07-14 用于在神经网络中执行操作的模拟存储器内计算引擎和数字存储器内计算引擎
KR1020257026616A KR20250134117A (ko) 2023-04-10 2023-07-14 신경망에서 연산들을 수행하기 위한 아날로그 메모리-내-계산 엔진 및 디지털 메모리-내-계산 엔진
TW113111113A TW202445421A (zh) 2023-04-10 2024-03-26 神經網路中執行運算之類比記憶體中計算引擎及數位記憶體中計算引擎

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