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WO2024162978A1 - Multiplexeurs pour réseau de réseaux neuronaux - Google Patents

Multiplexeurs pour réseau de réseaux neuronaux Download PDF

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Publication number
WO2024162978A1
WO2024162978A1 PCT/US2023/019753 US2023019753W WO2024162978A1 WO 2024162978 A1 WO2024162978 A1 WO 2024162978A1 US 2023019753 W US2023019753 W US 2023019753W WO 2024162978 A1 WO2024162978 A1 WO 2024162978A1
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Prior art keywords
memory cells
array
rows
vmm
volatile memory
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English (en)
Inventor
Hieu Van Tran
Stanley Hong
Thuan Vu
Stephen Trinh
Anh Ly
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority claimed from US18/135,664 external-priority patent/US20240256846A1/en
Application filed by Silicon Storage Technology Inc filed Critical Silicon Storage Technology Inc
Priority to EP23725490.9A priority Critical patent/EP4659148A1/fr
Priority to KR1020257022222A priority patent/KR20250119601A/ko
Priority to CN202380092722.1A priority patent/CN120604240A/zh
Priority to TW113101487A priority patent/TWI897198B/zh
Publication of WO2024162978A1 publication Critical patent/WO2024162978A1/fr
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0499—Feedforward networks

Definitions

  • Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other.
  • Figure 1 illustrates neural network 100, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning.
  • neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network.
  • the neurons at each level individually or collectively make a decision based on the received data from the synapses.
  • One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency 1 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation.
  • CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.
  • Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference.
  • the non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns.
  • the neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs.
  • the first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region.
  • Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate.
  • Non-Volatile Memory Cells are known.
  • U.S. Patent 5,029,130 (“the ’130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells.
  • Such a memory cell 210 is shown in Figure 2.
  • Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between.
  • Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14.
  • Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up 2 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 and over the floating gate 20.
  • the floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide.
  • Bitline 24 is coupled to drain region 16.
  • Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. [0010] Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal).
  • SSI source side injection
  • the floating gate 20 is positively charged (i.e., erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
  • Table No.1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations: Table No.1: Operation of Flash Memory Cell 210 of Figure 2 WL BL SL Read 2-3V 0.6-2V 0V Erase ⁇ 11-13V 0V 0V 3 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 Program 1-2V 10.5- 9-10V 3 ⁇ A [0012] Other split gate memory cell configurations, which are other types of flash memory cells, are known.
  • Figure 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14.
  • WL word line
  • FIG. 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14.
  • WL word line
  • erase gate 30 over the source region 14.
  • Table No.2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No.2: Operation of Flash Memory Cell 310 of Figure 3 WL/SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V Erase -0.5V/0V 0V 0V/-8V 8-12V 0V Program 1V 0.1- 8-11V 4.5-9V 4.5-5V 1 ⁇ A [0014] Figure 4 depicts a three-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is identical to the memory cell 310 of Figure 3 except that memory cell 410 does not have a separate control gate.
  • the erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the Figure 3 except there is no control gate bias applied.
  • the programming operation also is done without the control gate bias, 4 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 and as a result, a higher voltage is applied on the source line during a program operation to compensate for a lack of control gate bias.
  • Table No.3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations: Table No.3: Operation of Flash Memory Cell 410 of Figure 4 WL/SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V Erase -0.5V/0V 0V 11.5V 0V Program 1V 0.2- 4.5V 7-9V 3 ⁇ A [0016] Figure 5 depicts stacked gate memory cell 510, which is another type of flash memory cell.
  • Memory cell 510 is similar to memory cell 210 of Figure 2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown).
  • the erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel 18 and the drain region 16, by the electrons flowing from the source region 14 towards to drain region 16 and read operation which is similar to that for memory cell 210 with a higher control gate voltage.
  • CHE channel hot electron
  • Table No.4 depicts typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and program operations: Table No.4: Operation of Flash Memory Cell 510 of Figure 5 C G BL SL Substrate Read 2-5V 0.6 – 2V 0V 0V Erase -8 to -10V/0V FLT FLT 8-10V / 15-20V Program 8-12V 3-5V 0V 0V 5 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 [0018]
  • the methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide- silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change
  • the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below.
  • continuous (analog) programming of the memory cells is provided.
  • the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells.
  • FIG. 6 conceptually illustrates a non-limiting example of a neural network 600 utilizing arrays of non-volatile memory cells of the present examples. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.
  • S0 is the input layer, which for this example is a 32x32 pixel RGB image with 5 bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being 5 bit precision).
  • the synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 6 WEST ⁇ 302574590.1
  • values for 9 pixels in a 3x3 portion of the image are provided to the synapses CB1, where these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1.
  • the 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse.
  • This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values).
  • the process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.
  • layer C1 in the present example, there are 16 feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships – i.e., the arrays are not necessarily oriented in physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification.
  • the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges
  • the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.
  • An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map.
  • the purpose of the pooling function P1 is to average out the nearby location (or a max function can also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage.
  • 1615x15 feature maps i.e., sixteen 7 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 different arrays of 15x15 pixels each).
  • the synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of 1 pixel.
  • An activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map.
  • An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3.
  • the synapses CB4 going from layer C3 to the output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 is connected to every neuron in layer S3.
  • the output at S3 includes 10 neurons, where the highest output neuron determines the class. This output could, for example, be indicative of an identification or classification of the contents of the original image.
  • Each layer of synapses is implemented using an array, or a portion of an array, of non- volatile memory cells.
  • FIG. 7 is a block diagram of a VMM system 32 that can be used for that purpose.
  • VMM Vector-by-matrix multiplication
  • VMM system 32 includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in Figure 6) between one layer and the next layer.
  • VMM system 32 includes VMM array 33 (which can also be referred to as neural network array 33), which is an array of non-volatile memory cells, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33.
  • VMM array 33 can be from the erase gate and wordline gate decoder 34 or from the control gate decoder 35.
  • Source line decoder 37 in this example also decodes the output of VMM array 33.
  • bit line decoder 36 can decode the output of VMM array 33.
  • VMM array 33 serves two purposes. First, it stores the weights that will be used by the VMM system 32. Second, VMM array 33 effectively multiplies the inputs by the weights stored in VMM array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer.
  • VMM array 33 negates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation. 8 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 [0028]
  • the output of VMM array 33 is supplied to a differential summer (such as a summing op- amp or a summing current mirror) 38, which sums up the outputs of the VMM array 33 to create a single value for that convolution.
  • the differential summer 38 is arranged to perform summation of positive weight and negative weight.
  • the summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output.
  • the activation function block 39 may provide sigmoid, tanh, or ReLU functions.
  • the rectified output values of activation function block 39 become an element of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to produce the next feature map layer or final layer. Therefore, in this example, VMM array 33 constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp 38 and activation function block 39 constitute a plurality of neurons.
  • the input to VMM system 32 in Figure 7 can be analog level, binary level, or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).
  • Figure 8 depicts neural network 800.
  • Neural network 800 comprises numerous layers formed of VMM systems 32, here labeled as VMM systems 32a, 32b, 32c, 32d, and 32e.
  • the input, denoted Inputx is converted from digital to analog by a digital-to- analog converter 31 and provided to input VMM system 32a.
  • the converted analog inputs could be voltage or current.
  • the input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM system 32a.
  • the input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a.
  • A/A analog to analog converter to convert an external analog input to a mapped analog input to the input VMM system 32a.
  • the output generated by input VMM system 32a is provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as an input to the next VMM system (hidden level 2) 32c, and so on.
  • VMM system 32 function as different layers of synapses and neurons of a convolutional neural network (CNN).
  • CNN convolutional neural network
  • Each VMM system 32a, 32b, 32c, 32d, and 32e can comprise a stand-alone, physical non- volatile memory array, or multiple VMM systems could utilize different portions of the same physical non-volatile memory array, or multiple VMM systems could utilize overlapping portions of the same physical non-volatile memory array.
  • the example shown in Figure 8 contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e).
  • VMM array 900 depicts VMM array 900, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array can also be referred to as a neural network array.
  • VMM array 900 comprises memory array 901 of non- volatile memory cells and reference array 902 (at the top of the array) of non-volatile reference memory cells. Alternatively, another reference array can be placed at the bottom.
  • control gate lines such as control gate line 903, run in a vertical direction (hence reference array 902 in the row direction is orthogonal to control gate line 903)
  • erase gate lines such as erase gate line 904, run in a horizontal direction.
  • the inputs to VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array 900 emerges on the source lines (SL0, SL1).
  • the current placed on each source line (SL0, SL1, respectively) performs a summing function of all the currents from the memory cells connected to that particular source line.
  • the non-volatile memory cells of VMM array 900 i.e., the memory cells 310 of VMM array 900, may be configured to operate in a sub- threshold region.
  • Vg n*Vt*log [Ids/wp*Io] where, wp is w of a reference or peripheral memory cell.
  • wa w of each memory cell in the memory array.
  • Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell.
  • the threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias voltage, denoted Vsb, can be modulated to compensate for various conditions, on such temperature.
  • a wordline or control gate can be used as the input for the memory cell for the input voltage.
  • a wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region.
  • the bitline or sourceline can be used as the output for the memory cell.
  • a memory cell such as a reference memory cell or a peripheral memory cell
  • a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage.
  • a wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region.
  • the bitline or sourceline can be used as the output for the output neuron.
  • the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.
  • Other examples for VMM system 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated by reference herein. As described in that application. a sourceline or a bitline can be used as the neuron output (current summation output).
  • Figure 10 depicts VMM array 1000, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses between an input layer and the next layer.
  • VMM array 1000 comprises a memory array 1003 of non-volatile memory cells, reference array 1001 of first non-volatile reference memory cells, and reference array 1002 of second non- volatile reference memory cells.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1014 (only 12 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 partially depicted) with current inputs flowing into them.
  • Memory array 1003 serves two purposes. First, it stores the weights that will be used by the VMM array 1000 on respective memory cells thereof. Second, memory array 1003 effectively multiplies the inputs (i.e.
  • memory array 1003 negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0 - BLN during a read (inference) operation.
  • the current placed on each of the bit lines BL0 - BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.
  • Table No.5 depicts operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells. The rows indicate the operations of read, erase, and program.
  • VMM Array 1000 of Figure 10 WL WL -unsel BL BL -unsel SL SL -unsel Read 1-3.5V -0.5V/0V 0.6-2V (Ineuron) 0.6V-2V/0V 0V 0V Erase ⁇ 5-13V 0V 0V 0V 0V 0V Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT 13 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 [0050]
  • Figure 11 depicts VMM array 1100, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 1100 comprises a memory array 1103 of non-volatile memory cells, reference array 1101 of first non-volatile reference memory cells, and reference array 1102 of second non-volatile reference memory cells. Reference arrays 1101 and 1102 run in row direction of the VMM array 1100.
  • VMM array is similar to VMM 1000 except that in VMM array 1100, the word lines run in the vertical direction.
  • the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation.
  • the current placed on each source line performs a summing function of all the currents from the memory cells connected to that particular source line.
  • Table No.6 depicts operating voltages and currents for VMM array 1100.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM Array 1100 of Figure 11 WL WL -unsel BL BL -unsel SL SL -unsel ⁇ 0.3-1V Read 1-3.5V -0.5V/0V 0.6-2V 0.6V-2V/0V (Ineuron) 0V SL-inhibit ( ⁇ 4- Erase ⁇ 5-13V 0V 0V 0V 0V 8V) Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT [0052]
  • Figure 12 depicts VMM array 1200, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and 14 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 the next layer.
  • VMM array 1200 comprises a memory array 1203 of non-volatile memory cells, reference array 1201 of first non-volatile reference memory cells, and reference array 1202 of second non-volatile reference memory cells.
  • Reference arrays 1201 and 1202 serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1212 (only partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3.
  • Multiplexors 1212 each include a respective multiplexor 1205 and a cascoding transistor 1204 to ensure a constant voltage on the bitline (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation.
  • the reference cells are tuned to target reference levels.
  • Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200.
  • memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays 1201 and 1202 convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 – BLN, and will be the input to the next layer or input to the final layer.
  • the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • VMM array 1200 implements uni-directional tuning for non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased, and the sequence of partial programming operations starts over.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, reference array 1301 or first non-volatile reference memory cells, and reference array 1302 of second non-volatile reference memory cells.
  • EG lines EGR0, EG0, EG1 and EGR1 are run vertically while CG lines CG0, CG1, CG2 and CG3 and SL lines WL0, WL1, WL2 and WL3 are run horizontally.
  • VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate EG lines.
  • reference arrays 1301 and 1302 convert input 16 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 current in the terminal BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells through multiplexors 1314) to be applied to the memory cells in the row direction.
  • the current output (neuron) is in the bit lines BL0 – BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bitline.
  • Table No.8 depicts operating voltages and currents for VMM array 1300.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM Array 1300 of Figure 13 CG -unsel WL - BL - same CG - EG - SL - WL unsel BL unsel CG sector unsel EG unsel SL unsel -0.5V/ 0.6-2V
  • Read 1.0-2V 0V (Ineuron) 0V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0-2.6V 0V 0V
  • Figure 14 depicts VMM array 1400, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer
  • FIG. 15 depicts neuron VMM array 1500, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input 17 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 layer and the next layer.
  • the inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL 0 , SL 1 , SL 2 , and SL 3 , respectively, and the outputs OUTPUT 0 , ... OUTPUT N are generated on bit lines BL 0 , ..., BL N .
  • Figure 16 depicts VMM array 1600, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL 0 , ..., WLM, respectively, and the outputs OUTPUT0, ...
  • FIG. 17 depicts VMM array 1700, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on word lines WL0, ..., WL M , respectively, and the outputs OUTPUT 0 , ... OUTPUT N are generated on bit lines BL 0 , ..., BL N .
  • FIG 18 depicts VMM array 1800, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT n are received on vertical control gate lines CG0, ..., CGN, respectively, and the outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.
  • Figure 19 depicts VMM array 1900, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • FIG. 20 depicts VMM array 2000, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • Figure 21 depicts VMM array 2100, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • FIG. 22 depicts VMM array 2200, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on control gate lines CG0, ..., CG M .
  • Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical bit lines BL 0 , ..., BL N , respectively, where each bit line BL i is coupled to the bit lines of all memory cells in column i.
  • FIG. 23 depicts VMM system 2300.
  • W+ lines half of the bit lines
  • W- lines half of the bit lines connecting to memory cells that will store positive weights W+
  • W- lines bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 2301 and 2302.
  • a summation circuit that receives current from a W+ line and a W- line
  • Figure 24 depicts VMM system 2400.
  • VMM system 2400 positive weights W+ are implemented in first array 2411 and negative weights W- are implemented in a second array 2412, second array 2412 separate from the first array, and the resulting weights are appropriately combined together by summation circuits 2413.
  • Figure 25 depicts VMM system 2500.
  • VMM system 2500 comprises array 2501 and array 2502.
  • Half of the bit lines in each of array 2501 and 2502 are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines in each of array 2501 and 2502 are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 2503, 2504, 2505, and 2506.
  • the W values from each array 2501 and 2502 can be further combined through summation circuits 2507 and 2508, such that each W value is the result of a W value from array 2501 minus a W value from array 2502, meaning that the end result from summation circuits 2507 and 2508 is a differential value of two differential values.
  • Each non-volatile memory cells used in the analog neural memory system is to be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, in the floating gate.
  • each floating gate should hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.
  • Prior art systems have encountered significant leakage within VMM arrays. Also, the circuitry outside the VMM array in a VMM system take a significant amount of space in the 20 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 semiconductor die.
  • FIG. 1 depicts an example neural network.
  • Figure 2 depicts a split gate flash memory cell.
  • Figure 3 depicts another split gate flash memory cell.
  • Figure 4 depicts another split gate flash memory cell.
  • Figure 5 depicts another split gate flash memory cell.
  • Figure 6 depicts an example neural network.
  • Figure 7 depicts an example VMM system.
  • Figure 8 depicts an example neural network.
  • Figure 9 depicts another example of a VMM array.
  • Figure 10 depicts another example of a VMM array.
  • Figure 11 depicts another example of a VMM array.
  • Figure 12 depicts another example of a VMM array.
  • Figure 13 depicts another example of a VMM array.
  • Figure 14 depicts another example of a VMM array.
  • Figure 15 depicts another example of a VMM array.
  • Figure 16 depicts another example of a VMM array.
  • Figure 17 depicts another example of a VMM array.
  • Figure 18 depicts another example of a VMM array.
  • Figure 19 depicts another example of a VMM array.
  • Figure 20 depicts another example of a VMM array.
  • Figure 21 depicts another example of a VMM array.
  • Figure 22 depicts another example of a VMM array.
  • Figure 23 depicts another example of a VMM system. 21 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642
  • Figure 24 depicts another example of a VMM system.
  • Figure 25 depicts another example of a VMM system.
  • Figure 26 depicts a VMM system.
  • Figure 27A depicts a selected memory cell.
  • Figures 27B, 27C, and 27D depict an unselected memory cell.
  • Figure 28 depicts a VMM system comprising source line pull down circuitry.
  • Figure 29 depicts a VMM system comprising an input block coupled to a neural network array.
  • Figure 30 depicts a VMM system comprising an input block coupled to a neural network array.
  • Figure 31 depicts a VMM system comprising an input block coupled to a neural network array. DETAILED DESCRIPTION OF THE INVENTION VMM System Architecture
  • Figure 26 depicts a block diagram of VMM system 2600.
  • VMM system 2600 comprises neural network array 2601 (which is a VMM array), row decoder 2602, high voltage decoder 2603, column decoders 2604, bit line drivers 2605 (which can comprise bit line control circuitry for programming), input circuit 2606, output circuit 2607, control logic 2608, and bias generator 2609.
  • VMM system 2600 further comprises high voltage generation block 2610, which comprises charge pump 2611, charge pump regulator 2612, and high voltage level generator 2613.
  • VMM system 2600 further comprises (program/erase, or weight tuning) algorithm controller 2614, analog circuitry 2615, control engine 2616 (that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), test control logic 2617, and static random access memory (SRAM) block 2618 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data) or data in for programming (such as data in for a whole row or for multiple rows).
  • program/erase, or weight tuning algorithm controller 2614
  • analog circuitry 2615 that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation
  • test control logic 2617 test control logic 2617
  • SRAM static random access memory
  • Neural network array 2601 comprises an array of non- volatile memory cells arranged into rows and columns, where the non-volatile memory cells are of the type shown in Figures 2, 3, 4, or 5 as memory cells 210, 310, 410, or 510, respectively, or 22 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 are of other types known to persons of ordinary skill in the art.
  • the non-volatile memory cells are split-gate flash memory cells as in Figures 2, 3, or 4.
  • the non-volatile memory cells are stacked-gate flash memory cells as in Figure 5.
  • the input circuit 2606 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converter.
  • the input circuit 2606 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions.
  • the input circuit 2606 may implement a temperature compensation function for input levels.
  • the input circuit 2606 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid.
  • ReLU rectified linear activation function
  • Input circuit 2606 may store digital activation data to be applied as, or combined with, an input signal during a program or read operation.
  • the digital activation data may be stored in registers.
  • Input circuit 2606 may comprise circuits to drive the array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers.
  • a DAC can be used to convert digital activation data into an analog input voltage to be applied to the array.
  • the output circuit 2607 may include circuits such as an ITV (current-to-voltage circuit), ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converter.
  • the output circuit 2607 may convert array outputs into activation data.
  • the output circuit 2607 may implement an activation function such as an ReLU or sigmoid.
  • the output circuit 2607 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic function (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs.
  • the output circuit 2607 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant over temperature or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same over temperature.
  • the output circuit 2607 may comprise registers for storing output data.
  • Figure 27A depicts memory cell 2700 with examples of voltages that are applied when memory cell 2700 is selected for a read operation. In this example, 0.6 V is applied to memory cell 2700's bitline terminal, 1.4 V to its word line terminal, 1.5 V to its control gate terminal, and 0 V to its source line terminal.
  • Figures 27B, 27C, and 27D depict memory cell 2700 in three separate situations where it is unselected for a read operation, meaning that memory cell 2700 is not intended to be read and is not intended to contribute to the read current in a bitline.
  • 0.6 V is applied to the bitline terminal, 0 V to the word line terminal, and 1.5 V to the control gate terminal.
  • 0.6 V is applied to the bitline terminal, 1.4 V to the word line terminal, and 0 V to the control gate terminal.
  • 0.6 V is applied to the bitline terminal, 0 V to the word line terminal, and 0 V to the control gate terminal.
  • a voltage of around 0.6 V is applied to the source line terminal. The application of a voltage of around 0.6 V to the source line terminal of un-selected memory cell 2700 is an inhibit action to reduce leakage on the bitline of the un-selected cells.
  • FIG. 28 depicts VMM system 2800.
  • VMM system 2800 comprises array 2601 and source line pull down circuit (SLPN) 2801.
  • SLPN source line pull down circuit
  • array 2601 can comprise many more rows and many more columns.
  • a sector 2811 comprises two rows of cells in array 2601.
  • Source line pull down circuit 2801 is provided on a per sector basis.
  • Source line pull down circuit 2801 comprises NMOS transistors 2802, 2803, 2804, and 2805.
  • NMOS transistor 2803 comprises a first terminal coupled to a line VBSL (which contains a voltage as described below), a gate coupled to a signal line SL0EN (which is an enable signal to connect source line SL0 to VBSL and is generated as a result of a sector decode 24 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 operation where the sector shown in Figure 28 is either selected or not selected, such as by row decoder 2602 or the HV decoder 2603 in Figure 26), and a second terminal.
  • VBSL which contains a voltage as described below
  • SL0EN which is an enable signal to connect source line SL0 to VBSL and is generated as a result of a sector decode 24 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 operation where the sector shown in Figure 28 is either selected or not selected, such as by row decoder 2602 or the HV decoder 2603 in Figure 26
  • NMOS transistor 2802 comprises a first terminal coupled to the second terminal of NMOS transistor 2803, a gate coupled to a signal line VCAS (which is a voltage applied to reduce stress on NMOS transistors 2803 and 2805 when a high voltage is applied to source line SL0 during a programming operation), and a second terminal coupled to source line SL0.
  • NMOS transistor 2804 comprises a first terminal coupled to the source line SL0, a gate coupled to the signal line VCAS, and a second terminal.
  • NMOS transistor 2805 comprises a first terminal coupled to the second terminal of NMOS transistor 2804, a gate coupled to a signal line SL0ENB (which is the complement of SL0EN and is an enable signal to connect source line SL0 to VBSL2 and is generated as a result of a sector decode operation where the sector shown in Figure 28 is either selected or not selected, such as by row decoder 2602 or the HV decoder 2603 in Figure 26), and a second terminal coupled to a signal line VBSL2 (which contains a voltage as described below).
  • SL0ENB which is the complement of SL0EN and is an enable signal to connect source line SL0 to VBSL2 and is generated as a result of a sector decode operation where the sector shown in Figure 28 is either selected or not selected, such as by row decoder 2602 or the HV decoder 2603 in Figure 26
  • a second terminal coupled to a signal line VBSL2 (which contains a voltage as described below).
  • VBSL receives from an external voltage source (not shown) a first voltage such as 0 V or 0.1 V (corresponding to the select operation shown in Figure 27A)
  • VBLSL2 receives from an external voltage source (not shown) a second voltage such as around 0.6V (corresponding to the unselect operation shown in Figures 27B, 27C, and 27D to reduce or inhibit leakage).
  • SL0EN is asserted and SL0ENB is de-asserted, and source line SL0 is coupled to VBSL, meaning that SL0 receives the first voltage.
  • FIGS 29-39 depict various input multiplexing schemes that can be used in VMM system 2600 to reduce the die space used for input circuit 2606 that provides inputs to neural network array 2601.
  • Figure 29 depicts VMM system 2900, which comprises neural network array 2601 and input block 2910.
  • Input block 2910 comprises row registers 2901-1 through 2901-8, row tag registers 2902-1 through 2902-8 (optional) containing row tag bits, digital to analog converters (DACs) 2903-1 through 2903-8 (or, alternatively, row sample and hold buffers (not shown)), multiplexors 2904-1 through 2904-8, and source line pull down circuit 2905 (which can 25 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 comprise source line pull down circuit 2801 in Figure 28 for each pair of consecutive rows or a comparable circuit).
  • DACs digital to analog converters
  • DACs digital to analog converters
  • multiplexors 2904-1 through 2904-8 or, alternatively, row sample and hold buffers (not shown)
  • source line pull down circuit 2905 which can 25 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 comprise source line pull down circuit 2801 in Figure 28 for each pair of consecutive rows or a comparable circuit.
  • the DACs 2903 are n-bit analog DACs where n bits received from row register 2901 are converted into an analog signal that is applied to neural network array 2601.
  • the DACs are 1-bit analog DAC where n bits received from row register 2901 are converted one bit at a time into an analog signal that is sequentially applied to neural network array 2601 in n separate operations and the resulting output from neural network array 2601 is summed together with output bit shifting performed.
  • the DACs are pulse DACs where n bits received from register 2901 are converted into voltage pulses that are applied to neural network array 2601.
  • Neural network array 2601 comprises rows 2906-1 through 2906-16. Here, only 16 rows are shown in neural network array 2601, but it is to be understood that neural network array 2601 comprises i rows, where i can be a multiple of 2 and can be less than or more than 16.
  • the sharing of row registers, row tag registers, and digital-to-analog converters is enabled by the use of multiplexors 2904.
  • respective multiplexors 2904 route an output of a digital- to-analog converter 2903 (or sample and hold buffer) to one of two rows in neural network array 2601.
  • multiplexor 2904-1 routes the output of digital-to-analog converter 2903-1 to row 2906-1 or row 2906-3 according to its control signal
  • multiplexor 2904-2 routes the output of digital-to-analog converter 2903-2 to row 2906-2 or row 2906-4 according to its 26 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 control signal, and so forth.
  • a sector can comprise a pair of consecutive rows, and the rows of a sector can be accessed concurrently as no consecutive rows share the same multiplexor although consecutive rows may share a source line and an erase gate line.
  • Figure 30 depicts VMM system 3000, which comprises neural network array 2601 and input block 3010.
  • Input block 3010 comprises row registers 3001-1 through 3001-8, row tag registers 3002-1 through 3002-8 (optional) containing row tag bits, digital to analog converters 3003-1 through 3003-8, multiplexors 3004-1 through 3004-8, and source line pull down circuit 3005 (which can comprise source line pull down circuit 2801 in Figure 28 for each pair of consecutive rows or a comparable circuit).
  • Neural network array 2601 comprises rows 3006-1 through 3006-16. Here, only 16 rows are shown in neural network array 2601, but it is to be understood that neural network array 2601 comprises i rows, where i can be a multiple of 2 and can be less than or greater than 16.
  • the sharing of row registers, row tag registers, and digital-to-analog converters is enabled by the use of multiplexors 3004.
  • a multiplexor 3004 routes an output of a digital-to-analog converter 3003 to one of two rows in neural network array 2601.
  • multiplexor 3004-1 routes the output of digital-to-analog converter 3003-1 to row 3006-1 or row 3006-5 according to its control signal
  • multiplexor 3004-2 routes the output of digital-to-analog converter 3003-2 to row 3006-2 or row 3006-6 according to its control signal, and so forth.
  • a sector comprises consecutive rows.
  • a sector comprises four consecutive rows. In either case, all rows in a sector can be accessed concurrently as no group of two or four consecutive rows share the same multiplexor 3004.
  • Input block 3110 comprises row registers 3101-1 through 3101-4, row tag registers 3102-1 through 3102-4 (optional) containing row tag bits, digital to analog converters 3103-1 through 3103-4, multiplexors 3104-1 through 3104-4, and source line pull down circuit 3105 (which can comprise source line pull down circuit 2801 in Figure 28 for each pair of consecutive rows or a comparable circuit).
  • Neural network array 2601 comprises rows 3106-1 through 3106-16. Here, only 16 rows are shown in neural network array 2601, but it is to be understood that neural network array 2601 comprises i rows, where i can be a multiple of 2 and can be less than or greater than 16.
  • the sharing of row registers, row tag registers, and digital-to-analog converters is enabled by the use of multiplexors 3104.
  • a multiplexor 3104 routes an output of a digital-to-analog converter 3103 to one of four rows in neural network array 2601.
  • multiplexor 3104-1 routes the output of digital-to- analog converter 3103-1 to rows 3106-1, 3106-3, 3106-5, or 3106-7 according to its control signal
  • multiplexor 3104-2 routes the output of digital-to-analog converter 3103-2 to rows 3106- 2, 3106-4, 3106-6, or 3106-8 according to its control signal, and so forth.
  • the rows in a sector that is formed of two consecutive rows can be accessed concurrently as no two consecutive rows share the same multiplexor.
  • adjacent includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space 28 WEST ⁇ 302574590.1 Attorney Docket Number: 351913-980642 disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

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Abstract

Sont divulgués de nombreux exemples de multiplexeurs couplés à des rangées dans un réseau de neurones en réseau. Dans un exemple, un système comprend un réseau de neurones en réseau de cellules de mémoire non volatile comprenant i rangées, i étant un multiple de 2 ; j registres de rangée, j < i ; j convertisseurs numérique-analogiques destinés à convertir j ensembles de données numériques reçues des j registres de rangée en j signaux analogiques ; et j multiplexeurs destinés à acheminer les j signaux analogiques vers un sous-ensemble des i rangées en réponse à un signal de commande.
PCT/US2023/019753 2023-02-01 2023-04-25 Multiplexeurs pour réseau de réseaux neuronaux Ceased WO2024162978A1 (fr)

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KR1020257022222A KR20250119601A (ko) 2023-02-01 2023-04-25 신경망 어레이를 위한 멀티플렉서
CN202380092722.1A CN120604240A (zh) 2023-02-01 2023-04-25 用于神经网络阵列的多路复用器
TW113101487A TWI897198B (zh) 2023-02-01 2024-01-15 具有神經網路陣列的多工器之向量矩陣乘法系統及其操作方法

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
US20170337466A1 (en) 2016-05-17 2017-11-23 Silicon Storage Technology, Inc. Deep Learning Neural Network Classifier Using Non-volatile Memory Array
US10748630B2 (en) 2017-11-29 2020-08-18 Silicon Storage Technology, Inc. High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
WO2022046171A1 (fr) * 2020-08-25 2022-03-03 Silicon Storage Technology, Inc. Opérations simultanées d'écriture et de vérification dans une mémoire neuronale analogique
US20220374161A1 (en) * 2021-05-19 2022-11-24 Silicon Storage Technology, Inc. Output circuit for analog neural memory in a deep learning artificial neural network

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
US20170337466A1 (en) 2016-05-17 2017-11-23 Silicon Storage Technology, Inc. Deep Learning Neural Network Classifier Using Non-volatile Memory Array
US10748630B2 (en) 2017-11-29 2020-08-18 Silicon Storage Technology, Inc. High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
WO2022046171A1 (fr) * 2020-08-25 2022-03-03 Silicon Storage Technology, Inc. Opérations simultanées d'écriture et de vérification dans une mémoire neuronale analogique
US20220374161A1 (en) * 2021-05-19 2022-11-24 Silicon Storage Technology, Inc. Output circuit for analog neural memory in a deep learning artificial neural network

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