[go: up one dir, main page]

WO2025143987A1 - Carte de câblage multicouche - Google Patents

Carte de câblage multicouche Download PDF

Info

Publication number
WO2025143987A1
WO2025143987A1 PCT/KR2024/096718 KR2024096718W WO2025143987A1 WO 2025143987 A1 WO2025143987 A1 WO 2025143987A1 KR 2024096718 W KR2024096718 W KR 2024096718W WO 2025143987 A1 WO2025143987 A1 WO 2025143987A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring
wiring board
layers
electrodes
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2024/096718
Other languages
English (en)
Korean (ko)
Inventor
손동진
배진호
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongwoo Fine Chem Co Ltd
Original Assignee
Dongwoo Fine Chem Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongwoo Fine Chem Co Ltd filed Critical Dongwoo Fine Chem Co Ltd
Publication of WO2025143987A1 publication Critical patent/WO2025143987A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • a multilayer wiring board such as a printed circuit board is used to connect semiconductor chips such as an AP (Application Processor) chip and a memory element included in a smart phone to a circuit.
  • the multilayer wiring board may include a plurality of insulating layers and a plurality of wiring layers that are repeatedly laminated inside.
  • the AP chip or semiconductor chip can be mounted on the multilayer wiring board through soldering, wire connection, etc. using the outermost insulating layer and wiring layer.
  • First terminal electrodes and second terminal electrodes spaced apart from each other and included in the above wiring layers;
  • a multilayer wiring board wherein the coil via is included in one layer of the interlayer connection conductors among the interlayer connection conductors.
  • a multilayer wiring board comprising: first terminal electrodes and lower connection electrodes included in one wiring layer among the above wiring layers; second terminal electrodes and upper connection electrodes included in another wiring layer among the above wiring layers; and coil vias connected in a zigzag manner by the lower connection electrodes and the upper connection electrodes.
  • a multilayer wiring board further comprising a through glass via penetrating the glass substrate in the above 1.
  • FIG. 3 is a schematic cross-sectional view showing one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 4 is a schematic perspective view illustrating implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.
  • FIGS. 6A and 6B are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • Embodiments of the present invention provide a multilayer wiring board including a glass substrate and a wiring laminate.
  • first”, “second”, “third”, “fourth”, “one end”, “the other end”, “top surface”, “bottom surface”, etc. used in this application do not limit absolute positions or orders, and are used in a relative sense to distinguish different components or parts.
  • FIG. 1 is a schematic cross-sectional view showing a multilayer wiring board according to exemplary embodiments.
  • a multilayer wiring board (100) may include a glass substrate (105) and a wiring laminate (107) laminated on the glass substrate (105).
  • the glass substrate (105) may be manufactured from a glass product or bare glass that substantially does not contain organic materials.
  • the term "glass substrate” used in the present application may be used to mean excluding a structure in which glass particles or glass fibers are impregnated into an organic layer.
  • the glass substrate may include tempered glass.
  • the glass substrate (105) may not include any vacancy or etched space (e.g., a recess, groove, cavity, etc.) other than a through via hole for forming a through glass via as described below.
  • any vacancy or etched space e.g., a recess, groove, cavity, etc.
  • the dielectric constant of the glass substrate (105) can be from 1 to 10, for example, from 1 to 7, from 1 to 5, or from 1 to 3 at 1 MHz.
  • the loss tangent (dielectric loss) of the glass substrate (105) can be from 0.00005 to 0.001, for example, from 0.0005 to 0.001.
  • the coefficient of thermal expansion of the glass substrate (105) can be from 1*10 -6 /K to 10 -5 /K, for example, from 1*10 -6 /K to 5*10 -6 /K.
  • the thickness of the glass substrate (105) may be 25 ⁇ m to 1,000 ⁇ m, 50 ⁇ m to 1,000 ⁇ m, 100 ⁇ m to 1,000 ⁇ m, or 500 ⁇ m to 1,000 ⁇ m.
  • the thickness of the glass substrate (105) may be appropriately adjusted within the above range in consideration of the thickness and number of laminates of the wiring laminate (107).
  • a through via hole penetrating the upper and lower surfaces of the glass substrate (105) can be formed through laser drilling, etc.
  • the through via hole can be filled with a metal material through a plating process (e.g., copper plating) to form a through glass via (110).
  • a plating process e.g., copper plating
  • the wiring layers (130) may include a first wiring layer (130a), a second wiring layer (130b), a third wiring layer (130c), a fourth wiring layer (130d), and a fifth wiring layer (130e).
  • the insulating layers (120) may include a first insulating layer (120a), a second insulating layer (120b), a third insulating layer (120c), and a fourth insulating layer (120d).
  • the number of wiring layers (130) and insulating layers (120) illustrated in FIG. 1 is only an example provided for convenience of explanation, and the number of layers and circuit design of the wiring laminate (107) are not limited as illustrated in FIG. 1.
  • the wiring layers (130) can be formed by forming a conductive layer on the upper surface of the glass substrate (105) or on one of the insulating layers (120), and then patterning the conductive layer through an etching process.
  • the conductive layer can be formed through a deposition process such as a plating process or a sputtering process.
  • the wiring layers (130) may be formed through a SAP process (Semi-Additive Process), an M-SAP process (Modified Semi-Additive Process), or a tenting process.
  • SAP process Semi-Additive Process
  • M-SAP process Modified Semi-Additive Process
  • tenting process a tenting process.
  • the insulating layers (120) may each be formed to cover the wiring layer (130).
  • the insulating layers (120) may be formed using a photosensitive resin such as an acrylic resin and/or a thermosetting resin such as an epoxy resin.
  • the wiring laminate (107) may further include interlayer connection conductors (140) that connect the wiring layers (130) to each other.
  • the interlayer connection conductors (140) are disposed between the wiring layers (130) of different levels and refer to conductors formed within the insulating layer (120).
  • the interlayer interconnect conductor (140) may include a wiring-TGV via (140a) that interconnects the through-glass via (110) and the wiring layer (130) (e.g., the second wiring layer (130b)).
  • the wiring-TGV via (140a) may be in direct contact with the through-glass via (110) and the second wiring layer (130b).
  • the wiring laminate (107) and the glass substrate (105) may not include a chip receiving space, such as a cavity, a recess, or a through hole, for inserting/embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), inside. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip receiving space, can be prevented.
  • a chip receiving space such as a cavity, a recess, or a through hole
  • the common interconnect structure (CI) may be provided substantially as a single pillar.
  • a virtual centerline that vertically penetrates the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).
  • the wiring laminate (107) may be provided as an upper wiring/insulating structure of the wiring board (100).
  • the uppermost wiring layer (e.g., the fifth wiring layer (130e)) included in the wiring laminate (107) may include a pad for mounting an electronic component.
  • an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by a soldering or wire bonding method.
  • the TGV connection via (197) and the bottom wiring via (195) may be connected to the motherboard via conductive balls or soldering.
  • FIG. 2 is a schematic cross-sectional view showing an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 2 shows an example implementation of a second passive component (PE2) provided as a register.
  • PE2 second passive component
  • a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a third insulating layer (120c)).
  • An upper insulating layer e.g., a fourth insulating layer (120d)
  • Resistance may be adjusted according to the length of the line pattern (132a), so that a passive element performing a register function may be provided.
  • connection electrode (141) may be formed at each end of the line pattern (132a).
  • the connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a).
  • the terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).
  • the line pattern (132a) is included as a configuration of one of the wiring layers (130) and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).
  • the terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (for example, the uppermost wiring layer (for example, the fifth wiring layer (130e))) and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).
  • the connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).
  • FIG. 3 is a schematic cross-sectional view showing an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 3 shows an example implementation of a first passive component (PE1) provided as a capacitor.
  • PE1 first passive component
  • Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.
  • One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134).
  • the other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).
  • the first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).
  • FIG. 5 is a schematic plan view showing an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 5 shows an example implementation of a third passive component (PE3) provided as an inductor.
  • PE3 third passive component
  • a first coil part (138) is placed on a lower insulating layer (not shown) (for example, a second insulating layer (120b)), and an upper insulating layer (not shown) (for example, a third insulating layer (120c)) may be in contact with the first coil part (138) and cover the first coil part (138).
  • a second coil part (139) may be placed on the upper insulating layer.
  • the first coil portion (138) and the second coil portion (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having a plurality of turns can be implemented.
  • the first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).
  • the above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).
  • Terminal electrodes may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively.
  • the terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).
  • FIGS. 6A and 6B are schematic perspective and cross-sectional views, respectively, illustrating one implementation example of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 6B is a cross-sectional view taken vertically or in the thickness direction along line I-I' of FIG. 6A.
  • one of the wiring layers (130) may include a first terminal electrode (135) (or a first external electrode) and lower connection electrodes (135a).
  • An upper wiring layer (130) with an insulating layer (120) interposed therebetween may include a second terminal electrode (137) (or a second external electrode) and upper connection electrodes (137a).
  • Coil vias (145) may be distributed within the insulating layer (120).
  • the coil vias (145) are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).
  • the first terminal electrode (135) and the second terminal electrode (137) may be connected through coil vias (145) and connection electrodes (135a, 137a) to form a coil-shaped inductor.
  • the coil vias (145) adjacent in the width direction may be connected to each other by the upper connection electrode (137a), and the coil vias (145) adjacent in the diagonal direction with respect to the width direction may be connected to each other by the lower connection electrode (135a). Accordingly, a conductor may be repeated in a zigzag pattern across the lower layer and the upper layer to form a coil.
  • the multilayer wiring board (100) described above can be applied as a circuit board for highly integrated electronic devices such as smart phones, PCs, semiconductor packages, etc.
  • a glass substrate (105) and a passive component embedded wiring laminate can be combined to provide a low-loss, high-Q, high-speed, thin circuit board.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)

Abstract

Cette carte de câblage multicouche comprend : un substrat en verre ; et un stratifié de câblage, qui est disposé sur la surface supérieure du substrat en verre et comprend des couches de câblage, des couches isolantes et des conducteurs de connexion intercouche empilés de manière répétée. Un élément passif formé par les couches de câblage, les conducteurs de connexion intercouche ou les couches isolantes est intégré dans le stratifié de câblage.
PCT/KR2024/096718 2023-12-26 2024-12-11 Carte de câblage multicouche Pending WO2025143987A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020230191137A KR102737210B1 (ko) 2023-12-26 2023-12-26 다층 배선 기판
KR10-2023-0191137 2023-12-26

Publications (1)

Publication Number Publication Date
WO2025143987A1 true WO2025143987A1 (fr) 2025-07-03

Family

ID=93848014

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2024/096718 Pending WO2025143987A1 (fr) 2023-12-26 2024-12-11 Carte de câblage multicouche

Country Status (2)

Country Link
KR (1) KR102737210B1 (fr)
WO (1) WO2025143987A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102737210B1 (ko) * 2023-12-26 2024-12-02 동우 화인켐 주식회사 다층 배선 기판

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134432A (ja) * 2010-12-24 2012-07-12 Dainippon Printing Co Ltd 部品内蔵配線板
US20150289360A1 (en) * 2014-04-02 2015-10-08 Marvell World Trade Ltd. Circuits incorporating integrated passive devices having inductances in 3d configurations and stacked with corresponding dies
KR20160094502A (ko) * 2015-01-30 2016-08-10 주식회사 심텍 칩 내장형 pcb 및 그 제조 방법과, 그 적층 패키지
KR20230025209A (ko) * 2021-08-13 2023-02-21 삼성전자주식회사 반도체 패키지
KR102737210B1 (ko) * 2023-12-26 2024-12-02 동우 화인켐 주식회사 다층 배선 기판

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102565119B1 (ko) 2016-08-25 2023-08-08 삼성전기주식회사 전자 소자 내장 기판과 그 제조 방법 및 전자 소자 모듈

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134432A (ja) * 2010-12-24 2012-07-12 Dainippon Printing Co Ltd 部品内蔵配線板
US20150289360A1 (en) * 2014-04-02 2015-10-08 Marvell World Trade Ltd. Circuits incorporating integrated passive devices having inductances in 3d configurations and stacked with corresponding dies
KR20160094502A (ko) * 2015-01-30 2016-08-10 주식회사 심텍 칩 내장형 pcb 및 그 제조 방법과, 그 적층 패키지
KR20230025209A (ko) * 2021-08-13 2023-02-21 삼성전자주식회사 반도체 패키지
KR102737210B1 (ko) * 2023-12-26 2024-12-02 동우 화인켐 주식회사 다층 배선 기판

Also Published As

Publication number Publication date
KR102737210B1 (ko) 2024-12-02

Similar Documents

Publication Publication Date Title
EP1761119B1 (fr) Condensateur céramique
US8289725B2 (en) Package substrate having embedded capacitor
KR19990063681A (ko) 다중칩 모듈
WO2016099011A1 (fr) Carte de circuit imprimé souple, dispositif électronique la comprenant et procédé de fabrication de carte de circuit imprimé souple
US7791896B1 (en) Providing an embedded capacitor in a circuit board
WO2025143987A1 (fr) Carte de câblage multicouche
WO2019054668A1 (fr) Carte de circuit imprimé et son procédé de fabrication
WO2020096309A1 (fr) Interposeur
WO2012150777A2 (fr) Carte de circuit imprimé et procédé de fabrication de celle-ci
WO2016204504A1 (fr) Module composant de montage en surface
JP2630293B2 (ja) 多層配線基板
WO2025143734A1 (fr) Carte de câblage multicouche
WO2025143659A1 (fr) Substrat en verre et substrat de câblage multicouche le comprenant
US20200185327A1 (en) Sensor
WO2025206875A1 (fr) Substrat en verre et substrat de câblage multicouche le comprenant
WO2025192895A1 (fr) Substrat en verre et substrat de câblage multicouche le comprenant
TWI809624B (zh) 電路板結構
WO2009108030A2 (fr) Carte de circuits imprimés et procès de fabrication de celle-ci
WO2020145616A1 (fr) Carte à circuit imprimé multicouche et procédé pour sa fabrication
WO2025143660A2 (fr) Carte de câblage multicouche
WO2025239579A1 (fr) Carte de circuit imprimé et encapsulation semi-conductrice
WO2023113336A1 (fr) Condensateur céramique
WO2025147128A1 (fr) Carte de circuit imprimé et boîtier de semi-conducteur la comprenant
KR20250144277A (ko) 글래스 기판 및 이를 포함하는 다층 배선 기판
WO2025206836A1 (fr) Carte de circuit et boîtier de semi-conducteur la comprenant

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24913791

Country of ref document: EP

Kind code of ref document: A1