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WO2025143659A1 - Substrat en verre et substrat de câblage multicouche le comprenant - Google Patents

Substrat en verre et substrat de câblage multicouche le comprenant Download PDF

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Publication number
WO2025143659A1
WO2025143659A1 PCT/KR2024/020405 KR2024020405W WO2025143659A1 WO 2025143659 A1 WO2025143659 A1 WO 2025143659A1 KR 2024020405 W KR2024020405 W KR 2024020405W WO 2025143659 A1 WO2025143659 A1 WO 2025143659A1
Authority
WO
WIPO (PCT)
Prior art keywords
glass
wiring
glass substrate
reinforcement layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2024/020405
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English (en)
Korean (ko)
Inventor
손동진
배진호
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dongwoo Fine Chem Co Ltd
Original Assignee
Dongwoo Fine Chem Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dongwoo Fine Chem Co Ltd filed Critical Dongwoo Fine Chem Co Ltd
Publication of WO2025143659A1 publication Critical patent/WO2025143659A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Definitions

  • the present invention relates to a glass substrate and a multilayer wiring board including the same. More specifically, the present invention relates to a glass substrate including a glass body, a conductor, and an insulator, and a multilayer wiring board including the same.
  • An object of the present invention is to provide a glass substrate having improved mechanical stability and electrical efficiency.
  • An object of the present invention is to provide a multilayer wiring board having improved mechanical stability and electrical efficiency.
  • a glass substrate comprising a glass body; a through glass via (TGV) penetrating the glass body; and an organic reinforcement layer formed on a surface of the glass body.
  • TSV through glass via
  • the organic reinforcing layer includes a first organic reinforcing layer formed on the upper surface of the glass body and a second organic reinforcing layer formed on the lower surface of the glass body.
  • the width of the via hole is smaller than the width of the upper surface of the through glass via, the glass substrate.
  • the organic reinforcing layer is a glass substrate having compressive force.
  • a glass substrate including a plurality of through glass vias in the above 1, wherein the distance between adjacent through glass vias is 40 ⁇ m to 1,000 ⁇ m.
  • a multilayer wiring board comprising a glass substrate according to the embodiments described above; and a wiring laminate disposed on an upper surface of the glass substrate and including repeatedly laminated wiring layers, insulating layers, and interlayer connection conductors.
  • the wiring laminate is a multilayer wiring board having a passive element formed by the wiring layers, the interlayer connection conductors or the insulating layers.
  • a multilayer wiring board according to the above 11, wherein the passive component includes at least one of a resistor, a capacitor, and an inductor.
  • interlayer connecting conductor includes the wiring-TGV via and an interlayer via connecting at least one of the wiring layers to each other.
  • a wiring laminate can be laminated on a glass substrate.
  • the glass substrate serves as a support substrate for the wiring laminate, and overall warpage of the multilayer wiring board can be suppressed.
  • a glass substrate can be provided by forming an organic reinforcement layer on a glass body.
  • the organic reinforcement layer has compressive strength and can reduce or buffer stress due to tensile force of the glass body.
  • a through-glass via penetrating the glass body can be formed to electrically connect wiring layers included in the wiring laminate to the through-glass via. Accordingly, electrical signal loss from the lower surface of the glass body to the upper surface of the wiring laminate can be reduced, and high-Q characteristics can be implemented.
  • the organic reinforcement layer (90) may be formed on the surface of the glass body (105). According to exemplary embodiments, the organic reinforcement layer (90) may be formed on the upper surface and the lower surface of the glass body (105), respectively.
  • the organic reinforcement layer (90) may include a first organic reinforcement layer (90a) formed on the upper surface of the glass body (105) and a second organic reinforcement layer (90b) formed on the lower surface of the glass body (105).
  • a passive component embedded in a wiring substrate (200) or a wiring laminate (107) can be designed by utilizing the wiring layers (130), insulating layers (120), and/or interlayer connection conductors (140) included in the wiring laminate (107).
  • the passive component may not include any other configuration/structure other than the wiring layer (130), insulating layer (120), and/or interlayer connection conductor (140).
  • a separate, isolated chip-shaped passive element having a material different from that included in the wiring laminate (107) is not included, and an increase in warpage due to a difference in physical properties, such as a coefficient of thermal expansion, of the chip-shaped passive element can be prevented.
  • the wiring laminate (107) and the glass body (105) may not include a chip receiving space, such as a cavity, a recess, or a through hole, for inserting/embedding an electric element in the form of a chip (e.g., a passive element and an active element such as an IC chip), inside. Accordingly, mechanical defects, such as a decrease in substrate rigidity or warping due to the chip receiving space, can be prevented.
  • a chip receiving space such as a cavity, a recess, or a through hole
  • Through-glass vias (110) can be classified according to the conductive pattern included in the wiring laminate (107) to which they are connected.
  • the through-glass vias (110) can include a first through-glass via (110a), a second through-glass via (110b), and a third through-glass via (110c).
  • a first wiring-TGV via (95a) may be in contact with a first through-glass via (110a), and interlayer connection conductors (140) and wiring layers (130) may be alternately and sequentially laminated on the first wiring-TGV via (95a) to form a common interconnect structure (CI).
  • the common interconnect structure (CI) may provide a shortest electric signal path across the glass body (105) and the wiring laminate (107) in the vertical direction or thickness direction of the wiring substrate (100).
  • the common interconnect structure (CI) may be provided substantially as a single pillar.
  • a virtual centerline that vertically penetrates the first through-glass via (110a) may penetrate the entire common interconnect structure (CI).
  • the second through-glass via (110b) can be connected to a passive component.
  • a passive component For example, it can be connected to a first passive component (PE1) through the first wiring-TGV via (95a).
  • the third through-glass via (110c) can be connected to the wiring layer (130).
  • the third through-glass via (110c) can be electrically connected to the first wiring layer (130a) through the first wiring-TGV via (95a).
  • the common interconnect structure (CI) may further include a second wiring-TGV via (95b) in contact with the lower surface of the through glass via (110).
  • the wiring laminate (107) may be provided as an upper wiring/insulating structure of the wiring board (100).
  • the uppermost wiring layer (e.g., the fourth wiring layer (130d)) included in the wiring laminate (107) may include a pad for mounting an electronic component.
  • an active component such as a semiconductor die, an AP chip, an IC chip, etc. may be mounted on the pad by a soldering or wire bonding method.
  • the lower wiring via (195) may be connected to the motherboard via a conductive ball or soldering.
  • FIG. 6 is a schematic cross-sectional view showing an example implementation of a passive element included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 6 shows an example implementation of a second passive element (PE2) provided as a register.
  • PE2 second passive element
  • a line pattern (132a) included in the wiring layers (130) may be placed on a lower insulating layer (e.g., a second insulating layer (120c)).
  • An upper insulating layer e.g., a third insulating layer (120c)
  • Resistance may be adjusted according to the length of the line pattern (132a), so that a passive element performing a register function may be provided.
  • connection electrode (141) may be formed at each end of the line pattern (132a).
  • the connection electrode (141) may penetrate the upper insulating layer and contact or be connected to the line pattern (132a).
  • the terminal electrode (132b) may be formed on the upper insulating layer and contact or be connected to the connection electrode (141).
  • the line pattern (132a) is included as a configuration of one of the wiring layers (130) and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).
  • the terminal electrode (132b) is also included as a configuration of one of the wiring layers (130) (for example, the uppermost wiring layer (for example, the fourth wiring layer (130d))) and can be formed at the same level with substantially the same material and the same process as the wiring layer (130).
  • the connecting electrode (141) is included as a component of one layer of the interlayer connecting conductor (140) among the interlayer connecting conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connecting conductor (140).
  • FIG. 7 is a schematic cross-sectional view showing an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 7 shows an example implementation of a first passive component (PE1) provided as a capacitor.
  • PE1 first passive component
  • the first electrode (131) and the second electrode (133) can be placed facing each other with an insulating layer (120) therebetween. Accordingly, a passive element of a MIM (Metal-Insulator-Metal) capacitor structure can be implemented.
  • MIM Metal-Insulator-Metal
  • the first electrode (131) and the second electrode (133) are each included as a component of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).
  • the first electrode (131) and the second electrode (133) may be connected to an interlayer connection conductor (140) or a first wiring-TGV via (95a), respectively (see the first passive element (PE1)).
  • the interlayer connection conductor (140) or the first wiring-TGV via (95a) connected to the first electrode (131) and the second electrode (133) may be provided as a terminal electrode or an external electrode.
  • FIG. 8 is a schematic perspective view showing implementation examples of passive components included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 8 shows one implementation example of a capacitor as a passive component.
  • one of the wiring layers (130) may be provided as a first terminal electrode (134) (or a first external electrode), and one of the wiring layers (130) may be provided as a second terminal electrode (136) (or a second external electrode).
  • the first terminal electrode (134) and the second terminal electrode (136) may be included in a wiring layer (130) of the same level.
  • the first terminal electrode (134) and the second terminal electrode (136) may be included in wiring layers (130) of different levels.
  • Internal electrodes may be distributed within the insulating layer (120). For example, first internal electrodes (142) and second internal electrodes (144) may be alternately repeated in the horizontal direction.
  • One end of the first internal electrodes (142) can be in contact with or connected to the first terminal electrode (134).
  • the other end of the second internal electrodes (144) (the ends opposite to the one end of the first internal electrodes (152)) can be in contact with or connected to the second terminal electrode (136).
  • Electrostatic capacitance can be formed in a portion of the insulating layer (120) between the first inner electrode (142) and the second inner electrode (144) that are adjacent to each other. Accordingly, a passive element of a multilayer capacitor structure can be implemented.
  • the first internal electrodes (142) and the second internal electrodes (144) are included as a configuration of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).
  • FIG. 9 is a schematic plan view showing an example implementation of a passive component included in a multilayer wiring board according to exemplary embodiments.
  • FIG. 9 shows an example implementation of a third passive component (PE3) provided as an inductor.
  • PE3 third passive component
  • a first coil part (138) is disposed on a lower insulating layer (not shown) (for example, a first insulating layer (120a)), and an upper insulating layer (not shown) (for example, a second insulating layer (120b)) may be in contact with the first coil part (138) and cover the first coil part (138).
  • a second coil part (139) may be disposed on the upper insulating layer.
  • the first coil portion (138) and the second coil portion (139) can be connected to each other by a coil via (not shown) penetrating the upper insulating layer. Accordingly, a coil-shaped inductor having a plurality of turns can be implemented.
  • the first coil portion (138) and the second coil portion (139) are each included as a configuration of one of the wiring layers (130), and can be formed at the same level using substantially the same material and the same process as the wiring layer (130).
  • the above coil via is included as a component of one layer of the interlayer connection conductor (140) among the interlayer connection conductors (140), and can be formed at the same level with substantially the same material and the same process as the interlayer connection conductor (140).
  • Terminal electrodes may be contacted or connected to the ends of the first coil portion (138) and the second coil portion (139), respectively.
  • the terminal electrodes are included as a component of one layer of the interlayer connection conductors (140) among the interlayer connection conductors (140), and may be formed at the same level using substantially the same material and the same process as the interlayer connection conductor (140).
  • the bending stress of the glass substrates of the examples and comparative examples was measured according to the ASTM C158 standard. Specifically, the bending stress until the through glass via in the glass substrate was removed from the through via hole was measured.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)

Abstract

La présente invention concerne un substrat en verre et un substrat de câblage multicouche. Le substrat en verre comprend : un corps en verre ; un trou d'interconnexion traversant le verre (TGV) pénétrant dans le corps en verre ; et une couche de renforcement organique formée sur une surface du corps en verre. Le substrat de câblage multicouche comprend : le substrat en verre ; et un stratifié de câblage stratifié sur le substrat en verre. Le substrat en verre est disposé en tant que substrat de support pour le stratifié de câblage, ce qui permet de supprimer le gauchissement global du substrat de câblage multicouche, permettant à la couche de renforcement organique d'exercer une force de compression, et de réduire ou d'amortir la contrainte provoquée par la force de traction du corps en verre.
PCT/KR2024/020405 2023-12-26 2024-12-16 Substrat en verre et substrat de câblage multicouche le comprenant Pending WO2025143659A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2023-0191314 2023-12-26
KR1020230191314A KR102819094B1 (ko) 2023-12-26 2023-12-26 글래스 기판 및 이를 포함하는 다층 배선 기판

Publications (1)

Publication Number Publication Date
WO2025143659A1 true WO2025143659A1 (fr) 2025-07-03

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PCT/KR2024/020405 Pending WO2025143659A1 (fr) 2023-12-26 2024-12-16 Substrat en verre et substrat de câblage multicouche le comprenant

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KR (1) KR102819094B1 (fr)
WO (1) WO2025143659A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134432A (ja) * 2010-12-24 2012-07-12 Dainippon Printing Co Ltd 部品内蔵配線板
JP2015070189A (ja) * 2013-09-30 2015-04-13 凸版印刷株式会社 インターポーザーおよびその製造方法、並びにインターポーザーを備える半導体装置およびその製造方法
JP2016157982A (ja) * 2016-05-23 2016-09-01 新光電気工業株式会社 配線基板及びその製造方法
JP6301812B2 (ja) * 2014-11-04 2018-03-28 日本特殊陶業株式会社 配線基板及びその製造方法
JP2019102733A (ja) * 2017-12-06 2019-06-24 凸版印刷株式会社 配線基板、半導体装置、及び配線基板の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102565119B1 (ko) 2016-08-25 2023-08-08 삼성전기주식회사 전자 소자 내장 기판과 그 제조 방법 및 전자 소자 모듈
KR102173721B1 (ko) * 2018-11-09 2020-11-03 단국대학교 천안캠퍼스 산학협력단 뉴트럴 포인트 영역에 글라스층과 버퍼층을 구비한 폴더블 디스플레이용 폴더블 기판
KR102194316B1 (ko) * 2018-11-09 2020-12-22 단국대학교 천안캠퍼스 산학협력단 뉴트럴 포인트 영역에 유리섬유 버퍼층을 구비한 폴더블 디스플레이용 폴더블 기판

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012134432A (ja) * 2010-12-24 2012-07-12 Dainippon Printing Co Ltd 部品内蔵配線板
JP2015070189A (ja) * 2013-09-30 2015-04-13 凸版印刷株式会社 インターポーザーおよびその製造方法、並びにインターポーザーを備える半導体装置およびその製造方法
JP6301812B2 (ja) * 2014-11-04 2018-03-28 日本特殊陶業株式会社 配線基板及びその製造方法
JP2016157982A (ja) * 2016-05-23 2016-09-01 新光電気工業株式会社 配線基板及びその製造方法
JP2019102733A (ja) * 2017-12-06 2019-06-24 凸版印刷株式会社 配線基板、半導体装置、及び配線基板の製造方法

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Publication number Publication date
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