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WO2025023683A1 - Carte de circuit imprimé et boîtier de semi-conducteur la comprenant - Google Patents

Carte de circuit imprimé et boîtier de semi-conducteur la comprenant Download PDF

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Publication number
WO2025023683A1
WO2025023683A1 PCT/KR2024/010563 KR2024010563W WO2025023683A1 WO 2025023683 A1 WO2025023683 A1 WO 2025023683A1 KR 2024010563 W KR2024010563 W KR 2024010563W WO 2025023683 A1 WO2025023683 A1 WO 2025023683A1
Authority
WO
WIPO (PCT)
Prior art keywords
pad
insulating layer
circuit board
protective layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2024/010563
Other languages
English (en)
Korean (ko)
Inventor
정원석
조혜진
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of WO2025023683A1 publication Critical patent/WO2025023683A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings

Definitions

  • the embodiment relates to a semiconductor package.
  • semiconductor packages that place a plurality of semiconductor elements using multiple substrates have been recently provided. These semiconductor packages have a structure in which multiple semiconductor elements are connected to each other in a horizontal and/or vertical direction on the substrate. Accordingly, the semiconductor package has the advantage of efficiently using the mounting area of the semiconductor elements and transmitting high-speed signals through a short signal transmission path between the semiconductor elements.
  • semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers are seeing an increase in the number of semiconductor elements and/or the size of each semiconductor element in line with the trend toward high integration.
  • IoT Internet of Things
  • the concept is expanding to semiconductor chiplets in which the functional parts of the semiconductor elements are divided.
  • An interposer can function as a redistribution layer that gradually increases the width or depth of a circuit pattern as it moves from a semiconductor device to a semiconductor package in order to facilitate interconnection between semiconductor devices and/or semiconductor chiplets, or to interconnect a semiconductor device and a semiconductor package substrate, thereby facilitating electrical signals between the semiconductor device and a semiconductor package substrate having a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.
  • the width and/or spacing of terminals of semiconductor devices and/or semiconductor chiplets is trending toward narrowing. Accordingly, the width and/or spacing of wiring electrodes provided on circuit boards is also becoming smaller.
  • circuit boards are manufactured using the Embedded Trace Substrate (ETS) method, which is advantageous in miniaturizing the width and/or spacing of the top pads connected to semiconductor elements.
  • ETS Embedded Trace Substrate
  • Circuit boards manufactured using the ETS method have a structure in which the top pads are embedded within an insulating layer, and therefore, there is no circuit loss due to etching, which is advantageous in miniaturizing the circuit pitch.
  • a portion of the pad may also be removed, and thus the upper surface of the pad may be positioned lower than the upper surface of the insulating layer. Accordingly, a circuit board manufactured by the conventional ETS method had to manage the height difference between the upper surface of the insulating layer and the upper surface of the pad, and thus had a problem of reduced product yield.
  • the degree of removal of each pad may be different, and thus a height difference may occur in the upper surfaces of the plurality of pads. In this case, a semiconductor element may not be stably attached on the pad of the circuit board, and thus a problem may occur in which the semiconductor element does not operate stably.
  • the embodiment provides a circuit board of a novel structure and a semiconductor package including the same.
  • the embodiment provides a circuit board advantageous for fine pitch and a semiconductor package including the same.
  • the embodiment provides a circuit board having an electrode portion with improved flatness and a semiconductor package including the same.
  • the embodiment provides a circuit board capable of preventing deformation of a pad and a semiconductor package including the same.
  • the embodiment provides a circuit board having improved electrical connection reliability between semiconductor elements and a semiconductor package including the same.
  • the embodiment provides a circuit board including a protective layer capable of alleviating thermal deformation according to a heat cycle and a semiconductor package including the same.
  • the circuit board of the embodiment includes an insulating layer having a recess on an upper surface; a pad disposed within the recess of the insulating layer; and a protective layer disposed on the insulating layer, wherein side surfaces of the pad include a first side in contact with the insulating layer and a second side in contact with the protective layer, and a first vertical length of the first side and a second vertical length of the second side are different from each other.
  • the ratio of the first length to the second length is greater than 1:1 and less than or equal to 1:3.
  • the protective layer has a through hole that overlaps the pad in a vertical direction.
  • the horizontal width of the through hole is smaller than the horizontal width of the pad.
  • circuit board further includes a bonding portion positioned within the through hole of the protective layer.
  • the bonding portion includes a penetration portion arranged within the penetration hole and a protrusion portion arranged on the penetration portion and protruding onto the protective layer.
  • the bonding portion includes a metal material of either copper or tin.
  • the circuit board further includes a barrier layer provided within the through hole of the protective layer and positioned between the pad and the bonding portion.
  • barrier layer and the pad contain different metal materials.
  • the pad comprises copper and the barrier layer comprises nickel.
  • the upper surface of the pad has a concave crevice facing the lower surface of the pad, and the barrier layer includes an extension provided within the crevice of the pad.
  • the vertical length from the upper surface of the pad to the lowest point of the crevice satisfies a range of 5% to 15% of the vertical length from the upper surface of the pad to the lower surface of the pad.
  • the circuit board further includes a via electrode disposed within the insulating layer and connected to the pad, wherein an inclination of a side surface of the pad is closer to a right angle than an inclination of a side surface of the via electrode.
  • At least one of the upper surface of the insulating layer and the lower surface of the protective layer includes at least one of a concave surface and a convex surface.
  • a circuit board includes an insulating layer having a recess on an upper surface; a pad disposed within the recess of the insulating layer; a protective layer disposed on the insulating layer; and a connecting member disposed within the insulating layer, wherein the pads include a first group of pads that vertically overlap with the connecting member and a second group of pads that do not vertically overlap with the connecting member, and side surfaces of each of the pads of the first group and the second group include a first side surface contacting the insulating layer and a second side surface contacting the protective layer, and a first vertical length of the first side surface and a second vertical length of the second side surface are different from each other.
  • the ratio of the first length to the second length is greater than 1:1 and less than or equal to 1:3.
  • the bonding portion is further included, which is disposed on each of the pads of the first group and the second group and includes a penetration portion penetrating the protective layer and a protrusion portion protruding above the protective layer, wherein the width of the penetration portion of the bonding portion is smaller than the width of each of the pads of the first group and the second group.
  • the circuit board further includes a barrier layer disposed between the through-portion of the bonding portion and the pads of each of the first group and the second group, wherein the barrier layer and the pads of each of the first group and the second group include different metal materials, and a width of the barrier layer is smaller than a width of the pads of each of the first group and the second group.
  • the circuit board of the embodiment includes an insulating layer having a recess on an upper surface, a pad disposed within the recess of the insulating layer, and a protective layer disposed on the insulating layer, wherein a side surface of the pad includes a first side surface contacting the insulating layer and a second side surface contacting the protective layer.
  • the circuit board of the embodiment can be manufactured through the ETS method, and thus, at least a portion of the pad positioned on the uppermost part of the circuit board can have a structure in which it is embedded in the upper surface of the insulating layer.
  • the embodiment can have a step difference between the upper surface of the pad and the upper surface of the insulating layer, and further, the upper surface of the pad can be positioned higher than the upper surface of the insulating layer. Accordingly, the embodiment can have at least a portion of the pad embedded in the insulating layer, while at least the remaining portion protrudes above the insulating layer.
  • the embodiment can make it possible to refine the width of the pad and/or the spacing between the pads, and further, form a bonding portion having a uniform height on the pad. Accordingly, the embodiment can make it possible for a semiconductor element to be stably attached to the circuit board, and further, make it possible for the semiconductor element to operate stably. Through this, the embodiment can improve the operational reliability of a product such as a sub to which a semiconductor package is applied.
  • the first vertical length of the first side of the pad and the second vertical length of the second side are different from each other.
  • the ratio of the first length and the second length may be more than 1:1 and less than or equal to 1:3.
  • the embodiment can maximize the flattening improvement effect of the upper surface of a plurality of bonding portions that appears by protruding a part of the pad above the insulating layer, thereby enabling the semiconductor element to be more stably attached to the circuit board.
  • the embodiment can solve the mechanical reliability problem of the pad being detached from the insulating layer, thereby enabling the pad to be stably protected by the insulating layer and the protective layer.
  • the protective layer is provided with a through hole that overlaps the pad in the vertical direction, and the through portion of the barrier layer and the bonding portion is provided within the through hole of the protective layer.
  • the horizontal width of the through hole of the protective layer is smaller than the horizontal width of the pad. Therefore, the horizontal width of the barrier layer and the horizontal width of the through portion of the bonding portion are smaller than the horizontal width of the pad.
  • the embodiment can prevent a shape change of the pad that occurs in the process of forming the barrier layer.
  • the barrier layer may include nickel and may be disposed on the pad through an electroless plating process.
  • the barrier layer may be provided on the pad by applying a substitution plating method.
  • the substitution plating when the substitution plating is performed, a substitution reaction may occur with the pad in the process of plating the barrier layer, and accordingly, the upper surface and side surfaces of the pad may be shaved while the barrier layer is plated.
  • the vertical cross-sectional shape of the pad when the horizontal width of the penetration hole of the protective layer is greater than the width of the pad, the vertical cross-sectional shape of the pad may have a shape in which the width decreases from the upper surface to the lower surface, or the side surface of the pad may have a slope. In this case, it may be difficult to stably place the bonding portion on the pad due to the decrease in the area of the upper surface of the pad, and furthermore, there may be a limit to reducing the width and/or pitch of the bonding portion.
  • the embodiment minimizes shape changes of the pad that occur in the process of plating the barrier layer by ensuring that at least a portion of the upper surface of the pad is covered with a protective layer.
  • the embodiment can maintain the area of the upper surface of the pad, thereby stably positioning the bonding portion on the pad, and further reduce the width and/or pitch of the bonding portion.
  • the upper surface of the insulating layer and the lower surface of the protective layer include at least one of a concave surface and a convex surface corresponding to the curvature of the filler provided in the insulating layer.
  • the upper surface of the pad of the embodiment may be provided with a concave crevice facing the lower surface of the pad.
  • the width of the crevice in the horizontal direction may be larger than the width of the through hole of the upper protective layer.
  • the barrier layer may include an extension portion arranged in the crevice of the pad.
  • the extension portion of the barrier layer is larger than the width of the through hole of the bonding portion.
  • FIG. 1 is a cross-sectional view illustrating the configuration of a circuit board according to the first embodiment.
  • FIG. 2 is a diagram illustrating a configuration of a semiconductor package of the first embodiment having the circuit board illustrated in FIG. 1.
  • Figure 3a is an enlarged cross-sectional view of area R1 of Figure 1.
  • Fig. 3b is a cross-sectional view specifically showing the shape of the interface between the insulating layer and the protective layer of Fig. 3a.
  • FIG. 3c is an enlarged cross-sectional view of area R1 of FIG. 1 according to another embodiment.
  • Figures 4a to 4c are cross-sectional views showing examples of modifications of the bonding portion illustrated in Figure 1.
  • Fig. 5 is a cross-sectional view showing the configuration of a semiconductor package according to the second embodiment.
  • FIGS. 6A to 6H are cross-sectional views for explaining the manufacturing method of the circuit board illustrated in FIG. 1 in process order.
  • each component when it is described as being formed or arranged "above or below” each component, above or below includes not only the cases where the two components are in direct contact with each other, but also the cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as “above or below", it can include the meaning of the downward direction as well as the upward direction based on one component.
  • the electronic device includes a main board (not shown).
  • the main board may be physically and/or electrically connected to various components.
  • the main board may be connected to the semiconductor package of the embodiment.
  • the semiconductor package includes a circuit board having a connection member embedded therein, a semiconductor element, and a connection portion for electrically connecting the semiconductor element and the circuit board.
  • various semiconductor elements may be mounted on the semiconductor package.
  • the semiconductor device may include active components and/or passive components.
  • the active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip.
  • the semiconductor device may be a logic chip, a memory chip, or the like.
  • the logic chip may be a central processor (CPU), a graphics processor (GPU), or the like.
  • the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of any of the foregoing.
  • AP application processor
  • the memory chip may be a stack memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.
  • a volatile memory e.g., DRAM
  • a non-volatile memory e.g., ROM
  • flash memory etc.
  • the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.
  • CSP Chip Scale Package
  • FC-CSP Flip Chip-Chip Scale Package
  • FC-BGA Flip Chip Ball Grid Array
  • POP Package On Package
  • SIP System In Package
  • the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc.
  • the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.
  • FIG. 1 is a cross-sectional view illustrating a configuration of a circuit board according to a first embodiment
  • FIG. 2 is a diagram illustrating a configuration of a semiconductor package according to the first embodiment having the circuit board illustrated in FIG. 1
  • FIG. 3a is an enlarged cross-sectional view of an area R1 of FIG. 1
  • FIG. 3b is a cross-sectional view specifically illustrating the shape of an interface between an insulating layer and a protective layer of FIG. 3a
  • FIG. 3c is an enlarged cross-sectional view of an area R1 of FIG. 1 according to another embodiment
  • FIGS. 4a to 4c are cross-sectional views illustrating modified examples of a bonding portion illustrated in FIG. 1.
  • a semiconductor package includes a circuit board (100) electrically connecting a main board of an electronic device and semiconductor elements (410, 420), a plurality of semiconductor elements (410, 420) mounted on the circuit board (100), and a connection portion (310, 320) electrically connecting the plurality of semiconductor elements (410, 420) and the circuit board (100).
  • the circuit board (100) includes an insulating layer (110), an electrode portion (150), an upper protective layer (160), and a lower protective layer (170).
  • the insulating layer (110) may mean a support substrate of the circuit board (100) on which the electrode portion (150) is formed.
  • the insulating layer (110) is provided in a structure in which first to fourth insulating layers (111, 112, 113, 114) are sequentially laminated.
  • the upper surface of the insulating layer (110) is provided as the upper surface of the first insulating layer (111), and the lower surface of the insulating layer (110) is provided as the lower surface of the fourth insulating layer (114).
  • the electrode portion (150) includes a wiring electrode, a via electrode, a barrier layer (140), and a bonding portion (145).
  • the wiring electrode includes a first wiring electrode (121) disposed on an upper surface of a first insulating layer (111), a second wiring electrode (122) disposed on a lower surface of the first insulating layer (111) or an upper surface of a second insulating layer (112), a third wiring electrode (123) disposed on a lower surface of the second insulating layer (112) or an upper surface of a third insulating layer (113), a fourth wiring electrode (124) disposed on a lower surface of the third insulating layer (113) or an upper surface of a fourth insulating layer (114), and a fifth wiring electrode (125) disposed on a lower surface of the fourth insulating layer (124).
  • the first wiring electrode (121) includes a plurality of pads connected to the via electrode or connected to the bonding portion (145). At this time, the first wiring electrode (121) of Fig. 1 only illustrates a pad connected to the bonding portion (145), and accordingly, the first wiring electrode (121) can be called a 'pad'.
  • the via electrode includes a first via electrode (131) that penetrates the first insulating layer (111) and connects the first wiring electrode (121) and the second wiring electrode (122), a second via electrode (132) that penetrates the second insulating layer (112) and connects the second wiring electrode (122) and the third wiring electrode (123), a third via electrode (133) that penetrates the third insulating layer (113) and connects the third wiring electrode (123) and the fourth wiring electrode (124), and a fourth via electrode (134) that penetrates the fourth insulating layer (114) and connects the fourth wiring electrode (124) and the fifth wiring electrode (125).
  • the electrode portion (150) includes a barrier layer (140) disposed on the first wiring electrode (pad, 121).
  • the electrode portion (150) includes a bonding portion (145) disposed on the barrier layer (140).
  • the bonding portion (145) includes a protrusion portion (145-1) protruding onto the upper protective layer (160) and a penetration portion (145-2) penetrating the upper protective layer (160) and connected to the barrier layer (140).
  • the semiconductor package may include semiconductor elements (310, 320) arranged on a circuit board (100).
  • the semiconductor elements (310, 320) may include a first semiconductor element (310) and a second semiconductor element (320), but are not limited thereto.
  • three or more semiconductor elements may be arranged on the circuit board (100), or one semiconductor element may be arranged.
  • the semiconductor package includes a connection portion (210, 220) arranged between the semiconductor elements (310, 320) and the bonding portion (145) of the circuit board (100).
  • the connection portion (210, 220) connects between the terminals (315, 325) of the semiconductor elements (310, 320) and the bonding portion (145) of the circuit board (100).
  • the connecting portion (210, 220) electrically connects the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using at least one bonding method among wire bonding, solder bonding, and direct metal bonding.
  • the wire bonding method means electrically connecting the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using a conductor such as gold (Au).
  • the solder bonding method electrically connects the electrode portion of the substrate and the terminal (315, 325) of the semiconductor element (310, 320) by using a material including at least one of Sn, Ag, and Cu.
  • the direct bonding method between metals means applying heat and pressure between an electrode portion of a substrate and a terminal (315, 325) of a semiconductor element (310, 320) to recrystallize without the use of solder, wires, conductive adhesives, etc., thereby directly bonding the electrode portion of a substrate and the terminal (315, 325) of the semiconductor element (310, 320).
  • the connecting portion (210, 220) may mean a metal layer formed between the bonding portion (145) of the circuit substrate (100) and the terminal (315, 325) of the semiconductor element (310, 320) by recrystallization.
  • the connecting portions (210, 220) can electrically connect the bonding portions (145) of the circuit board (100) and the terminals (315, 325) of the semiconductor elements (310, 320) by a thermal compression bonding method.
  • the thermal compression bonding method can reduce the volume of the connecting portions (210, 220) and prevent short circuits between a plurality of connecting portions. Therefore, when the terminals (315, 325) of the semiconductor elements (310, 320) and/or the bonding portions (145) of the circuit board (100) have a fine pitch, the thermal compression bonding method can be advantageous.
  • circuit board (100) Each component of the circuit board (100) is specifically described as follows.
  • the laminated first to fourth insulating layers (111, 112, 113, 114) of the circuit board (100) may be formed of an insulating material having ease of process, excellent insulating properties, a function of reducing loss of a signal transmitted through the electrode portion (150), or a function of creating a fine gap between the electrode portions (150).
  • the first to fourth insulating layers (111, 112, 113, 114) may all be formed of the same insulating material, but are not limited thereto, and at least one layer may be formed of an insulating material different from the other insulating layers.
  • ABF Ajinomoto Build-up Film
  • FR-4 BT (Bismaleimide Triazine)
  • PID Photo Image-able Dielectric resin
  • At least one of the first to fourth insulating layers (111, 112, 113, 114) may include a reinforcing member (110F) including at least one of glass fiber and GCP (Glass Core Primer).
  • the reinforcing member (110F) may improve the rigidity of the insulating layer (110), thereby preventing the circuit board (100) and/or the semiconductor package from being bent in a specific direction. If the insulating layer (110) is bent in a specific direction during the process of forming the circuit board (100), the accuracy of the position may decrease during the process of arranging the electrode portion (150), but this problem can be solved as the rigidity of the circuit board (100) is improved.
  • At least one of the first to fourth insulating layers (111, 112, 113, 114) may include a filler (110F) made of an inorganic material.
  • the diameter and content of the filler (110F) may be adjusted in consideration of the coefficient of thermal expansion rate, rigidity, etc. of the insulating layer (110), and to solve problems such as light scattering during a laser process for densely arranging the electrode portions (150).
  • the diameter of the filler (110F) may be applied to 0.1 ⁇ m to 5.0 ⁇ m, and the content may be applied to 30 wt% to 40 wt% or 78 wt% to 85 wt%, but is not limited thereto.
  • the first to fifth wiring electrodes (121, 122, 123, 124, 125) can be designed in various shapes in consideration of the impedance for transmitting signals and power between a plurality of semiconductor elements (310, 320) and the main board of the electronic device and the bending of the circuit board (100).
  • the first to fifth wiring electrodes (121, 122, 123, 124, 125) can be arranged with a high density in consideration of signals and impedance, and can be arranged with a width and interval designed to be within 2 ⁇ m to 10 ⁇ m, respectively, in order to secure adhesive strength with the insulating layer (110) and prevent the problem of peeling.
  • the first to fifth wiring electrodes (121, 122, 123, 124, 125) can be arranged to have various widths and intervals, from a design in which the width is 2 ⁇ m and the interval is 2 ⁇ m, to a design in which the width is 10 ⁇ m and the interval is 10 ⁇ m.
  • the embodiment may apply the width and interval of each wiring electrode differently in consideration of the position and function of each wiring electrode. At this time, such width and interval may mean the width and interval of the trace of the first to fifth wiring electrodes (121, 122, 123, 124, 125).
  • the wiring electrode (125) provided adjacent to the main board of the electronic device can exchange signals with a semiconductor package substrate having a relatively large width and/or spacing.
  • the wiring electrode provided adjacent to a plurality of semiconductor elements (310, 320) can exchange signals with the semiconductor elements (310, 320) having a relatively small width and/or spacing. Accordingly, the first to fifth wiring electrodes (121, 122, 123, 124, 125) can have different widths and/or spacings.
  • the first wiring electrode (121) positioned closer to the semiconductor element (310, 320) may have a relatively small width and/or spacing.
  • the fifth wiring electrode (125) positioned closer to the semiconductor package substrate may have a relatively large width and/or spacing.
  • the embodiment may allow the width and/or spacing of the wiring electrodes to increase along a vertical direction from the upper surface to the lower surface of the insulating layer (110).
  • the wiring electrode positioned on the upper surface of the insulating layer (110) may have the smallest width and/or spacing
  • the wiring electrode on the lower surface of the insulating layer (110) may have the largest width and/or spacing.
  • the embodiment can arrange the first to fifth wiring electrodes (121, 122, 123, 124, 125) so that their widths and/or spacings gradually increase in the direction from the upper surface to the lower surface of the insulating layer (110), thereby enabling more efficient electrical connection between the semiconductor elements (310, 320) and the semiconductor package substrate. Accordingly, the embodiment can minimize signal transmission loss, and thus provide a semiconductor package with excellent communication characteristics. Through this, the embodiment can enable the semiconductor elements to operate more stably, and through this, the semiconductor package can operate more stably.
  • the width and spacing of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above are too fine to arrange the first to fourth via electrodes (131, 132, 133, 134) for vertically connecting the first to fifth wiring electrodes (121, 122, 123, 124, 125), respectively, and thus the width of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above is too narrow to secure the positional alignment of the first to fourth via electrodes (131, 132, 133, 134) or to form the first to fourth via electrodes (131, 132, 133, 134).
  • each of the first to fifth wiring electrodes includes a pad.
  • each pad of the first to fifth wiring electrodes means a wiring electrode that directly contacts the first to fourth via electrodes (131, 132, 133, 134) in each wiring electrode.
  • each pad of the first to fifth wiring electrodes has a width wider than the width of the trace of the first to fifth wiring electrodes (121, 122, 123, 124, 125) described above in order to be connected to the first to fourth via electrodes (131, 132, 133, 134).
  • each pad of the first to fifth wiring electrodes (121, 122, 123, 124, 125) may have a circular structure, and its diameter may be within 30 ⁇ m to 100 ⁇ m.
  • the pad (121) corresponding to the first wiring electrode (121) is the wiring electrode arranged at the uppermost side among the wiring electrodes of the electrode part (150). At this time, at least a portion of the pad (121) is embedded in the upper surface of the insulating layer (110).
  • a recess (110R) is provided in the upper surface of the insulating layer (110), and the pad (121) may be arranged in the recess (110R) provided in the upper surface of the insulating layer (110).
  • the embodiment since the embodiment has a structure in which at least a portion of the pad (121) is embedded in the upper surface of the insulating layer (110), miniaturization of the pad (121) is possible, and accordingly, miniaturization of the bonding part (145) arranged thereon may be possible.
  • the upper surface of the pad (121) may have a step from the upper surface of the insulating layer (110).
  • the upper surface of the pad (121) may be positioned higher than the upper surface of the insulating layer (110). That is, the pad (121) may be provided so as to protrude higher than the upper surface of the insulating layer (110).
  • the bonding portion (145) can be more stably placed on the pad (121), and further, the semiconductor element can be more stably placed on the bonding portion (145).
  • the side surfaces of the pad (121) may be covered with different insulating materials.
  • a portion of the side surface of the pad (121) may be covered with an insulating layer (110).
  • the remaining portion of the side surface of the pad (121) may be covered with an upper protective layer (160).
  • the embodiment controls the length of the portion of the side surface of the pad (121) covered with the insulating layer (110) and the portion covered with the upper protective layer (160), thereby forming a bonding portion (145) having a uniform thickness on the upper surfaces of the plurality of pads, while solving the problem of the plurality of pads being detached from the insulating layer (110). This will be described in more detail below.
  • the barrier layer (140) is disposed on the pad (121).
  • the barrier layer (140) includes a different metal material from the pad (121).
  • the barrier layer (140) may include nickel.
  • the adhesion between the bonding portion (145) and the pad (121) can be improved, and further, the diffusion of an intermetallic compound formed by the bonding of the bonding portion (145) and a connecting portion such as solder can be prevented.
  • the intermetallic compound has a problem of poor mechanical and electrical reliability.
  • the bonding portion (145) includes copper, mechanical reliability problems such as crack problems and/or deterioration of electrical characteristics caused by the intermetallic compound and/or electrical reliability problems can be further aggravated.
  • the barrier layer (140) contains nickel, it is possible to prevent the intermetallic compound from penetrating into the interface between the pad (121) and the upper insulating layer (160), thereby solving the problem of peeling that occurs due to the decrease in the bonding strength therebetween.
  • the bonding portion (145) is directly disposed on the pad (121), oxidation of the pad (121) may occur during the manufacturing process of the circuit board (100), which may decrease the bonding strength between the pad (121) and the bonding portion (145). Therefore, the embodiment arranges a barrier layer (140) between the pad (121) and the bonding portion (145) to prevent oxidation of the pad (121) while improving the bonding strength between the pad (121) and the bonding portion (145).
  • the circuit board (100) may be subject to stress due to expansion and/or contraction according to the heat cycle, and this may be concentrated at the interface between the pad (121) and the bonding portion (145).
  • a barrier layer (140) is placed between the pad (121) and the bonding portion (145)
  • the bonding strength between them can be improved, thereby preventing cracks due to stress, and further improving the electrical and mechanical reliability of the semiconductor package.
  • the electrode portion (150) includes a bonding portion (145).
  • the bonding portion (145) is disposed on the upper protective layer (160).
  • the bonding portion (145) may be a bonding area where a connection portion (210, 220) for electrically connecting a circuit board (100) and terminals (315, 325) of semiconductor elements (310, 320) are disposed.
  • the bonding portion (145) has a protrusion portion (145-1) disposed on the upper protective layer (160) and a penetration portion (145-2) penetrating the upper protective layer (160). The penetration portion (145-2) of the bonding portion (145) is connected to the barrier layer (140).
  • the bonding portion (145) has a protrusion (145-1) protruding on the upper protective layer (160), and based on this, thermal compression bonding is used to reduce the volume of the connecting portion (210, 220) such as solder while preventing short circuits between multiple bonding portions (145).
  • An upper protective layer (160) is disposed on the upper surface of the insulating layer (120), and a lower protective layer (170) is disposed on the lower surface of the insulating layer (120).
  • the upper protective layer (160) and the lower protective layer (170) can protect the pad from external moisture or contaminants, and can be provided with a photosensitive material and/or a solder resist to prevent a short circuit problem between the connecting portions (210, 220) when bonding between the semiconductor element and the circuit board (100) and/or the main board and the circuit board (100).
  • the upper protective layer (160) and the lower protective layer (170) can apply a photosensitive solder resist, for example.
  • a plurality of terminals for connecting to a circuit board (100) such as a semiconductor element (310, 320) and/or a main board of an electronic device can be arranged at a high density, and when a plurality of terminals and a bonding portion (145) of a circuit board (100) are joined, solder can be used.
  • solder When solder is used, a solder short-circuit problem may occur between terminals having a high density, and thus, in order to solve this short-circuit problem, a solder resist having poor wettability with the solder is arranged to prevent diffusion or movement of the solder, thereby preventing the solder short-circuit problem between the terminals.
  • the upper protective layer (160) and the lower protective layer (170) can be arranged with different thicknesses in consideration of the warpage or coefficient of thermal expansion of the circuit board (100).
  • the upper protective layer (160) is provided to surround at least a portion of the side surface of the pad (121). In addition, the upper protective layer (160) is provided to cover at least a portion of the upper surface of the pad (121). Specifically, the upper surface of the upper protective layer (160) is positioned higher than the upper surface of the pad (121). In addition, the lower surface of the upper protective layer (160) is positioned lower than the upper surface of the pad (121) and higher than the lower surface of the pad (121). That is, the interface between the lower surface of the upper protective layer (160) and the upper surface of the insulating layer (110) is positioned between the upper and lower surfaces of the pad (121).
  • a pad (121) is arranged in a recess (110R) provided on the upper surface of the insulating layer (110).
  • the vertical depth of the recess (110R) may be smaller than the vertical thickness of the pad (121). Accordingly, at least a portion of the pad (121) is arranged within the recess (110R) of the insulating layer (110), and the remaining portion of the pad (121) protrudes above the insulating layer (110).
  • an upper protective layer (160) is placed on the insulating layer (110). At this time, the upper protective layer (160) is placed to cover a part of the side of the pad (121) that is not covered by the insulating layer (110).
  • the pad (121) includes an upper surface (121T) and a lower surface (121B).
  • the pad (121) includes a side surface (121S) connecting the upper surface (121T) and the lower surface (121B).
  • the side surface (121S) of the pad (121) includes a first side surface (121S1) in contact with the insulating layer (110) and a second side surface (121S2) in contact with the upper protective layer (160).
  • the first side surface (121S1) of the pad (121) is closer to the lower surface (121B) of the pad (121) and extends from the lower surface (121B) of the pad (121) toward the upper surface (121T).
  • the second side surface (121S2) of the pad (121) is closer to the upper surface (121T) of the pad (121) and extends from the upper surface (121T) of the pad (121) toward the lower surface (121B) of the pad (121).
  • the first side surface (121S1) and the second side surface (121S2) of the pad (121) are directly connected to each other.
  • direct connection does not mean that the first side (121S1) and the second side (121S2) are different sides (e.g., the left side and the right side) of the pad (121), but rather that one side is divided into a plurality of parts along the vertical direction.
  • the first side (121S1) of the pad (121) has a first length (L1) in the vertical direction.
  • the second side (121S2) of the pad (121) has a second length (L2) in the vertical direction.
  • the first length (L1) and the second length (L2) may be different from each other.
  • the embodiment improves the flatness of the upper surface of the plurality of pads (121) by controlling the first length (L1) and the second length (L2) so that the bonding portion (145) having a uniform height is arranged on the plurality of pads (121) without causing mechanical reliability in which the pads (121) are detached from the insulating layer (110).
  • the first length (L1) may be smaller than the second length (L2).
  • the vertical length of the first side (121S) in contact with the insulating layer (110) on the side (121S) of the pad (121) may be smaller than the vertical length of the second side (121S2) in contact with the upper protective layer (160). This is to prevent cracks from occurring at the contact interface between the pad (121) and the barrier layer (140) due to stress acting on the circuit board (100).
  • the coefficient of thermal expansion of the upper protective layer (160) may be greater than the coefficient of thermal expansion of the insulating layer (110), and the upper protective layer (160) may shrink or expand more than the insulating layer (110) when expanding and/or shrinking according to the heat cycle. At this time, when stress occurs in the upper protective layer (160) due to expansion and/or shrinking according to the heat cycle, this may act in a horizontal direction toward the interface between the upper protective layer (160) and the insulating layer (110).
  • the embodiment makes the first length (L1) smaller than the second length (L2), and based on this, the stress acts in a horizontal direction closer to the lower surface (121B) than the upper surface (121T) of the pad (121), thereby improving mechanical reliability problems such as cracks.
  • the ratio of the first length (L1) to the second length (L2) may be greater than 1:1 and less than or equal to 1:3.
  • the ratio of the first length (L1) to the second length (L2) is less than or equal to 1:1, stress according to the heat cycle may be concentrated at the interface between the pad (121) and the barrier layer (140), which may cause cracks to occur.
  • the ratio of the first length (L1) to the second length (L2) is less than or equal to 1:1, the protrusion height of the pad (121) from the insulating layer (110) may be insufficient, and thus, the flattening improvement effect of the plurality of bonding portions (145) that appear by protruding a portion of the pad (121) above the insulating layer (110) may be insufficient.
  • the upper protective layer (160) is provided with a through hole that overlaps the pad (121) in a vertical direction, and the through part (145-2) of the barrier layer (140) and the bonding part (145) is provided within the through hole of the upper protective layer (160).
  • the embodiment can prevent a shape change of the pad (121) that occurs in the process of forming the barrier layer (140). Therefore, the inclination of the side surface (121S) of the pad (121) of the embodiment can be closer to a right angle than the inclination of the side surface of the first via electrode (131).
  • the barrier layer (140) may include nickel and may be disposed on the pad (121) through an electroless plating process. Specifically, the barrier layer (140) may be provided on the pad (121) by applying a substitution plating method. At this time, when substitution plating is performed, a substitution reaction may occur with the pad (121) in the process of plating the barrier layer (140), and accordingly, the upper surface and side surfaces of the pad (121) may be cut while the barrier layer (140) is plated.
  • the vertical cross-sectional shape of the pad (121) may have a shape in which the width decreases from the upper surface to the lower surface, or the side surface of the pad (121) may have an incline.
  • the embodiment minimizes the shape change of the pad (121) that occurs in the process of plating the barrier layer (140) by ensuring that at least a portion of the upper surface of the pad (121) is covered with the upper protective layer (160).
  • the embodiment can maintain the area of the upper surface of the pad (121), thereby ensuring that the bonding portion is stably arranged on the pad (121), and further reducing the width and/or pitch of the bonding portion (145).
  • the through hole of the upper protective layer (160) may be formed through a laser process. Accordingly, the through hole provided in the upper protective layer (160) may include a curved portion whose width becomes narrower at a portion adjacent to the pad (121).
  • the through hole of the upper protective layer (160) may be formed using a laser beam having a Gaussian distribution, and thus may have a shape corresponding to the laser beam having a Gaussian distribution.
  • the through hole of the upper protective layer (160) may include a first portion that is provided adjacent to the upper surface of the upper protective layer (160) and whose width has little change toward the lower surface of the upper protective layer (160), and a second portion that is provided adjacent to the lower surface of the upper protective layer (160) below the first portion and corresponding to the curved portion whose width becomes narrower toward the lower surface of the upper protective layer (160).
  • the through-hole (145-2) of the bonding portion (145) may include a curved portion that is arranged in the second portion of the through-hole of the upper protective layer (160) and has a narrow width.
  • the embodiment may form the through-hole of the upper protective layer (160) through a laser process, thereby reducing the width of the through-hole and the pitch between the plurality of through-holes provided in the upper protective layer (160).
  • the width and pitch of the through-hole that may be formed through an exposure and development process may exceed 40 um.
  • the embodiment may form the through-hole in the upper protective layer (160) through a laser process, thereby reducing the width and pitch of the through-hole to 30 um or less, 25 um or less, or further to 20 um or less.
  • the penetration portion (145-2) of the bonding portion (145) may include a curved portion with a width that is rapidly narrowed in an area adjacent to the pad (121) formed by a laser beam with a Gaussian distribution.
  • the upper surface of the insulating layer (110) may be provided with concave and convex portions.
  • the lower surface of the upper protective layer (160) may be provided with convex and concave portions. This may be to ensure that the first side surface (121S1) of the pad (121) is covered with the insulating layer (110) and the second side surface (121S2) of the pad (121) is covered with the upper protective layer (160).
  • the embodiment forms a pad (121) of a circuit board (100) by applying the ETS method.
  • the height of the upper surface of the pad (121) is lower than or equal to the height of the upper surface of the insulating layer (110).
  • the difficulty of the process of forming the bonding portion (145) on the pad (121) may increase, and accordingly, a height deviation of a plurality of bonding portions (145) may occur due to a process error in the process of plating the bonding portion (145).
  • the embodiment arranges the pad (121) to protrude above the insulating layer (110) by a thickness corresponding to the second length (L2) of the second side (121S2) of the pad (121), and minimizes the height deviation of the bonding portion (145) based on this.
  • the SAP method can be applied so that the pad (121) protrudes entirely over the insulating layer (110), but when the pad (121) is formed using the SAP method, there is a limit to miniaturization of the width and/or spacing of the pad (121), and thus there is a limit to miniaturizing the circuit board (100).
  • a process of removing a portion of the upper surface of an insulating layer (110) is performed, thereby making the upper surface of the insulating layer (110) positioned lower than the upper surface of a pad (121).
  • the insulating layer (110) is provided with a filler (110F). And, in the process of removing a part of the upper surface of the insulating layer (110), the filler (110F) may be exposed on the insulating layer (110) or may be removed from the insulating layer (110). In addition, when the process of removing a part of the upper surface of the insulating layer (110) is performed, the upper surface of the insulating layer (110) may be removed convexly along the curvature of the filler (110F) provided therein.
  • At least a portion (110F1) of the filler (110F) provided in the insulating layer (110) can protrude above the insulating layer (110), and accordingly, the protruding filler (110F1) can be covered with the upper protective layer (160).
  • a concave surface (IS1) corresponding to a location where the filler (110F) has escaped i.e., a removed location
  • a convex surface corresponding to the concave surface (IS1) may be provided on the lower surface of the upper protective layer (160).
  • a convex surface (IS2) may be provided on the upper surface of the insulating layer (110) along the curvature of the filler (110F), and accordingly, a concave surface corresponding to the convex surface (IS2) may be provided on the lower surface of the upper protective layer (160).
  • the embodiment provides a convex surface and a concave surface at the interface between the upper surface of the insulating layer (110) and the lower surface of the upper protective layer (160), thereby increasing the contact area between the insulating layer (110) and the upper protective layer (160). Therefore, the embodiment can solve the problem of the upper protective layer (160) being peeled off from the insulating layer (110), and thus improve the mechanical reliability of the circuit board and the semiconductor package.
  • the upper surface of the pad (121) of the embodiment may be provided with a concave crevice (121C) facing the lower surface of the pad (121).
  • the horizontal width of the crevice (121C) may be larger than the width of the through hole of the upper protective layer (160).
  • the barrier layer (1140) may include an extension portion (1140C) arranged within the crevice (121C) of the pad (121).
  • the extension portion (1140C) of the barrier layer (1140) is larger than the width of the through portion (145-2) of the bonding portion (145).
  • the embodiment can enable the extension portion (1140C) of the barrier layer (1140) to function as an anchor to firmly connect the bonding portion (145) and the pad (121), thereby further enhancing the bonding strength between the bonding portion (145) and the pad (121).
  • the third length (L3) in the vertical direction of the crevice (121C) provided on the upper surface of the pad (121) may be present.
  • the third length (L3) may mean the vertical length from the upper surface of the pad (121) to the lowermost end of the crevice (121C).
  • the third length (L2) may satisfy a range of 5% to 15% of the length from the upper surface to the lower surface of the pad (121). If the third length (L3) is less than 5% of the length of the pad (121), the anchoring effect through the extension portion (1140C) of the barrier layer (1140) may be insufficient.
  • the third length (L3) exceeds 15% of the length of the pad (121), the flatness of the upper surface of the barrier layer (1140) may be deteriorated, and further, the flatness of the bonding portion (145) may be deteriorated.
  • the bonding portion (1450) of the embodiment may only have a penetration portion that penetrates the upper protective layer (160).
  • the bonding portion (1450) may not protrude above the upper protective layer (160). This may be achieved by changing the material constituting the bonding portion (1450).
  • the bonding portion (145) illustrated in FIGS. 1 to 3c may be formed of a metal material including copper.
  • the bonding portion (1450) of FIG. 4a may include tin. That is, the embodiment may form the bonding portion (1450) by plating tin on the barrier layer (1140). Through this, the embodiment may enable the semiconductor element to be more stably mounted on the bonding portion (1450).
  • the embodiment can perform a process (e.g., coin process) to flatten the bonding portion (1450) after it is formed, thereby allowing the upper surface of the bonding portion (1450) to be positioned on the same plane as the upper surface of the upper protective layer (160).
  • a process e.g., coin process
  • the bonding portion (2450) of the embodiment may include a comment.
  • FIG. 4b may perform a coin process so that the bonding portion (2450) has a height higher than the upper protective layer (160), and through this, the bonding portion (2450) includes a penetration portion (2451) penetrating the upper protective layer (160) and a protrusion (2452) disposed on the penetration portion (2451) and protruding from the upper protective layer (160) toward the upper protective layer.
  • the protrusion (2452) may have a slope whose width gradually decreases from the upper surface to the lower surface.
  • the embodiment may enable the semiconductor element to be more stably settled on the protrusion (2452), and since the protrusion (2452) has a slope whose width decreases, it may solve an electrical short-circuit problem in which a plurality of adjacent protrusions are connected to each other.
  • the bonding portion (3450) of the embodiment may include a comment.
  • FIG. 4c may not perform a coin process after forming the bonding portion (3450).
  • the bonding portion (3450) includes a penetration portion (3451) penetrating the upper protective layer (160) and a protrusion portion (3452) disposed on the penetration portion (3451) and protruding onto the upper protective layer (160).
  • the upper surface of the protrusion portion (2452) may have a convex curve.
  • Fig. 5 is a cross-sectional view showing the configuration of a semiconductor package according to the second embodiment.
  • the circuit board includes a connecting member (400) embedded in an insulating layer (110).
  • the connecting member (400) partially overlaps with semiconductor elements (310, 320) arranged on the circuit board (100) in a vertical direction.
  • the connecting member (400) electrically connects a part of a terminal (315) of a first semiconductor element (310) and a part of a terminal (325) of a second semiconductor element (320).
  • the connecting member (400) may be formed of a material similar to the semiconductor element, such as silicon, or may be formed of an organic material, such as a photosensitive resin or a thermosetting resin.
  • a plurality of semiconductor devices having different functions such as a CPU and GPU, a GPU and HBM, or a chiplet unit separated according to functionality and/or pitch, may be mounted on a circuit board, and a connecting member (400) may have the function of horizontally electrically connecting them.
  • the electrode portion of the circuit board can be largely divided into three groups.
  • the electrode portions arranged on the connecting member (400) can be divided into three groups.
  • the electrode portion includes a first group of electrode portions (151) that are vertically overlapped with a connecting member (400). At this time, the first group of electrode portions includes pads, a barrier layer, and a bonding portion that are vertically overlapped with the connecting member (400).
  • the electrode portion includes a second group of electrode portions (152) that are vertically overlapped with the first semiconductor element while not vertically overlapping with the connecting member (400). At this time, the second group of electrode portions (152) include pads, a barrier layer, and a bonding portion.
  • the electrode portion includes a third group of electrode portions (153) that are vertically overlapped with the second semiconductor element while not vertically overlapping with the connecting member (400). At this time, the third group of electrode portions (153) include pads, a barrier layer, and a bonding portion.
  • the circuit board is arranged within the insulating layer (110) and further includes an adhesive member (420) connecting the pad (121) and the connecting member (400).
  • the connecting member (400) is provided with a connecting electrode (410) on an upper surface.
  • the adhesive member (420) may be provided between the lower surface of the pad of the first group of electrode parts (151) and the upper surface of the connecting electrode (410) of the connecting member (400).
  • FIGS. 6A to 6H are cross-sectional views for explaining the manufacturing method of the circuit board illustrated in FIG. 1 in process order.
  • the embodiment can prepare an insulating member that serves as a basis for manufacturing a circuit board.
  • the insulating member can be a carrier board.
  • the insulating member can include a carrier insulating layer (CB1) and a carrier metal layer (CB2).
  • the carrier metal layer (CB2) is a seed layer used for electroplating the pad (121) of the embodiment.
  • the embodiment configures the carrier metal layer (CB2) with a metal material that does not cause etching loss of the pad (121) in a process of removing the carrier metal layer (CB2) by etching after manufacturing the circuit board (100).
  • the carrier metal layer (CB2) may include a metal material different from the metal material configuring the pad (121).
  • the carrier metal layer (CB2) may include nickel, but is not limited thereto.
  • the embodiment may perform a process of forming a first wiring electrode (121) under a carrier metal layer (CB2).
  • the embodiment may perform a process of forming a first wiring electrode (121) by laminating a dry film having an opening under a carrier metal layer (CB2) and performing electrolytic plating within the opening of the dry film.
  • the first wiring electrode (121) may mean a pad (121).
  • the embodiment may perform a process of laminating a first insulating layer (111) under a carrier metal layer (CB2). For example, the embodiment may perform a process of forming a first insulating layer (111) covering the first wiring electrode (121) under the carrier metal layer (CB2). Thereafter, the embodiment may perform a process of forming a first via electrode (131) penetrating the first insulating layer (111) and a second wiring electrode (122) disposed on a lower surface of the first insulating layer (111).
  • the embodiment can perform a process of manufacturing a multilayer circuit board by repeating the process of FIG. 6c.
  • the embodiment can proceed with a process of separating and removing the carrier insulating layer (CB1).
  • the embodiment can perform a process of removing the carrier metal layer (CB2) by etching.
  • the carrier metal layer (CB2) includes a different metal material from the pad (121), and thus, the pad (121) is not removed when the carrier metal layer (CB2) is etched. Accordingly, the upper surface of the pad (121) and the upper surface of the first insulating layer (111) can be maintained in a state of being arranged on the same plane.
  • the embodiment may perform a process of removing a portion of an upper region of the first insulating layer (111), thereby allowing the upper surface of the first insulating layer (111) to be positioned lower than the upper surface of the pad (121).
  • the embodiment may perform plasma etching, thereby performing a process of thinning the thickness of the first insulating layer (111).
  • the embodiment may perform etching so that a ratio of a vertical length of a side surface of the pad (121) exposed through the etching of the first insulating layer (111) and a vertical length of a side surface of the pad (121) covered with the first insulating layer (111) satisfies a preset range.
  • the embodiment has a ratio of the vertical length of the side surface of the pad (121) covered with the first insulating layer (111) and the vertical length of the side surface of the pad (121) exposed by etching of the first insulating layer (111) in a range of more than 1:1 and less than or equal to 1:3.
  • the embodiment may perform a process of laminating an upper protective layer (160) covering a pad (121) on a first insulating layer (111).
  • the embodiment may form a through hole in the upper protective layer (160) that overlaps the upper surface of the pad (121) in a vertical direction.
  • the width of the through hole provided in the upper protective layer (160) is smaller than the width of the pad (121), and thus, at least a portion of the upper surface of the pad (121) may be covered with the upper protective layer (160).
  • the embodiment may proceed with a process of forming a barrier layer (140) within the through hole of the upper protective layer (160).
  • the embodiment may proceed with a process of forming a bonding portion (145) having a through portion positioned on the barrier layer (1140) within the through hole of the upper protective layer (160) and a protrusion protruding onto the upper protective layer (160).
  • a circuit board having the characteristics of the invention described above when used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply.
  • a circuit board having the characteristics of the invention when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect a semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current or electrical short circuits between terminals, or electrical open circuits of terminals supplying to semiconductor chips.
  • problems such as leakage current or electrical short circuits between terminals, or electrical open circuits of terminals supplying to semiconductor chips.
  • the circuit board having the characteristics of the invention described above can maintain the stable function of an IT device or home appliance, so that the entire product and the circuit board to which the invention is applied can achieve functional integration or technical interconnectivity with each other.
  • a circuit board having the characteristics of the invention described above When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of distortion of a signal transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and solve the problem of leakage current or electrical short circuit between terminals, or the problem of electrical open of a terminal supplied to the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Une carte de circuit imprimé d'un mode de réalisation comprend : une couche isolante ayant un évidement dans sa surface supérieure ; un tampon disposé dans l'évidement de la couche isolante ; et une couche de protection disposée sur la couche isolante : la surface latérale du tampon comprenant une première surface latérale en contact avec la couche isolante, et une seconde surface latérale en contact avec la couche de protection ; et une première longueur de la première surface latérale dans la direction verticale étant différente d'une seconde longueur de la seconde surface latérale dans la direction verticale.
PCT/KR2024/010563 2023-07-21 2024-07-22 Carte de circuit imprimé et boîtier de semi-conducteur la comprenant Pending WO2025023683A1 (fr)

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KR10-2023-0095498 2023-07-21
KR1020230095498A KR20250014840A (ko) 2023-07-21 2023-07-21 회로 기판 및 이를 포함하는 반도체 패키지

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WO2025023683A1 true WO2025023683A1 (fr) 2025-01-30

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