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WO2025147154A1 - Carte de circuit imprimé et boîtier de semi-conducteur la comprenant - Google Patents

Carte de circuit imprimé et boîtier de semi-conducteur la comprenant Download PDF

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Publication number
WO2025147154A1
WO2025147154A1 PCT/KR2025/000158 KR2025000158W WO2025147154A1 WO 2025147154 A1 WO2025147154 A1 WO 2025147154A1 KR 2025000158 W KR2025000158 W KR 2025000158W WO 2025147154 A1 WO2025147154 A1 WO 2025147154A1
Authority
WO
WIPO (PCT)
Prior art keywords
pad
circuit board
build
layer
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2025/000158
Other languages
English (en)
Korean (ko)
Inventor
남일식
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LG Innotek Co Ltd
Original Assignee
LG Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020240194508A external-priority patent/KR20250106696A/ko
Application filed by LG Innotek Co Ltd filed Critical LG Innotek Co Ltd
Publication of WO2025147154A1 publication Critical patent/WO2025147154A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

Definitions

  • the invention relates to a circuit board and a semiconductor package including the same.
  • semiconductor packages that place a plurality of semiconductor elements using multiple substrates have been recently provided. These semiconductor packages have a structure in which multiple semiconductor elements are connected to each other in a horizontal direction and/or a vertical direction on a circuit board. Accordingly, the semiconductor package has the advantage of efficiently using the mounting area of the semiconductor elements and transmitting high-speed signals through a short signal transmission path between the semiconductor elements.
  • the horizontal direction means the top (above) or bottom (below) of each component
  • the horizontal direction means the direction perpendicular to the vertical direction
  • the horizontal direction may include a first horizontal direction and a second horizontal direction.
  • the first horizontal direction may mean the X-axis
  • the second horizontal direction may mean the Y-axis
  • the vertical direction may mean the Z-axis.
  • the first horizontal direction may mean the direction along the azimuth
  • the second horizontal direction may mean the direction toward the radius, and these may be selectively used in combination.
  • the direction along the azimuth may be referred to as the circumferential direction
  • the direction toward the radius may be referred to as the centrifugal direction.
  • component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when component A is described as being exposed from component B, it should be understood to mean that component A is at least partially covered by component C.
  • a component A when it is described that a component A is in 'contact' with a component B, it may include not only the case where the component is in 'direct contact' with the other component, but also the case where the component is 'in contact' by another component between the component and the other component. Thus, if the component A is to be understood to be in 'direct contact' with the component B, it is described as being in 'direct contact'.
  • configuration A is 'fixed' to configuration B
  • configuration A is not only directly coupled and fixed to configuration B, but also indirectly fixed to configuration B through configuration C and/or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when it should be understood that configuration A is 'directly fixed' to configuration B, it is described as 'directly fixed'.
  • each component when it is described as being formed or arranged "above or below” each component, above or below includes not only the cases where the two components are in direct contact with each other, but also the cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as “above or below", it can include the meaning of the downward direction as well as the upward direction based on one component.
  • FIG. 1 is a cross-sectional view of a circuit board (100) according to an embodiment.
  • the circuit board (100) according to the embodiment may include a build-up insulating member (120), a build-up wiring body, and a protective layer (116, 117).
  • the build-up structure including the build-up insulating member (120), the build-up wiring body, and the protective layer (116, 117) may be referred to as a build-up structure, but is not limited thereto.
  • the build-up structure may function as a laminated circuit for connecting to electronic components/main boards, etc.
  • the build-up insulation (120) includes a single or multiple laminated insulation layers and provides insulation properties between the build-up wiring bodies.
  • the build-up insulation (120) may be referred to as a build-up insulator.
  • the build-up insulation (120) may include, but is not limited to, a first build-up insulation (111), a second build-up insulation (112), and a third build-up insulation (113).
  • One of the build-up insulation members (120) may be a core layer.
  • the first build-up insulation member (111) located at the center of the build-up insulation member (120) may be a core layer, but is not limited thereto.
  • the core layer can secure the overall mechanical rigidity of the circuit board and suppress warpage. Since it can suppress both warpage occurring during the process and warpage occurring during the operation of the product, the core layer can improve the yield of the circuit board and improve the reliability of the circuit board.
  • the core layer may include a reinforcing member such as glass fiber extending in a horizontal direction and a resin wrapping the same, and the mechanical rigidity may be controlled according to the density of the reinforcing member.
  • the reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided in the resin layer.
  • the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between the via electrodes can be easily controlled. In addition, it may have an advantage of being able to reduce the thickness of the circuit board due to higher mechanical rigidity than a resin including glass fiber.
  • the core layer may be freely selected and used as long as it is a material that can secure mechanical rigidity without being limited to what was described above in consideration of yield, price, etc.
  • the build-up insulation (120) may include an upper build-up insulation disposed on an upper surface of the core layer, and a lower build-up insulation disposed on a lower surface of the core layer.
  • the build-up insulation (120) may include a first build-up insulation (111) which is a core layer, a second build-up insulation (112) which is an upper build-up insulation disposed on an upper surface of the core layer, and a third build-up insulation (113) which is a lower build-up insulation disposed on a lower surface of the core layer.
  • the insulation layer of the build-up insulation member (120) may be a thermosetting material and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.
  • ABSF Ajinomoto build-up film
  • epoxy resin epoxy resin
  • polyimide polyimide
  • phenolic resin phenolic resin
  • bismaleimide triazine (BT) resin bismaleimide triazine (BT) resin
  • silicone resin silicone resin
  • a photocurable resin can form a fine pattern of through holes or openings through an exposure and development process, and can eliminate a stopper required in a cavity formation process.
  • the content of ceramic particles such as SiO 2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and accordingly, the interface between the photocurable resin and the thermosetting resin may be distinguishable.
  • XPS X-ray Photoelectron Spectroscopy
  • the insulation layer of the build-up insulation part (120) may include a prepreg, and through this, may have a strength of a certain level or higher that can improve the bending characteristics of the circuit board.
  • the prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.
  • the via electrode (126) may include a plurality of first via electrodes (127), second via electrodes (128), and third via electrodes (129) formed in through holes that penetrate the first to third build-up insulating portions (111, 112, 113), respectively.
  • the via electrode (126) may electrically connect between wiring layers (125) arranged in different layers.
  • a via electrode (126) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material.
  • the inside of the through hole can be filled with a conductive material to form a via electrode (126).
  • the metal material forming the via electrode (126) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd).
  • the conductive material filling can utilize one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.
  • the pad of the wiring layer (125) includes a connection pad or a connecting pad.
  • the connection pad may be a mounting pad on which an electronic component or a semiconductor chip is mounted, or a terminal pad connected to an external substrate.
  • the connecting pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion having a horizontal width larger than that of the trace for alignment margin.
  • the wiring layer (125) may include, but is not limited to, a first wiring layer (121) electrically connected to the upper surface of the first via electrode (127), a second wiring layer (122) disposed on the first build-up insulation portion (111) and electrically connected to the second via electrode (128), a third wiring layer (123) connected to the lower surface of the first via electrode (127), and a fourth wiring layer (124) electrically connected to the lower surface of the third via electrode (129).
  • the wiring layer (125) can be formed by a circuit board manufacturing process such as an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), and an SAP (Semi Additive Process).
  • a circuit board manufacturing process such as an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), and an SAP (Semi Additive Process).
  • any one of the above-described build-up wiring bodies may have an ETS (Embedded Trace Substrate) structure.
  • the ETS structure may also be referred to as a buried structure.
  • the ETS structure may be advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in the semiconductor device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.
  • the build-up wiring body can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn).
  • the build-up wiring body can be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.
  • connection part such as a solder ball
  • the connection part can be in contact not only with the upper and side surfaces of the second pad (150) but also with the lower surface of the second pad (150) exposed by the concave portion (160), thereby improving the electrical contact area, and there is a technical effect in that the edge area of the second pad (150) exposed by the concave portion (160) can act as an anchor to fix the connection part.
  • the circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).
  • CSP Chip Scale Package
  • FC-CSP Flexible Chip-Chip Scale Package
  • FC-BGA Flexible Chip Ball Grid Array
  • POP Package On Package
  • SIP System In Package
  • circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotive, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Une carte de circuit imprimé selon un mode de réalisation comprend : une partie d'isolation à accumulation comprenant une pluralité de couches d'isolation empilées verticalement; une première pastille disposée sur une première région de la partie d'isolation à accumulation; et une seconde pastille disposée sur la surface supérieure de la première pastille, la première pastille comprenant une partie concave qui est concave vers l'intérieur à partir d'une surface latérale de la première pastille, et la partie concave pouvant chevaucher verticalement la seconde pastille.
PCT/KR2025/000158 2024-01-03 2025-01-03 Carte de circuit imprimé et boîtier de semi-conducteur la comprenant Pending WO2025147154A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20240001021 2024-01-03
KR10-2024-0001021 2024-01-03
KR10-2024-0194508 2024-12-23
KR1020240194508A KR20250106696A (ko) 2024-01-03 2024-12-23 회로 기판 및 이를 포함하는 반도체 패키지

Publications (1)

Publication Number Publication Date
WO2025147154A1 true WO2025147154A1 (fr) 2025-07-10

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ID=96300566

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2025/000158 Pending WO2025147154A1 (fr) 2024-01-03 2025-01-03 Carte de circuit imprimé et boîtier de semi-conducteur la comprenant

Country Status (1)

Country Link
WO (1) WO2025147154A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100038148A (ko) * 2008-10-03 2010-04-13 신꼬오덴기 고교 가부시키가이샤 배선 기판 및 그 제조 방법
US20110048782A1 (en) * 2009-08-26 2011-03-03 Jun-Chung Hsu Solder Pad Structure With High Bondability To Solder Ball
JP2012164934A (ja) * 2011-02-09 2012-08-30 Mitsubishi Electric Corp 回路モジュール、電子部品実装基板および回路モジュールの製造方法
KR20220154067A (ko) * 2020-10-30 2022-11-21 엘지이노텍 주식회사 회로기판
JP2023164038A (ja) * 2022-04-28 2023-11-10 Ｔｏｐｐａｎホールディングス株式会社 配線基板、半導体装置及び配線基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100038148A (ko) * 2008-10-03 2010-04-13 신꼬오덴기 고교 가부시키가이샤 배선 기판 및 그 제조 방법
US20110048782A1 (en) * 2009-08-26 2011-03-03 Jun-Chung Hsu Solder Pad Structure With High Bondability To Solder Ball
JP2012164934A (ja) * 2011-02-09 2012-08-30 Mitsubishi Electric Corp 回路モジュール、電子部品実装基板および回路モジュールの製造方法
KR20220154067A (ko) * 2020-10-30 2022-11-21 엘지이노텍 주식회사 회로기판
JP2023164038A (ja) * 2022-04-28 2023-11-10 Ｔｏｐｐａｎホールディングス株式会社 配線基板、半導体装置及び配線基板の製造方法

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