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WO2025005458A1 - Carte de circuit imprimé en céramique, son procédé de fabrication et module d'alimentation de type à refroidissement double face la comprenant - Google Patents

Carte de circuit imprimé en céramique, son procédé de fabrication et module d'alimentation de type à refroidissement double face la comprenant Download PDF

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Publication number
WO2025005458A1
WO2025005458A1 PCT/KR2024/006529 KR2024006529W WO2025005458A1 WO 2025005458 A1 WO2025005458 A1 WO 2025005458A1 KR 2024006529 W KR2024006529 W KR 2024006529W WO 2025005458 A1 WO2025005458 A1 WO 2025005458A1
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WO
WIPO (PCT)
Prior art keywords
copper
layer
ceramic
base
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/KR2024/006529
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English (en)
Korean (ko)
Inventor
김민수
배일석
서진원
이효종
육점국
문상환
김병길
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rn2 Ceramics Co Ltd
Rn2 Technologies Co Ltd
Original Assignee
Rn2 Ceramics Co Ltd
Rn2 Technologies Co Ltd
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Filing date
Publication date
Priority claimed from KR1020240061407A external-priority patent/KR20250001881A/ko
Application filed by Rn2 Ceramics Co Ltd, Rn2 Technologies Co Ltd filed Critical Rn2 Ceramics Co Ltd
Publication of WO2025005458A1 publication Critical patent/WO2025005458A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern

Definitions

  • the technical idea of the present invention relates to a ceramic circuit board, and more specifically, to a ceramic circuit board having a copper structure with a differential porosity, a method for manufacturing the same, and a double-sided cooling type power module having the same.
  • Power semiconductor devices which are widely used in mobile devices, home appliances, and automobiles, play a role in converting, processing, and controlling power. Since power semiconductor devices, to which high current and high voltage are applied for power supply, generate a large amount of heat, ceramic circuit boards made of ceramic materials such as Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), and Si 3 N 4 are used. Ceramics have high insulation, mechanical strength, and relatively high heat dissipation performance, and are therefore suitable as substrates for high-power power semiconductor devices.
  • the ceramic circuit board may include a conductive pattern made of aluminum (Al) or copper (Cu) with high thermal conductivity on the ceramic material.
  • a double-sided cooling type power module in which ceramic circuit boards are arranged on both sides of the power semiconductor device to enable cooling on both sides.
  • cooling fins are arranged on the outside of the ceramic circuit board, and heat can be transferred to a water cooler installed externally through the cooling fins.
  • the conventional technology for manufacturing such ceramic circuit boards forms a pattern of a conductive layer using an etching process, and therefore has limitations in the shape of the pattern.
  • the Mo-Cu alloy conductive spacer has low thermal conductivity, and has a limitation in that it requires an additional process of individually mounting small-sized spacers on the ceramic circuit board.
  • the technical problem to be achieved by the technical idea of the present invention is to provide a ceramic circuit board having excellent heat dissipation performance including a copper structure, a method for manufacturing the same, and a double-sided cooling type power module having the same.
  • a ceramic circuit board having excellent heat dissipation performance including a copper structure, a method for manufacturing the same, and a double-sided cooling type power module having the same are provided.
  • the ceramic circuit board may include a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; and a first copper structure disposed on a portion of the first base copper layer, the first copper structure being formed by printing, pressing, and sintering a copper-containing paste, the first copper structure having a differential porosity, and including a region on an upper side having a lower porosity than a lower side relatively adjacent to the first base copper layer.
  • the porosity of the first copper structure may decrease from the lower side relatively adjacent to the first base copper layer toward the upper side.
  • the first copper structure may include a first base portion; and a first surface portion disposed on the first base portion and having a lower porosity than the first base portion.
  • the first base portion may have a porosity in a range of more than 5 volume% and less than or equal to 20 volume%
  • the first surface portion may have a porosity in a range of more than 0 volume% and less than or equal to 5 volume%.
  • the first base portion can be formed using a paste including copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m
  • the first surface portion can be formed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m.
  • At least one copper-containing paste is formed by printing, pressing and sintering, and is disposed on at least a portion of the first copper structure.
  • a second copper structure may be further included.
  • the second copper structure may include a region on the upper side having a differential porosity and having a lower porosity than the lower side relatively adjacent to the first copper structure.
  • the porosity of the second copper structure may decrease from the lower side relatively adjacent to the first copper structure toward the upper side.
  • the second copper structure may include a second base portion; and a second surface portion disposed on the second base portion and having a lower porosity than the second base portion.
  • the second base portion may have a porosity in a range of more than 5 volume% and less than or equal to 20 volume%, and the second surface portion may have a porosity in a range of more than 0 volume% and less than or equal to 5 volume%.
  • the second base portion can be formed using a paste including copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m, and the second surface portion can be formed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m.
  • the first base copper layer may be formed of a TPC copper layer formed by printing, pressing, and sintering a copper-containing paste on the ceramic layer, a DBC copper layer formed by bonding copper foil on the ceramic layer using a high-temperature oxidation process, a DPC copper layer formed by forming a seed layer on the ceramic layer and then plating the seed layer with copper, or an AMB copper layer formed by bonding copper foil to the ceramic layer using an active metal foil.
  • the first base copper layer may include at least one of a bonded copper layer, a laminated copper layer, and a surface copper layer.
  • the bonding copper layer may be formed using a copper-containing bonding paste including glass frit, inorganic particles, copper oxide particles, copper particles, a solvent and a binder
  • the laminated copper layer may be formed using a copper-containing laminated paste including inorganic particles, copper particles, a solvent and a binder
  • the surface copper layer may be formed using a copper-containing surface paste including copper oxide particles, copper particles, a solvent and a binder.
  • the ceramic substrate may further include a second base copper layer disposed on a second surface of the ceramic layer.
  • the ceramic layer may include at least one of Al 2 O 3 , AlN, ZTA (Zirconia Toughened Alumina), and Si 3 N 4 .
  • the ceramic circuit board may include a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; and a first copper structure disposed on a portion of the first base copper layer, the first copper structure being formed by printing, pressing, and sintering a copper-containing paste, and having a pyramidal shape whose plane area decreases from a lower side relatively adjacent to the first base copper layer to an upper side.
  • the first copper structure may include a region on the upper side having a differential porosity and having a lower porosity than the lower side that is relatively adjacent to the first base copper layer.
  • the porosity of the first copper structure may decrease from the lower side relatively adjacent to the first base copper layer toward the upper side.
  • the first copper structure may include a first base portion; and a first surface portion disposed on the first base portion and having a lower porosity than the first base portion.
  • the first base portion may have a porosity in a range of more than 5 volume% and less than or equal to 20 volume%
  • the first surface portion may have a porosity in a range of more than 0 volume% and less than or equal to 5 volume%.
  • the present invention may further include a second copper structure disposed on a portion of the first copper structure and formed by printing, pressing, and sintering a copper-containing paste.
  • the second copper structure may have a pyramidal shape whose plane area decreases from the lower side relatively adjacent to the first copper structure to the upper side.
  • the second copper structure may include a region on the upper side having a differential porosity and having a lower porosity than the lower side relatively adjacent to the first copper structure.
  • the porosity of the second copper structure may decrease from the lower side relatively adjacent to the first base copper layer toward the upper side.
  • the second copper structure may include a second base portion; and a second surface portion disposed on the second base portion and having a lower porosity than the second base portion.
  • the second base portion may have a porosity in a range of more than 5 volume% and less than or equal to 20 volume%, and the second surface portion may have a porosity in a range of more than 0 volume% and less than or equal to 5 volume%.
  • the double-sided cooling power module comprises: a lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and a lower second copper structure disposed on a portion of the lower first copper structure; an upper ceramic circuit board including an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; and an upper second copper structure disposed on a portion of the upper first copper structure; a first semiconductor element disposed between the lower first copper structure and the upper first copper structure; a second semiconductor element disposed between the lower second copper structure and the upper second copper structure and having a smaller thickness than the first semiconductor element; And a mold layer covering the first semiconductor element and the second semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic substrate; wherein at least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper
  • the lower ceramic substrate may further include a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer
  • the upper ceramic substrate may further include an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer.
  • the double-sided cooling power module comprises: a lower ceramic circuit board comprising: a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and a lower second copper structure disposed on a portion of the lower first copper structure; an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; a first semiconductor element disposed between the lower first copper structure and the upper first base copper layer; a second semiconductor element disposed between the lower second copper structure and the upper first base copper layer and having a smaller thickness than the first semiconductor element; and a mold layer filling a space between the lower ceramic circuit board and the upper ceramic circuit board and covering the first semiconductor element and the second semiconductor element; wherein at least one of the lower first copper structure and the lower second copper structure may have a differential porosity, and may include a region on an upper side having a lower porosity than a lower side that is relatively adjacent to the lower first base copper layer.
  • the lower ceramic substrate may include a lower active metal brazing layer interposed between the lower ceramic layer and the lower first base copper layer
  • the upper ceramic substrate may include an upper active metal brazing layer interposed between the upper ceramic layer and the upper first base copper layer.
  • the double-sided cooling power module comprises: a lower ceramic circuit board comprising a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and a lower second copper structure disposed on a portion of the lower first copper structure; an upper ceramic circuit board including an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; and an upper second copper structure disposed on a portion of the upper first copper structure; a first semiconductor element disposed between the lower first copper structure and the upper first copper structure; a second semiconductor element disposed between the lower second copper structure and the upper second copper structure and having a smaller thickness than the first semiconductor element; And a mold layer covering the first semiconductor element and the second semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic circuit board; wherein the lower first copper structure, the upper first copper structure, the lower second copper structure and the upper second copper structure are formed by
  • the double-sided cooling power module comprises: a lower ceramic circuit board including a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and a lower second copper structure disposed on a portion of the lower first copper structure; an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; a first semiconductor element disposed between the lower first copper structure and the upper ceramic substrate; a second semiconductor element disposed between the lower second copper structure and the upper ceramic substrate and having a smaller thickness than the first semiconductor element; And a mold layer covering the first semiconductor element and the second semiconductor element by filling the space between the lower ceramic circuit board and the upper ceramic substrate; wherein the lower first copper structure and the lower second copper structure are formed by printing, pressing and sintering a copper-containing paste, and at least one of the lower first copper structure and the lower second copper structure may have a frusto-prism shape whose plane area decreases from the lower side relatively adjacent to the lower
  • the ceramic circuit board according to the present invention can form a three-dimensional pattern on a ceramic substrate by using a copper structure formed by printing, pressing, and sintering as a spacer so as to be able to respond to various types of semiconductor elements mounted on the substrate.
  • a copper structure formed by printing, pressing, and sintering as a spacer so as to be able to respond to various types of semiconductor elements mounted on the substrate.
  • electrical conductivity and thermal conductivity are improved, and durability against thermal cycles can be improved.
  • the copper structure is a sintered material rather than a rolled material, there are differences in the microstructure, such as not having the directionality that appears in a rolled material, and there are differences in the degree of inclusion and distribution of pores.
  • the copper structure according to the present invention includes a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue destruction, and furthermore, by including an upper layer having a low porosity, it can prevent bonding defects of power semiconductor devices.
  • the copper structure has a pyramidal shape, a power semiconductor element can be stably mounted.
  • the method for manufacturing a ceramic circuit board according to the present invention can prevent the formation of defects due to heat by performing sintering of a copper structure at a temperature in the range of 500°C to 800°C.
  • surface blasting treatment copper oxide formed on the surface of the copper structure during sintering can be removed to provide a smooth surface, and thus, the bonding of a power semiconductor element mounted on the copper structure can be stably ensured.
  • Figures 1 to 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.
  • FIGS. 5A and 5B are cross-sectional views illustrating a base copper layer and a copper body of a ceramic circuit board according to one embodiment of the present invention.
  • FIG. 6 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.
  • FIGS. 7A and 7B are cross-sectional views and photographs illustrating a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.
  • FIG. 8 is a flow chart illustrating a method for manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • Figure 9 is a result of an ultrasonic inspection showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 10 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to one embodiment of the present invention.
  • FIG. 11 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.
  • FIGS. 12 to 15 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.
  • a layer formed "on" another layer may refer to a layer formed directly on the other layer, or may refer to a layer formed on an intermediate layer or intermediate layers formed on the other layer. It should be noted that the meanings of "upper” and “lower” in this specification are relative, and the direction upward from the ceramic substrate is described as “upper”, and the direction downward is described as “lower.”
  • power semiconductor devices are exemplary, and cases composed of other semiconductor devices are also included in the technical spirit of the present invention.
  • Figures 1 to 4 are cross-sectional views of a ceramic circuit board according to one embodiment of the present invention.
  • the ceramic circuit board (1) may include a ceramic substrate (110) and a first copper structure (150).
  • the ceramic circuit board (1a) may include a ceramic substrate (110a) and a first copper structure (150).
  • the ceramic circuit board (100) may include a ceramic substrate (110), a first copper structure (150), and a second copper structure (160).
  • the ceramic circuit board (100a) may include a ceramic substrate (110a), a first copper structure (150), and a second copper structure (160).
  • the ceramic substrate (110) may include a ceramic layer (120), a first base copper layer (130), and a second base copper layer (140).
  • the ceramic substrate (110a) may include a ceramic layer (120), a first active metal brazing layer (125), a second active metal brazing layer (126), a first base copper layer (130), and a second base copper layer (140). Compared to the ceramic substrate (110), the ceramic substrate (110a) has a difference in that it further includes a first active metal brazing layer (125) and a second active metal brazing layer (126).
  • the ceramic layer (120) may have a first surface (121) and a second surface (122) that face each other. In FIGS. 1 to 4, the first surface (121) is illustrated as an upper surface and the second surface (122) is illustrated as a lower surface with respect to the ceramic layer (120).
  • the ceramic layer (120) may have excellent thermal conductivity and electrical insulation.
  • the ceramic layer (120) may be formed of a ceramic material, and may include, for example, at least one of Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), and Si 3 N 4 .
  • the first base copper layer (130) can be disposed on the first surface (121) of the ceramic layer (120).
  • the first base copper layer (130) can be formed using TPC technology, DBC technology, DPC technology, or AMB technology.
  • the first base copper layer (130) can have a total thickness in a range of, for example, 100 ⁇ m to 1000 ⁇ m, and can have a total thickness of, for example, about 300 ⁇ m.
  • the second base copper layer (140) may be disposed on the second surface (122) opposite to the first surface (121) of the ceramic layer (120).
  • the second base copper layer (140) may function as a warpage prevention layer that prevents the ceramic layer (120) from warping during a sintering process for forming the first base copper layer (130) and a sintering process for forming the first copper structure (150) and the second copper structure (160).
  • the second base copper layer (140) may provide a path for dissipating heat generated from the power semiconductor element to the outside.
  • a heat dissipation structure (not shown) may be attached to the second base copper layer (140).
  • the second base copper layer (140) may be formed as a single layer or as a plurality of layers.
  • the second base copper layer (140) can be formed in the same manner as the first base copper layer (130).
  • the second base copper layer (140) can be formed using the above-described TPC technology, DBC technology, DPC technology, or AMB technology.
  • the second base copper layer (140) can include the same material as the first base copper layer (130), and can be formed at the same time.
  • the first base copper layer (130) and the second base copper layer (140) may be formed as TPC (thick printed copper) copper layers using a TPC (thick printed copper) technology.
  • the TPC technology may refer to a technology of forming a copper layer having a predetermined thickness by printing, pressing, and sintering using a copper-containing paste.
  • the TPC copper layer may be formed by printing a copper-containing paste on one or both sides of a ceramic layer (120) to form a paste layer, and pressing and sintering the paste layer. Since the TPC technology forms the TPC copper layer using a screen printing method, it does not require an additional etching process, and can freely implement various patterning shapes.
  • the TPC technology may allow one layer formed in one process cycle of printing, pressing, and sintering to have a very small thickness, and the one layer may have a thickness in the range of, for example, 10 ⁇ m to 100 ⁇ m.
  • the thickness of the TPC copper layer can be increased by repeatedly performing the above process cycle to form multiple layers, thickness control can be facilitated.
  • the TPC copper layer can secure uniformity in thickness, surface quality, etc. as a whole.
  • nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the TPC copper layer.
  • the first base copper layer (130) and the second base copper layer (140) may be formed as DBC copper layers formed using DBC (direct bonded copper) technology.
  • the DBC technology may refer to a technology of forming a copper layer by directly attaching a copper foil to a ceramic layer.
  • the DBC copper layer may be formed by placing a copper foil on one or both sides of a ceramic layer (120), performing a high-temperature oxidation process at a temperature in the range of 1000° C. to 1080° C., and bonding the copper foil to the ceramic layer using a copper-oxygen eutectic liquid. The bonding may be performed in a nitrogen atmosphere containing about 30 ppm of oxygen at a temperature of 1083° C.
  • the DBC copper layer may be patterned using an etching process. Additionally, nickel (Ni), silver (Ag), gold (Au), etc. can be plated on the DBC copper layer.
  • the first base copper layer (130) and the second base copper layer (140) may be formed as DPC copper layers formed using a DPC (direct plating copper) technology.
  • the DPC technology may refer to a technology of forming a copper layer by using a thin film process, an etching process, and a plating process.
  • the DPC copper layer may be formed by forming a seed layer of titanium (Ti), titanium-tungsten (TiW), or the like on one or both sides of a ceramic layer (120), and then plating copper (Cu) on the seed layer.
  • a photoresist pattern may be formed on the seed layer, and then copper (Cu) may be plated on the photoresist pattern, and the photoresist pattern may be removed to form the DPC copper layer having a desired pattern. Subsequently, if necessary, the DPC copper layer may be patterned using an etching process.
  • Cu copper
  • the first base copper layer (130) and the second base copper layer (140) may be formed of an AMB (active metal brazing) copper layer formed using an AMB technology.
  • the AMB technology may refer to a technology of bonding a ceramic layer and a copper layer using an active metal foil. An active metal foil and a copper foil are sequentially placed on one or both sides of a ceramic layer (120), and the active metal foil is melted by heating. As shown in FIG. 2, a first active metal brazing layer (125) and a second active metal brazing layer (126) are formed, thereby bonding the ceramic layer (120) and the copper foil to each other. Therefore, the first active metal brazing layer (125) may perform a function of bonding the ceramic layer (120) and the first base copper layer (130). The second active metal brazing layer (126) may perform a function of bonding the ceramic layer (120) and the second base copper layer (140). Next, if necessary, the AMB copper layer can be patterned using an etching process.
  • the first active metal brazing layer (125) and the second active metal brazing layer (126) may include a metal or metal alloy having a lower melting point than copper constituting the copper foil, and may include, for example, an active metal alloy in which copper, aluminum, nickel, or silver is added to titanium, hafnium, nickel, molybdenum, or zirconium, which are active for oxygen, to reduce the melting point.
  • the first active metal brazing layer (125) and the second active metal brazing layer (126) may include, for example, an alloy including at least one of silver (Ag), copper (Cu), and titanium (Ti).
  • first active metal brazing layer (125) and the second active metal brazing layer (126) may include at least one of aluminum (Al), titanium (Ti), nickel (Ni), niobium (Nb), and molybdenum (Mo).
  • the first active metal brazing layer (125) may be disposed on the first surface (121) of the ceramic layer (120).
  • the first base copper layer (130) may be disposed on the first active metal brazing layer (125). That is, the first active metal brazing layer (125) is interposed between the ceramic layer (120) and the first base copper layer (130), so that the ceramic layer (120) and the first base copper layer (130) may be bonded to each other.
  • the second active metal brazing layer (126) may be disposed on the second surface (122) of the ceramic layer (120).
  • the second base copper layer (140) may be disposed on the second active metal brazing layer (126). That is, the second active metal brazing layer (126) is interposed between the ceramic layer (120) and the second base copper layer (140), thereby bonding the ceramic layer (120) and the second base copper layer (140) to each other.
  • an additional etching process may be required when applying the DBC technology, the DPC technology, or the AMB technology. Therefore, when using this etching process, there is a limitation in that there is a limitation on the pattern shape, and in order to respond to various types of semiconductor devices, it may be difficult to have a difference in thickness between patterns or to form secondary and tertiary patterns on the pattern. On the other hand, when applying the TPC technology to form the first base copper layer (130), the pattern can be easily formed during printing, and an additional etching process may not be required.
  • the first copper structure (150) may be disposed on a portion of the ceramic substrate (110), for example, on a portion of the first base copper layer (130).
  • the first copper structures (150) may have substantially all the same height.
  • the height may refer to the height from the ceramic substrate (110).
  • the second copper structure (160) may be positioned on at least a portion of the first copper structure (150). As the second copper structure (160) is formed on at least a portion of the first copper structure (150), the portion where the second copper structure (160) is additionally formed may have a higher height than the portion where only the first copper structure (150) is formed.
  • the first copper structure (150) and the second copper structure (160) can be formed using the above-described TPC technology that forms a copper layer by printing, pressing, and sintering. Therefore, the first structure (150) and the second copper structure (160) can be a sintered body made of substantially the same material.
  • the second copper structure (160) can be laminated one or more times on the first copper structure (150). In FIGS. 3 and 4, as an example, one layer of the second copper structure (160) is laminated on a portion of the first copper structure (150).
  • the present invention is not limited thereto, and the second copper structure (160) can be formed in two or more layers in order to adjust the height of the copper structure as needed.
  • the first copper structure (150) and the second copper structure (160) can provide a space in which the power semiconductor element is mounted, and can perform the function of a spacer that corrects a thickness deviation of the power semiconductor element.
  • the height at which the power semiconductor element is placed can be changed by the arrangement of the first copper structure (150) and the second copper structure (160). That is, as the second copper structure (160) is selectively formed on a portion of the first copper structure (150), the height provided when the first copper structure (150) and the second copper structure (160) are included can be greater than the height provided when only the first copper structure (150) is included.
  • the height can refer to the height from the ceramic substrate (110). Copper structures having different heights are formed, and thus, the thickness deviation of power semiconductor elements having different thicknesses can be corrected.
  • the first copper structure (150) and the second copper structure (160) may have the same planar area, or the second copper structure (160) may have a smaller planar area than the first copper structure (150).
  • first copper structure (150) and the second copper structure (160) can additionally perform the function of wiring that provides an electrical passage.
  • the first copper structure (150) and the second copper structure (160) can be applied with a high current or high voltage from the power semiconductor element.
  • the first copper structure (150) and the second copper structure (160) can be integrated by sintering.
  • At least one of the first copper structure (150) and the second copper structure (160) may have a surface from which oxide has been removed by blasting treatment.
  • FIGS. 5A and 5B are cross-sectional views illustrating a base copper layer and a copper structure of a ceramic circuit board according to one embodiment of the present invention.
  • the first base copper layer (130) may be a copper foil formed by DBC technology or AMB technology, or a copper plating layer formed by DPC technology.
  • the first copper structure (150) and the second copper structure (160) may be a sintered body of a copper-containing paste formed by TPC technology.
  • first base copper layer (130), the first copper structure (150), and the second copper structure (160) formed using TPC (thick printed copper) technology will be described in detail.
  • the first base copper layer (130) may be a sintered body of a copper-containing paste formed by TPC technology.
  • the first copper structure (150) and the second copper structure (160) may be sintered bodies of a copper-containing paste formed by TPC technology.
  • the first base copper layer (130), the first copper structure (150), and the second copper structure (160) can be formed by commonly printing a copper-containing paste to form a paste layer and pressing and sintering the paste layer.
  • the first base copper layer (130) may be disposed on a portion of the ceramic layer (120).
  • the first base copper layer (130) may be formed using the TPC technology described above.
  • the first base copper layer (130) may be composed of a plurality of layers.
  • the first base copper layer (130) may include, for example, at least one of a bonding copper layer (131), a laminated copper layer (132), and a surface copper layer (133).
  • the thickness of the first base copper layer (130) can be varied by controlling the thickness of the relatively thick laminated copper layer (132).
  • the laminated copper layer (132) can have a greater thickness than the bonded copper layer (131) and the surface copper layer (133).
  • the bonded copper layer (131) and the surface copper layer (133) can have the same thickness or different thicknesses.
  • the bonded copper layer (131) can have a thickness of, for example, 1 ⁇ m to 100 ⁇ m, for example, about 20 ⁇ m.
  • the laminated copper layer (132) can have a thickness of, for example, 100 ⁇ m to 1000 ⁇ m.
  • the surface copper layer (133) can have a thickness of, for example, 1 ⁇ m to 100 ⁇ m, for example, about 30 ⁇ m.
  • the bonding copper layer (131) may be disposed on at least a portion of the ceramic layer (120).
  • the laminated copper layer (132) may be disposed on the bonding copper layer (131).
  • the surface copper layer (133) may be disposed on the laminated copper layer (132).
  • this is exemplary and the technical idea of the present invention is not limited thereto.
  • the first base copper layer (130) may be configured to include the bonding copper layer (131) and the surface copper layer (133), excluding the laminated copper layer (132).
  • the first base copper layer (130) may be configured to include the bonding copper layer (131) and the laminated copper layer (132), excluding the surface copper layer (133).
  • the bonding copper layer (131) can be formed by forming a bonding paste layer by printing a copper-containing bonding paste on the ceramic layer (120) using a screen printing method or the like, drying to remove the solvent, pressing the dried bonding paste layer, and then heating to sinter it.
  • the laminated copper layer (132) can be formed by printing a copper-containing laminated paste on the bonded copper layer (131) using a screen printing method or the like to form a laminated paste layer, then drying to remove the solvent, pressing the dried laminated paste layer, and then heating to sinter it.
  • the surface copper layer (133) can be formed by printing a copper-containing surface paste on the laminated copper layer (132) using a screen printing method or the like to form a surface paste layer, then drying to remove the solvent, pressing the dried surface paste layer, and then heating to sinter it.
  • the internal pores of the bonding paste layer, the laminated paste layer, and the surface paste layer can be reduced and the uniformity of height can be secured.
  • the above-described printing, pressing, and sintering steps can be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing can be performed again to further form one subsequent paste layer on the previously formed paste layer, and this can be repeated to form a plurality of paste layers.
  • the plurality of paste layers can be sintered together.
  • the copper layer can be formed. That is, sintering can be performed once or more for one copper layer constituting the first base copper layer (130). The number of times of the printing, pressing, and sintering can be varied.
  • the above copper-containing bonding paste may include, for example, copper particles, glass frit, inorganic particles, copper oxide particles, a solvent and a binder.
  • the copper-containing laminate paste may include, for example, copper particles, inorganic particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing laminate paste may not include glass frit and copper oxide particles.
  • the copper-containing surface paste may include copper particles, copper oxide particles, a solvent, and a binder. Compared to the copper-containing bonding paste, the copper-containing surface paste may not include glass frit and inorganic particles.
  • the above glass frit is a sintering aid that helps sintering of copper (Cu) particles and can provide better bonding between the ceramic layer (120) and the bonding copper layer (131).
  • the above inorganic particles may include at least one powder of Al 2 O 3 , CaO, and ZrO 2 .
  • the above inorganic particles may perform a function of reducing the shrinkage rate of the paste.
  • the shrinkage rate may be measured by printing the paste in a disk shape, drying and sintering it, and comparing the diameter of the disk after drying and after sintering.
  • the above copper oxide particles may include at least one of CuO and Cu 2 O, and may perform a function of improving bonding properties with a component to be bonded.
  • the above copper oxide particles may form a process liquid phase during a sintering process.
  • the ceramic layer (120) includes alumina (Al 2 O 3 )
  • the copper oxide may react with alumina to form CuAlO 2 , CuAl 2 O 4 , etc., thereby improving bonding properties.
  • the above copper particles may be composed of copper and may be a main component constituting the first base copper layer (130).
  • the above copper particles may include fine copper particles having an average particle diameter ranging from 1 ⁇ m to 10 ⁇ m and may be included in 60 wt% to 95 wt% of the paste.
  • the shrinkage ratio of the copper-containing laminate paste may be higher than the shrinkage ratio of the copper-containing bonding paste.
  • the shrinkage ratio of the copper-containing surface paste may be higher than the shrinkage ratio of the copper-containing bonding paste and the shrinkage ratio of the copper-containing bonding paste.
  • the shrinkage ratio of the copper-containing bonding paste may be, for example, 0% to 3%.
  • the shrinkage ratio of the copper-containing laminate paste may be, for example, 3% to 9%.
  • the shrinkage ratio of the copper-containing surface paste may be, for example, 10% to 15%.
  • the copper-containing bonding paste, the copper-containing laminate paste, and the copper-containing surface paste can change the types and contents of glass frit, inorganic particles, copper oxide particles, copper particles, solvent, and binder in order to implement a desired thermal expansion coefficient and shrinkage ratio.
  • composition and paste for the first base copper layer (130) described above can be equally applied to the second base copper layer (140).
  • the first copper structure (150) may be placed on a portion of the first base copper layer (130).
  • the first copper structure (150) may have a thermal expansion coefficient in the range of, for example, 5 x 10 -6 /°C to 20 x 10 -6 /°C in order to reduce a difference in thermal expansion coefficient with respect to a power semiconductor device mounted thereon.
  • the first copper structure (150) may be a porous structure having pores therein.
  • the first copper structure (150) may have a differential porosity. This means that the first copper structure (150) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first base copper layer (130).
  • the porosity of the first copper structure (150) may decrease from the lower side relatively adjacent to the first base copper layer (130) toward the upper side.
  • the first copper structure (150) may be composed of a plurality of layers and may include a first base portion (151) and a first surface portion (152) that is disposed on the first base portion (151) and has a lower porosity than the first base portion (151).
  • the first base portion (151) may have a porosity in a range of, for example, more than 5 vol% and less than or equal to 20 vol%.
  • the first surface portion (152) may have a porosity in a range of, for example, more than 0 vol% and less than or equal to 5 vol%.
  • the pores perform a buffer function against thermal shock, thereby reducing thermal stress and increasing resistance to thermal fatigue destruction due to thermal stress under repeated thermal history.
  • the first surface portion (152) since the first surface portion (152) has a relatively low porosity, it can have a smooth surface, and thus the bonding of the power semiconductor element mounted thereon can be improved. If the first surface portion (152) has a high porosity, void defects may remain on the bonding surface due to the pores, and the bonding of the power semiconductor element may become poor. Therefore, it is desirable to control the first surface portion (152) so that there are no pores or the porosity is low.
  • the particle size and fraction of the copper particles included in the paste can be controlled. If the particle size of the copper particles is large or the fraction is low, the porosity can increase, and if the particle size of the copper particles is small or the fraction is large, the porosity can decrease.
  • the first paste forming the first base portion (151) may include copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m.
  • the second paste forming the first surface portion (152) may include copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m. That is, the average particle diameter of the copper particles included in the second paste may be smaller than the average particle diameter of the copper particles included in the first paste. Due to this difference in the average particle diameters of the copper particles, the first surface portion (152) may have a denser microstructure and a lower porosity than the first base portion (151).
  • the first copper structure (150) can have an overall thickness in the range of, for example, 100 ⁇ m to 2000 ⁇ m.
  • the first base portion (151) can have a greater thickness than the first surface portion (152).
  • the first base portion (151) can have a thickness in the range of, for example, 100 ⁇ m to 1900 ⁇ m.
  • the first surface portion (152) can have a thickness in the range of, for example, 1 ⁇ m to 100 ⁇ m, for example, about 20 ⁇ m.
  • the first copper structure (150) can be formed using the TPC technology described above.
  • the first copper structure (150) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder.
  • the copper-containing paste can further include copper oxide particles.
  • the first copper structure (150) can be formed by printing the copper-containing paste using a screen printing method or the like to form a paste layer, drying to remove the solvent, pressing the dried paste layer, and then heating to sinter it.
  • the above-described printing, pressing, and sintering steps can be performed repeatedly. For example, after forming one paste layer in one cycle of the printing and pressing, the printing and pressing can be performed again to further form one subsequent paste layer on the previously formed paste layer, and this can be repeated a plurality of times to form a plurality of paste layers.
  • the plurality of paste layers can be sintered together.
  • the copper layer can be formed. That is, sintering can be performed one or more times for one copper layer constituting the first copper structure (150). The number of times of the printing, pressing, and sintering can be varied.
  • the second copper structure (160) may be arranged on at least a portion of the first copper structure (150).
  • the second copper structure (160) may be formed using the TPC technique described above.
  • the second copper structure (160) may have a thermal expansion coefficient in the range of, for example, 5 x 10 -6 /° C. to 20 x 10 -6 /° C. in order to reduce a difference in thermal expansion coefficient with respect to a power semiconductor device mounted thereon.
  • the second copper structure (160) may be a porous structure having pores inside.
  • the second copper structure (160) may have a differential porosity. This means that the second copper structure (160) includes a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first copper structure (150).
  • the porosity of the second copper structure (160) may decrease from the lower side toward the upper side relative to the first copper structure (150).
  • the second copper structure (160) may be composed of a plurality of layers and may include a second base portion (161) and a second surface portion (162) that is disposed on the second base portion (161) and has a lower porosity than the second base portion (161).
  • the second base portion (161) may have a porosity in a range of, for example, more than 5 vol% and less than or equal to 20 vol%.
  • the second surface portion (162) may have a porosity in a range of, for example, more than 0 vol% and less than or equal to 5 vol%.
  • the first paste forming the second base portion (161) may include copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m.
  • the second paste forming the second surface portion (162) may include copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m.
  • the second copper structure (160) can have an overall thickness in the range of, for example, 100 ⁇ m to 2000 ⁇ m.
  • the second base portion (161) can have a greater thickness than the second surface portion (162).
  • the second base portion (161) can have a thickness in the range of, for example, 100 ⁇ m to 1900 ⁇ m.
  • the second surface portion (162) can have a thickness in the range of, for example, 1 ⁇ m to 100 ⁇ m, for example, about 20 ⁇ m.
  • the second copper structure (160) can be formed using the TPC technology described above.
  • the second copper structure (160) can be formed using a copper-containing paste including copper particles, inorganic particles, a solvent, and a binder.
  • the second base portion (161) may be identical or similar to the first base portion (151), and the second surface portion (162) may be identical or similar to the first surface portion (152).
  • the second copper structure (160) has a different structure than the first copper structure (150), has a different composition material, or is formed by a different manufacturing method.
  • FIG. 6 is a photograph showing the microstructure of a copper structure of a ceramic circuit board according to one embodiment of the present invention.
  • the internal pores of the first base portion (151) and the first surface portion (152) of the first copper structure (150) are shown.
  • the first surface portion (152) has a low porosity, and the size of each pore is also small. That is, the first surface portion (152) has a dense microstructure.
  • the Mo-Cu spacer according to the prior art is a metalworking material that substantially does not include pores inside and has a porosity of about 0%, so it has high thermal stress and low thermal fatigue fracture characteristics.
  • the copper structure according to the present invention includes a lower layer having a high porosity, thereby providing low thermal stress and improved resistance to thermal fatigue fracture, and further includes an upper layer having a low porosity, thereby preventing bonding defects of power semiconductor devices.
  • FIGS. 7A and 7B are cross-sectional views and photographs illustrating a pyramid-shaped copper structure of a ceramic circuit board according to one embodiment of the present invention.
  • the first copper structure (150) may have a truncated pyramid shape in which the planar area of the upper side is smaller than that of the lower side as the planar area decreases from the lower side relatively adjacent to the first base copper layer (130) to the upper side. That is, the first copper structure (150) may have a trapezoidal vertical cross-sectional shape.
  • the first copper structure (150) may have a horizontal cross-sectional shape of a polygon such as a triangle, a square, a pentagon, or a hexagon, or a circle such as a square, an ellipse, or a semicircle.
  • the first copper structure (150) has a pyramidal shape, a power semiconductor element can be stably mounted. In addition, an undercut phenomenon formed by etching can be prevented.
  • pyramidal shapes can be formed as follows.
  • the first layer (151_1) of the first base portion (151) and then sintering After printing and pressing the first layer (151_1) of the first base portion (151) and then sintering, it can naturally shrink due to volume reduction caused by evaporation of the solvent and sintering of the copper particles. At this time, the lower side of the first layer (151_1) is attached to the first base copper layer (130), so that shrinkage occurs little, while the upper side shrinks greatly. Then, when the second layer (151_2) is printed, the area of the upper side that has shrunk corresponds to the area, so that the lower area of the second layer (150_2) is reduced. When the second layer (151_2) is sintered, the upper side shrinks more than the lower side, similar to the first layer (150_1).
  • a plurality of layers having an upper side having a smaller area than the lower side are formed.
  • a first surface portion (152) having an upper side having a smaller area than a lower side is formed on the nth layer (150_n). Accordingly, a first copper structure (150) having a pyramidal shape can be formed.
  • the application area of the paste applied during printing can be reduced from the bottom to the top using TPC technology to implement the pyramidal shape.
  • the application area can be reduced to 1 area% to 10 area%, for example, 3 area% to 5 area%.
  • the second copper structure (160) may have a pyramidal shape whose planar area decreases from the lower side to the upper side relatively adjacent to the first copper structure (150).
  • FIG. 7b photographs of an actual implementation of such a pyramid-shaped copper structure are shown.
  • FIG. 8 is a flow chart illustrating a method for manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • a method for manufacturing a ceramic circuit board may include a step (S110) of providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer; a step (S120) of forming a first copper structure on a portion of the ceramic substrate; and a step (S130) of forming one or more second copper structures on at least a portion of the first copper structure.
  • the method for manufacturing a ceramic circuit board (S100) may further include a step (S140) of blasting the surface of at least one of the first copper structure and the second copper structure.
  • the step of providing the ceramic substrate (S110) may be performed by providing a ceramic substrate including a ceramic layer and a first base copper layer disposed on a first surface of the ceramic layer.
  • the ceramic substrate may further include a second base copper layer disposed on a second surface of the ceramic layer opposite to the first surface.
  • the base copper layer should be understood to mean the first base copper layer and the second base copper layer.
  • the first base copper layer may be a TPC copper layer, a DBC copper layer, a DPC copper layer, or an AMB copper layer.
  • the step (S120) of forming the first copper structure may include a printing step of printing a copper-containing paste on a portion of the first base copper layer to form a paste layer; a pressing step of pressing the paste layer; and a sintering step of sintering the paste layer to form the first copper structure.
  • a copper-containing paste may be formed on the ceramic layer by screen printing.
  • the printing step may include a drying step that is intentionally performed to remove all or part of the solvent contained in the paste layer by maintaining the temperature in the range of 10° C. to 100° C. in the air. Alternatively, the drying may be performed unintentionally by natural drying.
  • the paste layer can be pressed to form a uniform thickness.
  • the boundary of the paste layer can have a higher viscosity than the center because the flow speed of the copper-containing paste is reduced, and can be formed to a thick thickness. By pressing the paste layer, such thickness deviation can be reduced. In addition, the internal pores of the paste layer can be removed or reduced.
  • the copper particles contained in the paste layer can be sintered.
  • the sintering step can be performed in an inert atmosphere, such as a nitrogen atmosphere, an argon atmosphere, or the like, or can be performed in an air atmosphere.
  • the sintering step can be performed in a continuous heat treatment furnace, such as a muffle type heat treatment furnace, or in a batch type heat treatment furnace, such as a box oven.
  • the step (S130) of forming the second copper structure may include a printing step of printing a copper-containing paste on a portion of the first copper structure to form a paste layer; a pressing step of pressing the paste layer; and a sintering step of sintering the paste layer to form the second copper structure.
  • At least one of the sintering step for forming the first copper structure and the sintering step for forming the second copper structure may be performed at a temperature of, for example, less than 900°C, and may be performed at a temperature of, for example, 500°C to 800°C for 10 minutes to 120 minutes.
  • the ceramic substrate includes an active metal brazing layer
  • the sintering temperature is preferably lower than the melting temperature of the active metal brazing layer, and is preferably lower, for example, in the range of 50°C to 100°C.
  • the sintering may be performed by including a bake out step at a temperature ranging from 300° C. to 500° C. by supplying a small amount of water vapor or oxygen to a nitrogen atmosphere to remove the binder contained in the paste layer, and a liquid-phase sintering step of the copper particles contained in the paste layer.
  • a bake out step at a temperature ranging from 300° C. to 500° C. by supplying a small amount of water vapor or oxygen to a nitrogen atmosphere to remove the binder contained in the paste layer, and a liquid-phase sintering step of the copper particles contained in the paste layer.
  • this is exemplary and the technical idea of the present invention is not limited thereto, and the bake out step may be omitted.
  • the step (S120) of forming the first copper structure may be performed so that the first copper structure has a differential porosity.
  • the first copper structure may include a region on the upper side having a lower porosity than a region on the lower side that is relatively adjacent to the first base copper layer.
  • the step (S120) of forming the first copper structure may include: a step of forming a first base portion; and a step of forming a first surface portion having a lower porosity than the first base portion on the first base portion.
  • the step of forming the first base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m.
  • the step of forming the first surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m on the first base portion.
  • the first base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%.
  • the first surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.
  • the step (S130) of forming the second copper structure may be performed so that the second copper structure has a differential porosity.
  • the second copper structure may include a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the first copper structure.
  • the step of forming the second copper structure may include: a step of forming a second base portion; and a step of forming a second surface portion having a lower porosity than the second base portion on the second base portion.
  • the step of forming the second base portion may be performed using a paste including copper particles having an average particle diameter in a range of more than 3 ⁇ m and less than or equal to 10 ⁇ m.
  • the step of forming the second surface portion may be performed using a paste including copper particles having an average particle diameter in a range of 100 nm to 3 ⁇ m on the second base portion.
  • the second base portion may have a porosity in a range of more than 5 vol% and less than or equal to 20 vol%.
  • the second surface portion may have a porosity in a range of more than 0 vol% and less than or equal to 5 vol%.
  • the printing step, the pressing step, and the sintering step for forming the first copper structure and the second copper structure can be performed repeatedly. For example, after the printing step and the pressing step are performed in one cycle to form one paste layer, the printing step and the pressing step are performed again to further form one subsequent paste layer on the previously formed paste layer, thereby forming a plurality of paste layers.
  • the plurality of paste layers can be sintered together.
  • the copper layers can be formed. That is, the sintering step can be performed once or more for one copper layer constituting the first copper structure and the second copper structure.
  • the number of times of the printing step, the pressing step, and the sintering step can be variously changed.
  • the ceramic layer may warp during sintering.
  • paste layers may be formed on both sides of the ceramic layer and sintered together to form the first base copper layer and the second base copper layer at the same time.
  • the second base copper layer may be additionally formed at the same time as the first copper structure and the second copper structure. It is preferable that the paste layers formed on both sides and sintered simultaneously based on the ceramic layer have the same volume, or the volume ratio may be, for example, 90% to 100%.
  • the volume ratio may be a percentage obtained by dividing the volume of the paste layer having a small volume by the volume of the paste layer having a large volume. In addition, the volume can be calculated from the weight of the paste layer.
  • the step (S120) of forming the first copper structure can cause the first copper structure to have a pyramidal shape by reducing the application area of the copper-containing paste from the lower side relatively adjacent to the first base copper layer toward the upper side when performing the printing step.
  • the application area of the copper-containing paste is reduced from the lower side relatively adjacent to the first copper structure toward the upper side, thereby allowing the second copper structure to have a pyramidal shape.
  • the above blasting treatment step (S140) can treat the surface of at least one of the base copper layer, the first copper structure, and the second copper structure by blasting it with ceramic particles such as sand.
  • Solder is applied on the first copper structure and the second copper structure, and a power semiconductor element is mounted.
  • the process of sintering the first copper structure and the second copper structure is heat-treated at a high temperature in the air, so that a copper oxide layer may be formed on the surface.
  • oxidation by oxygen may occur.
  • the copper oxide layer may reduce the adhesion of the power semiconductor element to the first copper structure and the second copper structure. Therefore, after forming the first copper structure and the second copper structure, the copper oxide layer may be removed by blasting fine-diameter ceramic particles on the surfaces of the first copper structure and the second copper structure.
  • the blasting may be referred to as sand blasting.
  • a case in which a base copper layer is blasted is also included in the technical idea of the present invention.
  • Figure 9 is a result of an ultrasonic inspection showing whether a defect occurs depending on the sintering temperature of a ceramic circuit board according to an embodiment of the present invention.
  • the sintering temperature of the base copper layer, the first copper structure, and the second copper structure is preferably lower than 900°C, and for example, a temperature in the range of 500°C to 800°C is preferable.
  • FIG. 10 is a photograph showing the surface state of a copper structure of a ceramic circuit board before and after blasting treatment according to one embodiment of the present invention.
  • FIG. 10 the surface state of the copper structure before and after blasting treatment is shown.
  • blasting treatment is not performed, it can be seen that copper oxide exists on the surface of the copper structure and that the copper structure has a rough surface.
  • the copper oxide is removed by blasting treatment, and a smooth surface is obtained, and the surface becomes smoother as the number of blasting cycles increases. Therefore, after blasting treatment, the power semiconductor element mounted on the copper structure can be more stably joined.
  • FIG. 11 is a perspective view illustrating a pair of ceramic circuit boards for forming a double-sided cooling power module according to one embodiment of the present invention.
  • a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U) forming a double-sided cooling power module are illustrated.
  • the lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D).
  • the lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).
  • the upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), and an upper second copper structure (160_U).
  • the upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).
  • FIGS. 12 to 15 are cross-sectional views illustrating a double-sided cooling power module according to one embodiment of the present invention.
  • a double-sided cooling power module (10) may include a lower ceramic circuit board (100_D), an upper ceramic circuit board (100_U), a first power semiconductor element (20), a second power semiconductor element (30), an element attachment layer (40), and a mold layer (50).
  • the lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D).
  • the lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).
  • the upper ceramic circuit board (100_U) may include an upper ceramic substrate (110_U), an upper first copper structure (150_U), and an upper second copper structure (160_U).
  • the upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).
  • the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) can be placed facing each other.
  • a first power semiconductor element (20) and a second power semiconductor element (30) may be arranged between a lower ceramic circuit board (100_D) and an upper ceramic circuit board (100_U).
  • the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U) may perform a function of dissipating heat generated from the first power semiconductor element (20) and the second power semiconductor element (30) to the outside.
  • a heat dissipation structure (not shown) may be arranged on an outer surface of at least one of the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U).
  • the first power semiconductor element (20) and the second power semiconductor element (30) may be, for example, a GTO (gate turn-off thyristor) semiconductor element or an IGBT (insulated gate bipolar mode transistor) semiconductor element, and may perform an operation of converting power supplied from a power supply unit such as a battery into power for driving a motor through a switching operation and supplying the converted power.
  • the first power semiconductor element (20) and the second power semiconductor element (30) may include electrode members formed on the upper or lower portions.
  • the first power semiconductor element (20) may be placed between the lower first copper structure (150_D) and the upper first copper structure (150_U). One side of the first power semiconductor element (20) may be attached to the lower first copper structure (150_D) by the element attachment layer (40), and the other side may be attached to the upper first copper structure (150_U) by the element attachment layer (40).
  • the second power semiconductor element (30) may be placed between the lower second copper structure (160_D) and the upper second copper structure (160_U).
  • One side of the second power semiconductor element (30) may be attached to the lower second copper structure (160_D) by the element attachment layer (40), and the other side may be attached to the upper second copper structure (160_U) by the element attachment layer (40).
  • the second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20). Therefore, a second copper structure (160) may be further arranged on the upper and lower sides of the second power semiconductor element (30) to correct the thickness difference between the second power semiconductor element (30) and the first power semiconductor element (20).
  • the component attachment layer (40) may be a solder layer or an adhesive layer, which is exemplary and the technical idea of the present invention is not limited thereto.
  • the mold layer (50) can fill the space between the lower ceramic circuit board (100_D) and the upper ceramic circuit board (100_U). Accordingly, the first power semiconductor element (20) and the second power semiconductor element (30) can be covered by the mold layer (50).
  • the mold layer (50) can insulate the first power semiconductor element (20) and the second power semiconductor element (30).
  • the mold layer (50) can be composed of, for example, EMC (epoxy molding compound).
  • At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D), and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than a lower side that is relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).
  • the double-sided cooling power module (10) may have a symmetrical structure based on the first power semiconductor element (20) and the second power semiconductor element (30). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be symmetrically arranged.
  • this is exemplary and the technical idea of the present invention is not limited thereto.
  • the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights.
  • the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.
  • a double-sided cooling power module (10a) may include a lower ceramic circuit board (100a_D), an upper ceramic circuit board (100a_U), a first power semiconductor element (20), a second power semiconductor element (30), an element attachment layer (40), and a mold layer (50).
  • the lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), and a lower second copper structure (160_D).
  • the lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).
  • the upper ceramic circuit board (100a_U) may include an upper ceramic substrate (110a_U), an upper first copper structure (150_U), and an upper second copper structure (160_U).
  • the upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).
  • the lower ceramic circuit board (100a_D) and the upper ceramic circuit board (100a_U) may be arranged to face each other.
  • the first power semiconductor element (20) may be arranged between the lower first copper structure (150_D) and the upper first copper structure (150_U).
  • the second power semiconductor element (30) may be arranged between the lower second copper structure (160_D) and the upper second copper structure (160_U).
  • the second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).
  • At least one of the lower first copper structure (150_D), the upper first copper structure (150_U), the lower second copper structure (160_D), and the upper second copper structure (160_U) may have a differential porosity and include a region on the upper side having a lower porosity than a lower side that is relatively adjacent to the lower first base copper layer (130_D) or the upper first base copper layer (130_U).
  • the double-sided cooling power module (10a) may have a symmetrical structure based on the first power semiconductor element (20) and the second power semiconductor element (30). That is, the lower first copper structure (150_D), the lower second copper structure (160_D), the upper first copper structure (150_U), and the upper second copper structure (160_U) may be symmetrically arranged.
  • this is exemplary and the technical idea of the present invention is not limited thereto.
  • the lower first copper structure (150_D) and the upper first copper structure (150_U) may have different heights.
  • the lower second copper structure (160_D) and the upper second copper structure (160_U) may have different heights.
  • the double-sided cooling power module (10a) of FIG. 13 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).
  • a double-sided cooling power module (10b) may include a lower ceramic circuit board (100_D), an upper ceramic board (110_U), a first power semiconductor element (20), a second power semiconductor element (30), an element attachment layer (40), and a mold layer (50).
  • the lower ceramic circuit board (100_D) may include a lower ceramic substrate (110_D), a lower first copper structure (150_D), and a lower second copper structure (160_D).
  • the lower ceramic substrate (110_D) may include a lower ceramic layer (120_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).
  • the upper ceramic substrate (110_U) may include an upper ceramic layer (120_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).
  • the lower ceramic circuit board (100_D) and the upper ceramic board (110_U) can be placed facing each other.
  • the first power semiconductor element (20) may be placed between the lower first copper structure (150_D) and the upper first base copper layer (130_U).
  • the second power semiconductor element (30) may be placed between the lower second copper structure (160_D) and the upper first base copper layer (130_U).
  • the second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).
  • At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the lower first base copper layer (130_D).
  • the double-sided cooling type power module (10b) of Fig. 14 has a difference in that it includes an upper ceramic substrate (110_U) instead of an upper ceramic circuit substrate (100_U). That is, the double-sided cooling type power module (10b) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). Therefore, the double-sided cooling type power module (10b) may have an asymmetrical structure with respect to the first power semiconductor element (20) and the second power semiconductor element (30).
  • a double-sided cooling power module (10c) may include a lower ceramic circuit board (100a_D), an upper ceramic board (110a_U), a first power semiconductor element (20), a second power semiconductor element (30), an element attachment layer (40), and a mold layer (50).
  • the lower ceramic circuit board (100a_D) may include a lower ceramic substrate (110a_D), a lower first copper structure (150_D), and a lower second copper structure (160_D).
  • the lower ceramic substrate (110a_D) may include a lower ceramic layer (120_D), a lower first active metal brazing layer (125_D), a lower second active metal brazing layer (126_D), a lower first base copper layer (130_D), and a lower second base copper layer (140_D).
  • the upper ceramic substrate (110a_U) may include an upper ceramic layer (120_U), an upper first active metal brazing layer (125_U), an upper second active metal brazing layer (126_U), an upper first base copper layer (130_U), and an upper second base copper layer (140_U).
  • the lower ceramic circuit board (100a_D) and the upper ceramic board (110a_U) can be placed facing each other.
  • the first power semiconductor element (20) may be placed between the lower first copper structure (150_D) and the upper first base copper layer (130_U).
  • the second power semiconductor element (30) may be placed between the lower second copper structure (160_D) and the upper first base copper layer (130_U).
  • the second power semiconductor element (30) may have a smaller thickness than the first power semiconductor element (20).
  • At least one of the lower first copper structure (150_D) and the lower second copper structure (160_D) may have a differential porosity and may include a region on the upper side having a lower porosity than the lower side that is relatively adjacent to the lower first base copper layer (130_D).
  • the double-sided cooling power module (10c) of FIG. 15 has a difference in that it further includes a lower first active metal brazing layer (125_D) interposed between the lower ceramic layer (120_D) and the lower first base copper layer (130_D), a lower second active metal brazing layer (126_D) interposed between the lower ceramic layer (120_D) and the lower second base copper layer (140_D), an upper first active metal brazing layer (125_U) interposed between the upper ceramic layer (120_U) and the upper first base copper layer (130_U), and an upper second active metal brazing layer (126_U) interposed between the upper ceramic layer (120_U) and the upper second base copper layer (140_U).
  • the double-sided cooling type power module (10c) of Fig. 15 has a difference in that it includes an upper ceramic substrate (110a_U) instead of an upper ceramic circuit substrate (100a_U). That is, the double-sided cooling type power module (10c) does not include an upper first copper structure (150_U) and an upper second copper structure (160_U). Therefore, the double-sided cooling type power module (10c) may have an asymmetrical structure with respect to the first power semiconductor element (20) and the second power semiconductor element (30).
  • a method for manufacturing a double-sided cooling power module comprises the steps of: providing a lower ceramic circuit board comprising: a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and one or more lower second copper structures disposed on at least a portion of the lower first copper structure; mounting a first power semiconductor device on the lower first copper structure; mounting a second power semiconductor device having a smaller thickness than the first power semiconductor device on the lower second copper structure; disposing an upper ceramic circuit board, on the lower ceramic circuit board, comprising: an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer; an upper first copper structure disposed on a portion of the upper ceramic substrate; and one or more upper second copper structures disposed on at least a portion of the upper first copper structure; facing the lower ceramic circuit board; and a step of forming a mold layer covering the first power semiconductor element and the second power semiconductor element by filling the space between the lower ceramic circuit board and the
  • a method for manufacturing a double-sided cooling power module may include the steps of: providing a lower ceramic circuit board including a lower ceramic substrate including a lower ceramic layer and a lower first base copper layer; a lower first copper structure disposed on a portion of the lower ceramic substrate; and one or more lower second copper structures disposed on at least a portion of the lower first copper structure; mounting a first power semiconductor element on the lower first copper structure; mounting a second power semiconductor element having a smaller thickness than the first power semiconductor element on the lower second copper structure; arranging an upper ceramic substrate including an upper ceramic layer and an upper first base copper layer on the lower ceramic circuit board so as to face the lower ceramic circuit board; and forming a mold layer that fills a space between the lower ceramic circuit board and the upper ceramic substrate to cover the first power semiconductor element and the second power semiconductor element.
  • At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure can be formed by printing, pressing, and sintering of a copper-containing paste at a temperature ranging from 500° C. to 800° C.
  • a surface of at least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure can be blasted.
  • At least one of the lower first copper structure, the upper first copper structure, the lower second copper structure, and the upper second copper structure may have a differential porosity, and may include a region on the upper side having a lower porosity than a region on the lower side that is relatively adjacent to the upper first base copper layer or the lower first base copper layer.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

La présente invention concerne une carte de circuit imprimé en céramique ayant d'excellentes performances de dissipation de chaleur grâce à une structure en cuivre, son procédé de fabrication, et un module d'alimentation de type à refroidissement double face la comprenant. La carte de circuit imprimé en céramique selon un mode de réalisation de la présente invention comprend : un substrat en céramique comprenant une couche de céramique et une première couche de cuivre de base disposée sur une première surface de la couche de céramique ; et une première structure en cuivre disposée sur une zone partielle de la première couche de cuivre de base, formée par impression, compression et frittage d'une pâte contenant du cuivre, ayant une porosité différentielle, et comprenant une zone ayant une porosité inférieure à un côté inférieur relativement adjacent à la première couche de cuivre de base sur un côté supérieur de celle-ci.
PCT/KR2024/006529 2023-06-29 2024-05-14 Carte de circuit imprimé en céramique, son procédé de fabrication et module d'alimentation de type à refroidissement double face la comprenant Pending WO2025005458A1 (fr)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
KR20230084314 2023-06-29
KR10-2023-0084313 2023-06-29
KR20230084315 2023-06-29
KR10-2023-0084315 2023-06-29
KR10-2023-0084314 2023-06-29
KR20230084313 2023-06-29
KR20230114523 2023-08-30
KR10-2023-0114523 2023-08-30
KR10-2024-0061407 2024-05-09
KR10-2024-0061409 2024-05-09
KR1020240061407A KR20250001881A (ko) 2023-06-29 2024-05-09 세라믹 회로 기판, 그 제조방법, 및 이를 구비한 양면 냉각형 파워 모듈
KR1020240061409A KR20250001883A (ko) 2023-06-29 2024-05-09 세라믹 회로 기판, 그 제조방법, 및 이를 구비한 양면 냉각형 파워 모듈

Publications (1)

Publication Number Publication Date
WO2025005458A1 true WO2025005458A1 (fr) 2025-01-02

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PCT/KR2024/006529 Pending WO2025005458A1 (fr) 2023-06-29 2024-05-14 Carte de circuit imprimé en céramique, son procédé de fabrication et module d'alimentation de type à refroidissement double face la comprenant

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WO (1) WO2025005458A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228804A (ja) * 2005-02-15 2006-08-31 Fuji Electric Holdings Co Ltd 半導体モジュール用セラミックス回路基板及びその製造方法
JP6096094B2 (ja) * 2013-10-28 2017-03-15 日本発條株式会社 積層体、絶縁性冷却板、パワーモジュールおよび積層体の製造方法
KR20220109171A (ko) * 2021-01-28 2022-08-04 주식회사 알엔투세라믹스 냉각 핀을 구비한 양면 냉각형 파워 모듈용 세라믹 회로 기판, 그 제조방법 및 이를 구비한 양면 냉각형 파워 모듈
KR20230066662A (ko) * 2017-06-09 2023-05-16 덴카 주식회사 세라믹스 회로 기판
KR20230087833A (ko) * 2021-12-10 2023-06-19 현대자동차주식회사 양면 냉각형 파워모듈 제조 방법 및 양면 냉각형 파워모듈

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228804A (ja) * 2005-02-15 2006-08-31 Fuji Electric Holdings Co Ltd 半導体モジュール用セラミックス回路基板及びその製造方法
JP6096094B2 (ja) * 2013-10-28 2017-03-15 日本発條株式会社 積層体、絶縁性冷却板、パワーモジュールおよび積層体の製造方法
KR20230066662A (ko) * 2017-06-09 2023-05-16 덴카 주식회사 세라믹스 회로 기판
KR20220109171A (ko) * 2021-01-28 2022-08-04 주식회사 알엔투세라믹스 냉각 핀을 구비한 양면 냉각형 파워 모듈용 세라믹 회로 기판, 그 제조방법 및 이를 구비한 양면 냉각형 파워 모듈
KR20230087833A (ko) * 2021-12-10 2023-06-19 현대자동차주식회사 양면 냉각형 파워모듈 제조 방법 및 양면 냉각형 파워모듈

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