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WO2014115929A1 - Boîtier étanche d'une puce à semi-conducteurs et procédé de traitement associé - Google Patents

Boîtier étanche d'une puce à semi-conducteurs et procédé de traitement associé Download PDF

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Publication number
WO2014115929A1
WO2014115929A1 PCT/KR2013/003399 KR2013003399W WO2014115929A1 WO 2014115929 A1 WO2014115929 A1 WO 2014115929A1 KR 2013003399 W KR2013003399 W KR 2013003399W WO 2014115929 A1 WO2014115929 A1 WO 2014115929A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
metal
layer
chip
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2013/003399
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English (en)
Korean (ko)
Inventor
권명호
이호준
정한
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I3SYSTEM Inc
Original Assignee
I3SYSTEM Inc
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Filing date
Publication date
Application filed by I3SYSTEM Inc filed Critical I3SYSTEM Inc
Publication of WO2014115929A1 publication Critical patent/WO2014115929A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal

Definitions

  • the present invention relates to a sealed package and a process method of a semiconductor chip, and more particularly, to place a semiconductor chip to be sealed from the outside on a lower wiring board chip including a metal wiring for signal transmission, and serves as a lower wiring board chip and a cover.
  • the present invention relates to a hermetic package and a process method of a semiconductor chip which are manufactured by sealing a semiconductor chip by soldering a metal sealing part formed at a predetermined position of an upper cover substrate.
  • the conventional hermetic package of the semiconductor chip mainly used a metal package or a ceramic package.
  • a wafer-level package In the case of a wafer-level package, it consists of a semiconductor chip in which a sensor part etc. were formed, and the cover substrate which is joined with a semiconductor chip, and cuts off a sensor part from the exterior.
  • the senor when the sensor is manufactured on a signal acquisition circuit board for driving the same, it is advantageous to reduce the size of a single semiconductor chip because the price of the signal acquisition circuit board manufactured by an external foundry service company is expensive.
  • the wafer-level package requires a metal seal for sealing on the signal acquisition circuit board and a bonding pad in the outer area of the metal seal, which inevitably increases the size of the semiconductor chip, which leads to a low production rate and high manufacturing cost. You lose.
  • a signal acquisition circuit board manufactured by an external company has a problem in that it is difficult to manage in terms of quality control of the substrate surface for sealing.
  • FIG. 1 is a process of dicing a signal acquisition circuit board 100 including a signal acquisition circuit 113 to operate a sensor 111, a sensor 111 and a substrate formed on the substrate, and dividing it into a semiconductor chip 110. It is a form of.
  • the signal generated from the sensor 111 is converted into an electrical signal in the signal acquisition circuit 113, and the electrical signal is transmitted to the external package through the bonding pad 112.
  • 2 is a shape of a hermetic package method using a conventional metal and ceramic.
  • the semiconductor chip 110 is bonded to an existing metal package or ceramic package 120, and the wire bonding 114 is bonded to the bonding pad 112 and the package feedthrough on the semiconductor chip for electrical signal transmission.
  • Processing 122 is performed.
  • the lid 126 made of a wafer, ceramic or metal or the like and the metal seal 117 of the metal or ceramic substrate 120 described above are soldered 119 to seal.
  • FIG 3 shows the shape of the signal acquisition circuit board 200 of the conventional wafer level package manufactured to solve the disadvantages of the metal or ceramic package.
  • the signal acquisition circuit board 200 including the metal sealing unit 215 is separated into a single semiconductor chip 210 for the wafer level package, and the metal sealing unit 215 is included in the signal acquisition circuit board 200. Therefore, it can be seen that the size of the diced semiconductor chip 210 becomes larger than the size of the semiconductor chip 110 that is combined with the existing metal and ceramic package 120.
  • an object of the present invention is to improve the size, weight, and high manufacturing cost of the conventional metal and ceramic packages, and also to improve the conventional wafer level package.
  • Forming a metal sealing part for sealing directly on the signal acquisition circuit board does not increase the size of a single semiconductor chip by using a cheap wiring board having a metal wiring for transmitting a signal and a metal sealing part for sealing, so that the signal acquisition circuit is not increased.
  • Increasing the amount of semiconductor chip production compared to the substrate and using only good quality semiconductor chips can minimize the loss of the cover substrate due to defects.
  • Another object of the present invention is that the sensor manufacturer can easily apply the wafer-level package because the quality control for sealing can be provided through a wiring board and a cover board that can be easily manufactured directly instead of a signal acquisition circuit board manufactured by an external company. In order to reduce the manufacturing cost.
  • a semiconductor chip 110 attached to an upper side of the wiring board chip and having a sensor 111 formed on an upper end thereof;
  • a metal wire 314 having one side connected to the bonding pad and the other side connected to the metal wiring layer;
  • a plurality of metal wiring layers 311 formed at a predetermined distance apart from the wiring board chip to transfer electrical signals generated from the semiconductor chips;
  • An insulating layer 312 formed on an upper end of the metal wiring layer to protect the metal wiring layer;
  • solder layer 319 formed at both ends of the wall to seal the metal sealing layer and the wall of the wiring board chip and the cover substrate, thereby solving the problems of the present invention.
  • Inexpensive wiring boards with metal sealing parts for wiring and sealing do not increase the size of a single semiconductor chip, increasing semiconductor chip production compared to signal acquisition circuit boards, and using only good quality semiconductor chips. It will provide an effect that can be minimized.
  • quality control for sealing can be provided through wiring boards and cover boards that can be easily manufactured instead of signal acquisition circuit boards manufactured by external companies, so that sensor manufacturers can easily apply wafer-level packages. Can be lowered.
  • the area loss of the expensive semiconductor chip generated due to the metal sealing part can be reduced, thereby reducing the manufacturing cost.
  • the metal sealing part is formed on the wiring board and the cover board, which can be easily manufactured, soldering is performed for sealing. Therefore, it is manufactured through an external foundry service company in terms of quality control such as the board and chip surface state required for sealing. It is advantageous in terms of process control because it is not necessary to form a metal seal on the signal acquisition circuit board which cannot be managed.
  • the signal acquisition circuit board and the cover board proposed in the prior art are collectively bonded to compensate for the disadvantage that the cover board is consumed even in a defective semiconductor chip.
  • FIG. 1 is an exemplary diagram showing a shape obtained by dicing a signal acquisition circuit board on which a conventional sensor is formed with a semiconductor chip.
  • FIG. 2 is a cross-sectional view illustrating a package method of sealing a semiconductor chip on which a conventional sensor is formed using an existing metal and a ceramic.
  • FIG 3 is an exemplary view showing a shape in which a signal acquisition circuit board of a conventional wafer level package is separated by a semiconductor chip.
  • FIG. 4 is a cross-sectional view illustrating a wafer level package method of sealing a semiconductor chip including a sensor, a bonding pad, a metal seal, and a signal acquisition circuit and a cover substrate by soldering a metal seal.
  • FIG. 5 is an exemplary diagram illustrating a shape in which a wiring board of a hermetic package of a semiconductor chip is diced into a wiring board chip and then combined with a semiconductor chip on which a sensor is formed.
  • FIG. 6 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 7 is a flowchart illustrating a method of manufacturing a sealed package of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to a third embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an exemplary embodiment of the present invention.
  • a semiconductor chip 110 attached to an upper side of the wiring board chip and having a sensor 111 formed on an upper end thereof;
  • a metal wire 314 having one side connected to the bonding pad and the other side connected to the metal wiring layer;
  • a plurality of metal wiring layers 311 formed at a predetermined distance apart from the wiring board chip to transfer electrical signals generated from the semiconductor chips;
  • An insulating layer 312 formed on an upper end of the metal wiring layer to protect the metal wiring layer;
  • solder layer 319 formed at both ends of the wall to seal the metal sealing layer and the wall of the wiring board chip and the cover substrate.
  • a semiconductor chip 110 attached to an upper side of the wiring board chip and having a sensor 111 formed on an upper end thereof;
  • a metal wire 314 having one side connected to the bonding pad and the other side connected to the metal wiring layer;
  • a plurality of metal wiring layers 311 formed at a predetermined distance apart from the wiring board chip to transfer electrical signals generated from the semiconductor chips;
  • An insulating layer 312 formed on an upper end of the metal wiring layer to protect the metal wiring layer;
  • solder layer 319 formed between the wiring board chip and the metal sealing layer of the cover board to seal the wiring board chip and the cover board.
  • the semiconductor chip is formed at the etched position by etching the position where the semiconductor chip is disposed above,
  • the wiring board chip is thicker than the semiconductor chip, and the etching is characterized by etching more than the thickness of the semiconductor chip.
  • the semiconductor chip is formed at the etched position by etching the position where the semiconductor chip is disposed below,
  • the cover substrate is thicker than the semiconductor chip, and the etching is characterized by etching more than the thickness of the semiconductor chip.
  • the sum of the etching depth of the wiring board chip 310 and the etching depth of the cover board is greater than or equal to the thickness of the semiconductor chip.
  • It is characterized by consisting of a stack of one or more of silicon, metal, ceramic.
  • Al, Ti, Cr, Ni, Pt, Au is composed of one or two or more laminates, or is characterized by consisting of two or more alloys.
  • It is characterized by consisting of silicon oxide or silicon nitride.
  • Ti, Cr, Pt, Ni, Au, In, Sn, Ag, Pb, Sn, Bi, Sb, Cd, Cu is composed of one or two or more laminates, or is characterized by consisting of two or more alloys.
  • Silicon, germanium, Kovar, Invar it is characterized by consisting of one or two or more laminates of ceramic.
  • Silicon, Kovar, Invar characterized in that it is composed of any one of a metal and a ceramic.
  • the semiconductor chip is an image sensor that requires light transmission, it is characterized in that the non-reflective coating.
  • It is characterized by being more than the thickness of a semiconductor chip.
  • Soldering step (S170) for placing and soldering the wall between the wiring board chip 310 and the cover substrate 316;
  • FIG. 1 is an exemplary diagram showing a shape obtained by dicing a signal acquisition circuit board on which a conventional sensor is formed with a semiconductor chip.
  • a semiconductor chip 110 including a conventional sensor 111, a bonding pad 112, and a signal acquisition circuit 113 may be formed of a semiconductor chip 110.
  • a bonding pad 112 capable of transmitting an electrical signal of the signal acquisition circuit is configured at a predetermined position of the semiconductor chip 110.
  • FIG. 2 is a cross-sectional view illustrating a package method of sealing a semiconductor chip on which a conventional sensor is formed using an existing metal and a ceramic.
  • FIG 3 is an exemplary view showing a shape in which a signal acquisition circuit board of a conventional wafer level package is separated by a semiconductor chip.
  • an exemplary view manufactured to solve the disadvantages of the conventional metal or ceramic package includes a sensor 211, a bonding pad 212, a metal seal 214, and a conventional wafer-level package.
  • a bonding pad 212 capable of transmitting an electrical signal of the signal acquisition circuit 213 is configured in the outer portion of the metal sealing 214 of the semiconductor chip 210.
  • FIG. 4 is a cross-sectional view illustrating a wafer level package method of sealing a semiconductor chip including a sensor, a bonding pad, a metal seal, and a signal acquisition circuit and a cover substrate by soldering a metal seal.
  • a bonding pad 212 capable of transmitting an electrical signal of the signal acquisition circuit is configured at a predetermined position outside the metal seal 215 on the wafer level package chip 210.
  • FIG. 5 is an exemplary diagram illustrating a shape in which a wiring board of a hermetic package of a semiconductor chip is diced into a wiring board chip and then combined with a semiconductor chip on which a sensor is formed.
  • FIG. 6 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • a semiconductor chip including a sensor is attached to an upper end of a wiring board chip including a metal wiring layer and a metal sealing part capable of transmitting a signal.
  • a semiconductor chip 110 attached to an upper side of the wiring board chip and having a sensor 111 formed on an upper end thereof;
  • a metal wire 314 having one side connected to the bonding pad and the other side connected to the metal wiring layer;
  • a plurality of metal wiring layers 311 formed at a predetermined distance apart from the wiring board chip to transfer electrical signals generated from the semiconductor chips;
  • An insulating layer 312 formed on an upper end of the metal wiring layer to protect the metal wiring layer;
  • solder layer 319 formed at both ends of the wall to seal the metal sealing layer and the wall of the wiring board chip and the cover substrate.
  • a semiconductor chip is disposed above the wiring board chip 310, and a sensor 111 is formed on an upper end of the semiconductor chip 110.
  • a plurality of bonding pads 112 are spaced apart from the semiconductor chip at a predetermined distance.
  • the metal wiring layer 311 is spaced apart at a predetermined distance from the upper end of the wiring board chip to form a plurality to serve to transfer the electrical signal generated from the semiconductor chip.
  • one side of the metal wire 314 is connected to the bonding pad, and the other side of the metal wire 314 is connected to the metal wiring layer.
  • the insulating layer 312 is formed on the upper portion of the metal wiring layer to protect the metal wiring layer, and the insulating film opening portion 313 is formed at a predetermined position above the metal wiring layer. It will serve to form.
  • the metal sealing layer 315 is formed on top of the insulating layer to provide sealing through soldering of the solder layer.
  • the cover substrate 316 having the metal sealing layer 317 is formed.
  • a wall 318 is formed between the wiring board chip and the cover board, and a solder layer 319 is formed at both ends of the wall to seal the metal sealing layer and the wall of the wiring board chip and the cover board through soldering. Will be done.
  • FIG. 7 is a flowchart illustrating a method of manufacturing a sealed package of a semiconductor chip according to an embodiment of the present invention.
  • Soldering step (S170) for placing and soldering the wall between the wiring board chip 310 and the cover substrate 316;
  • a method of packaging a semiconductor chip in a hermetic package is prepared by first preparing a wiring board chip and forming a metal wiring layer 311 on an upper surface of the wiring board chip (S100).
  • an insulating layer 312 is formed on the upper portion of the metal wiring layer to protect the metal wiring layer (S110), and the insulating film opening part 313 which forms an electrical passage by removing a portion of the insulating layer at a predetermined position above the metal wiring layer is formed. It is formed (S120).
  • a metal sealing layer 315 is formed on the insulating layer layer (S130), and the semiconductor chip 110 having the sensor 111 formed on the wiring board chip 310 is attached thereto. (S140).
  • the bonding pad 112 formed on the semiconductor chip and the metal wiring layer 311 of the wiring board chip are connected to the metal wire 314 (S150).
  • the cover substrate is prepared, the bottom of the cover substrate 316 is prepared.
  • the metal sealing layer 317 is formed at step S160, a wall is disposed between the wiring board chip 310 and the cover substrate 316, and the solder layer is sealed by soldering (S170).
  • the wiring board chip in which the sensor is sealed with the cover substrate is diced in a sealed package chip unit (S180) to be finally finished.
  • the wiring board chip 310 is composed of one or two or more laminates of general silicon, metal, and ceramic, and the metal wiring layer 311 includes one or two or more of Al, Ti, Cr, Ni, Pt, and Au. It must consist of a laminate or consist of two or more alloys.
  • the insulating layer 312 should be made of silicon oxide or silicon nitride, and the metal sealing layers 315 and 317 may include Ti, Cr, Pt, Ni, Au, In, Sn, Ag, Pb, Sn, It must consist of one or more laminates of Bi, Sb, Cd, Cu, or consist of two or more alloys.
  • cover substrate 316 is composed of one or two or more laminates of silicon, germanium, Kovar, Invar, ceramic, and the wall 318 is composed of any one of silicon, Kovar, Invar, metal and ceramic. It features.
  • the solder layer 319 is soldered, so that one or two or more laminates of Pb, Sn, In, Ag, Au, Cu, and Bi, or two or more alloys.
  • the cover substrate 316 is characterized in that the anti-reflective coating when the semiconductor chip is an image sensor requiring light transmission
  • the wall 318 is characterized in that the thickness of the semiconductor chip or more.
  • the height of the semiconductor chip 110 is mostly 0.6 mm or more.
  • the cover substrate 316 is the sensor 111. It touches the surface and hurts.
  • the wall 318 plays a role of separating the cover board and the wiring board, and in the case of FIG. 8, the wiring board and the cover board are more than the semiconductor chip.
  • the thick solder layer 319 is used instead of the wall 318 to separate the height
  • the semiconductor chip 110 is positioned therebetween.
  • the height of the wall must be higher than the height of the semiconductor chip to prevent the cover substrate and the sensor from coming off.
  • FIG. 8 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • the hermetic package of the semiconductor chip according to this embodiment is
  • a solder layer 319 thicker than the solder layer formed on both ends of the wall except for the wall is formed in one embodiment.
  • FIG. 9 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to a third embodiment of the present invention.
  • the semiconductor chip of the wiring board chip 310 is etched so that the semiconductor chip is formed at the etched position.
  • the characteristic is that the wiring board chip is thicker than the semiconductor chip, the etching should be etched more than the thickness of the semiconductor chip.
  • FIG. 10 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an embodiment of the present invention.
  • the semiconductor chip of the cover substrate 316 is etched so that the semiconductor chip is formed at the etched position.
  • the characteristic is that the cover substrate is thicker than the semiconductor chip, the etching is etched more than the thickness of the semiconductor chip.
  • FIG. 11 is a cross-sectional view illustrating a hermetic package of a semiconductor chip according to an exemplary embodiment of the present invention.
  • the position where the semiconductor chip of the wiring board chip 310 is disposed on the upper side is etched and the position where the semiconductor chip of the cover substrate 316 is disposed on the lower side is etched.
  • the characteristic is that the sum of the etching depth of the wiring board chip 310 and the etching depth of the cover substrate is equal to or greater than the thickness of the semiconductor chip.
  • the reason for forming the etching is to prevent the contact between the sensor surface and the cover substrate.
  • the configuration and process as described above are for manufacturing a hermetic package of a semiconductor chip, which is a package method of sealing with a cover substrate by using a wiring board chip on which the semiconductor chip is to be placed.
  • a semiconductor chip to be sealed from the outside is placed on a lower wiring board chip including a metal wiring for signal transmission, and the semiconductor sealing is formed by soldering a metal sealing part formed at a predetermined position of the lower wiring board chip and an upper cover board serving as a cover. It is possible to provide a hermetic package of a semiconductor chip that is manufactured by sealing the chip, which may be usefully used in the semiconductor chip package field.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

La présente invention se rapporte à un boîtier scellé d'une puce à semi-conducteurs et à un procédé de traitement et, plus particulièrement, à un boîtier scellé d'une puce à semi-conducteurs et à un procédé de traitement permettant de fabriquer ce dernier en plaçant une puce à semi-conducteurs qui doit être tenue de façon étanche par rapport à l'extérieur, sur une puce de substrat de fil inférieur qui comporte un fil métallique destiné à transmettre un signal, et en scellant la puce à semi-conducteurs en soudant une partie de scellage métallique formée à une position prédéterminée de la puce de substrat de fil inférieur et un substrat de revêtement supérieur qui fait office de revêtement.
PCT/KR2013/003399 2013-01-22 2013-04-22 Boîtier étanche d'une puce à semi-conducteurs et procédé de traitement associé Ceased WO2014115929A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2013-0006824 2013-01-22
KR1020130006824A KR101470946B1 (ko) 2013-01-22 2013-01-22 반도체칩의 밀폐형 패키지 및 공정 방법

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US9508676B1 (en) 2015-08-10 2016-11-29 Chipbond Technology Corporation Semiconductor package structure having hollow chamber and bottom substrate and package process thereof
CN114783956A (zh) * 2022-03-17 2022-07-22 深圳大道半导体有限公司 半导体芯片封装体及其制造方法
WO2023098004A1 (fr) * 2021-12-01 2023-06-08 华进半导体封装先导技术研发中心有限公司 Structure d'interconnexion d'emballage étanche à l'air intégrée tridimensionnelle et son procédé de fabrication

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US20170053879A1 (en) * 2015-08-21 2017-02-23 Infineon Technologies Ag Method, a semiconductor device and a layer arrangement
CN111698824B (zh) * 2020-05-22 2022-03-08 中国电子科技集团公司第二十九研究所 一种自气密封装功能模块的一体化互联结构及实现方法

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