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WO2025048866A1 - Circuit de sortie pour un réseau de multiplication vecteur-matrice - Google Patents

Circuit de sortie pour un réseau de multiplication vecteur-matrice Download PDF

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Publication number
WO2025048866A1
WO2025048866A1 PCT/US2023/081167 US2023081167W WO2025048866A1 WO 2025048866 A1 WO2025048866 A1 WO 2025048866A1 US 2023081167 W US2023081167 W US 2023081167W WO 2025048866 A1 WO2025048866 A1 WO 2025048866A1
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Prior art keywords
voltage
current
converter
analog
array
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Hieu Van Tran
Andrew Kunil Choe
Hoa Vu
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Silicon Storage Technology Inc
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Silicon Storage Technology Inc
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Priority to TW113126826A priority Critical patent/TW202509816A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions

Definitions

  • Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other.
  • Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning.
  • neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network.
  • the neurons at each level individually or collectively make a decision based on the received data from the synapses.
  • One of the major challenges in the development of artificial neural networks for high- performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. Attorney Docket Number: 351913-980712 However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation.
  • CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses.
  • Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference.
  • the non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns.
  • the neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs.
  • the first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region.
  • Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate.
  • Non-Volatile Memory Cells are well known.
  • U.S. Patent 5,029,130 (“the ’130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells.
  • Such a memory cell 210 is shown in Figure 2.
  • Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between.
  • Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14.
  • Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up Attorney Docket Number: 351913-980712 and over the floating gate 20.
  • the floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide.
  • Bitline 24 is coupled to drain region 16.
  • Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.
  • FN Fowler-Nordheim
  • Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22, and a positive voltage on the source region 14. Electron current will flow from the drain region 16 towards the source region 14. The electrons will accelerate and become heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20. [0010] Memory cell 210 is read by placing positive read voltages on the drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal).
  • SSI source side injection
  • the floating gate 20 is positively charged (i.e., erased of electrons), then the portion of the channel region 18 under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
  • Table No.1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations: Table No.1: Operation of Flash Memory Cell 210 of Figure 2 WL BL SL Read 2-3V 0.6-2V 0V Erase ⁇ 11-13V 0V 0V Attorney Docket Number: 351913-980712 Program 1-2V 10.5- 9-10V 3 ⁇ A [0012] Other split gate memory cell configurations, which are other types of flash memory cells, are known.
  • Figure 3 depicts a four-gate memory cell 310 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, a select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14.
  • WL word line
  • all gates are non-floating gates except floating gate 20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.
  • Table No.2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No.2: Operation of Flash Memory Cell 310 of Figure 3 WL/SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V Erase -0.5V/0V 0V 0V/-8V 8-12V 0V Program 1V 0.1- 8-11V 4.5-9V 4.5-5V 1 ⁇ A [0014] Figure 4 depicts a three-gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is identical to the memory cell 310 of Figure 3 except that memory cell 410 does not have a separate control gate.
  • the erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of the Figure 3 except there is no control gate bias applied.
  • the programming operation also is done without the control gate bias, Attorney Docket Number: 351913-980712 and as a result, a higher voltage is applied on the source line during a program operation to compensate for a lack of control gate bias.
  • Table No.3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations: Table No.3: Operation of Flash Memory Cell 410 of Figure 4 WL/SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V Erase -0.5V/0V 0V 11.5V 0V Program 1V 0.2- 4.5V 7-9V 3 ⁇ A [0016] Figure 5 depicts stacked gate memory cell 510, which is another type of flash memory cell.
  • Memory cell 510 is similar to memory cell 210 of Figure 2, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown).
  • the erase is done by FN tunneling of electrons from FG to substrate, programming is by channel hot electron (CHE) injection at region between the channel 18 and the drain region 16, by the electrons flowing from the source region 14 towards to drain region 16 and read operation which is similar to that for memory cell 210 with a higher control gate voltage.
  • CHE channel hot electron
  • Table No.4 depicts typical voltage ranges that can be applied to the terminals of memory cell 510 and substrate 12 for performing read, erase, and program operations: Table No.4: Operation of Flash Memory Cell 510 of Figure 5 C G BL SL Substrate Read 2-5V 0.6 – 2V 0V 0V Erase -8 to -10V/0V FLT FLT 8-10V / 15-20V Attorney Docket Number: 351913-980712 Program 8-12V 3-5V 0V 0V [0018] The methods and means described herein may apply to other non-volatile memory technologies such as FINFET split gate flash or stack gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide- silicon, metal charge trap in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic RAM (magne
  • the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as further explained below.
  • continuous (analog) programming of the memory cells is provided.
  • the memory state (i.e., charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, and vice-versa, independently and with minimal disturbance of other memory cells.
  • FIG. 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present examples. This example uses the non-volatile memory array neural network for a facial recognition application, but any other appropriate application could be implemented using a non-volatile memory array based neural network.
  • S0 is the input layer, which for this example is a 32x32 pixel RGB image with 5 bit precision (i.e. three 32x32 pixel arrays, one for each color R, G and B, each pixel being 5 bit Attorney Docket Number: 351913-980712 precision).
  • the synapses CB1 going from input layer S0 to layer C1 apply different sets of weights in some instances and shared weights in other instances and scan the input image with 3x3 pixel overlapping filters (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model).
  • values for 9 pixels in a 3x3 portion of the image are provided to the synapses CB1, where these 9 input values are multiplied by the appropriate weights and, after summing the outputs of that multiplication, a single output value is determined and provided by a first synapse of CB1 for generating a pixel of one of the feature maps of layer C1.
  • the 3x3 filter is then shifted one pixel to the right within input layer S0 (i.e., adding the column of three pixels on the right, and dropping the column of three pixels on the left), whereby the 9 pixel values in this newly positioned filter are provided to the synapses CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse.
  • This process is continued until the 3x3 filter scans across the entire 32x32 pixel image of input layer S0, for all three colors and for all bits (precision values).
  • the process is then repeated using different sets of weights to generate a different feature map of layer C1, until all the features maps of layer C1 have been calculated.
  • layer C1 in the present example, there are 16 feature maps, with 30x30 pixels each. Each pixel is a new feature pixel extracted from multiplying the inputs and kernel, and therefore each feature map is a two dimensional array, and thus in this example layer C1 constitutes 16 layers of two dimensional arrays (keeping in mind that the layers and arrays referenced herein are logical relationships, not necessarily physical relationships – i.e., the arrays are not necessarily oriented in physical two dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synapse weights applied to the filter scans. The C1 feature maps could all be directed to different aspects of the same image feature, such as boundary identification.
  • the first map (generated using a first weight set, shared for all scans used to generate this first map) could identify circular edges
  • the second map (generated using a second weight set different from the first weight set) could identify rectangular edges, or the aspect ratio of certain features, and so on.
  • An activation function P1 (pooling) is applied before going from layer C1 to layer S1, which pools values from consecutive, non-overlapping 2x2 regions in each feature map.
  • the purpose of the pooling function P1 is to average out the nearby location (or a max function can Attorney Docket Number: 351913-980712 also be used), to reduce the dependence of the edge location for example and to reduce the data size before going to the next stage.
  • the synapses CB2 going from layer S1 to layer C2 scan maps in layer S1 with 4x4 filters, with a filter shift of 1 pixel.
  • the activation function P2 (pooling) is applied before going from layer C2 to layer S2, which pools values from consecutive non-overlapping 2x2 regions in each feature map.
  • An activation function (pooling) is applied at the synapses CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 via a respective synapse of CB3.
  • Each layer of synapses is implemented using an array, or a portion of an array, of non- volatile memory cells.
  • Figure 7 is a block diagram of an array that can be used for that purpose.
  • VMM array 32 includes non-volatile memory cells and is utilized as the synapses (such as CB1, CB2, CB3, and CB4 in Figure 6) between one layer and the next layer.
  • VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoder 34, control gate decoder 35, bit line decoder 36 and source line decoder 37, which decode the respective inputs for the non-volatile memory cell array 33.
  • Input to VMM array 32 can be from the erase gate and wordline gate decoder 34 or from the control gate decoder 35.
  • Source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33.
  • Non-volatile memory cell array 33 serves two purposes. First, it stores the weights that will be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them up per output line (source line or bit line) to produce the output, which will be the input to the next layer or input to the final layer. By performing the multiplication and addition function, Attorney Docket Number: 351913-980712 the non-volatile memory cell array 33 removes the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory computation.
  • the output of non-volatile memory cell array 33 is supplied to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums up the outputs of the non-volatile memory cell array 33 to create a single value for that convolution.
  • the differential summer 38 is arranged to perform summation of positive weight and negative weight.
  • the summed-up output values of differential summer 38 are then supplied to an activation function block 39, which rectifies the output.
  • the activation function block 39 may provide sigmoid, tanh, or ReLU functions.
  • the rectified output values of activation function block 39 become an element of a feature map as the next layer (e.g.
  • non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from the prior layer of neurons or from an input layer such as an image database), and summing op-amp 38 and activation function block 39 constitute a plurality of neurons.
  • VMM array 32 in Figure 7 can be analog level, binary level, or digital bits (in which case a DAC is provided to convert digital bits to appropriate input analog level) and the output can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert output analog level into digital bits).
  • Figure 8 is a block diagram depicting the usage of numerous layers of VMM arrays 32, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e.
  • the input is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a.
  • the converted analog inputs could be voltage or current.
  • the input D/A conversion for the first layer could be done by using a function or a LUT (look up table) that maps the inputs Inputx to appropriate analog levels for the matrix multiplier of input VMM array 32a.
  • the input conversion could also be done by an analog to analog (A/A) converter to convert an external analog input to a mapped analog input to the input VMM array 32a.
  • FIG 8 contains five layers (32a,32b,32c,32d,32e): one input layer (32a), two hidden layers (32b,32c), and two fully connected layers (32d,32e).
  • VMM Vector-by-Matrix Multiplication
  • Figure 9 depicts neuron VMM array 900, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 900 comprises memory array 901 of non-volatile memory cells and reference array 902 (at the top of the array) of non-volatile reference memory cells. Alternatively, another reference array can be placed at the bottom.
  • control gate lines such as control gate line 903, run in a vertical direction (hence reference array 902 in the row direction is orthogonal to control gate line 903)
  • erase gate lines such as erase gate line 904, run in a horizontal direction.
  • the inputs to VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the output of VMM array 900 emerges on the source lines (SL0, SL1).
  • the non-volatile memory cells of VMM array 900 i.e., the memory cells 310 of VMM array 900, may be configured to operate in a sub- threshold region.
  • Vthp is effective threshold voltage of the peripheral memory cell and Vtha is effective threshold voltage of the main (data) memory cell.
  • the threshold voltage of a transistor is a function of substrate body bias voltage and the substrate body bias voltage, denoted Vsb, can be modulated to compensate for various conditions, on such temperature.
  • a wordline or control gate can be used as the input for the memory cell for the input voltage.
  • a wordline or control gate or bitline or sourceline can be used as the input for the memory cell operated in the linear region.
  • the bitline or sourceline can be used as the output for the memory cell.
  • a memory cell such as a reference memory cell or a peripheral memory cell
  • a transistor operating in the linear region can be used to linearly convert an input/output current into an input/output voltage.
  • a wordline, control gate, or erase gate can be used as the input for the memory cell operated in the saturation region.
  • the bitline or sourceline can be used as the output for the output neuron.
  • the memory cells of VMM arrays described herein can be used in all regions or a combination thereof (sub threshold, linear, or saturation) for each layer or multi layers of a neural network.
  • Other examples for VMM array 32 of Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated by reference herein. As described in that application. a sourceline or a bitline can be used as the neuron output (current summation output).
  • Figure 10 depicts neuron VMM array 1000, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses between an input layer and the next layer.
  • VMM array 1000 comprises a memory array 1003 of non-volatile memory cells, reference array 1001 of first non-volatile reference memory cells, and reference array 1002 of second non- Attorney Docket Number: 351913-980712 volatile reference memory cells.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1014 (partially depicted) with current inputs flowing into them.
  • the reference cells are tuned (e.g., programmed) to target reference levels.
  • Memory array 1003 serves two purposes. First, it stores the weights that will be used by the VMM array 1000 on respective memory cells thereof. Second, memory array 1003 effectively multiplies the inputs (i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003 and then adds all the results (memory cell currents) to produce the output on the respective bit lines (BL0 - BLN), which will be the input to the next layer or input to the final layer.
  • the inputs i.e. current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert into the input voltages to supply to wordlines WL0, WL1, WL2, and WL3
  • memory array 1003 negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • the voltage inputs are provided on the word lines WL0, WL1, WL2, and WL3, and the output emerges on the respective bit lines BL0 - BLN during a read (inference) operation.
  • the current placed on each of the bit lines BL0 - BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bitline.
  • Table No.5 depicts operating voltages and currents for VMM array 1000.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • FIG. 10 Operation of VMM Array 1000 of Figure 10: WL WL -unsel BL BL -unsel SL SL -unsel Read 1-3.5V -0.5V/0V 0.6-2V (Ineuron) 0.6V-2V/0V 0V 0V Erase ⁇ 5-13V 0V 0V 0V 0V 0V Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT [0050]
  • Figure 11 depicts neuron VMM array 1100, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 1100 comprises a memory array 1103 of non-volatile memory cells, reference array 1101 of first non-volatile reference memory cells, and reference array 1102 of second non-volatile reference memory cells. Reference arrays 1101 and 1102 run in row direction of the VMM array 1100.
  • VMM array is similar to VMM 1000 except that in VMM array 1100, the word lines run in the vertical direction.
  • the inputs are provided on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output emerges on the source line (SL0, SL1) during a read operation.
  • the current placed on each source line performs a summing function of all the currents from the memory cells connected to that particular source line.
  • FIG. 6 Operation of VMM Array 1100 of Figure 11 WL WL -unsel BL BL -unsel SL SL -unsel Attorney Docket Number: 351913-980712 ⁇ 0.3-1V Read 1-3.5V -0.5V/0V 0.6-2V 0.6V-2V/0V (Ineuron) 0V SL-inhibit ( ⁇ 4- Erase ⁇ 5-13V 0V 0V 0V 0V 8V) Program 1-2V -0.5V/0V 0.1-3 uA Vinh ⁇ 2.5V 4-10V 0-1V/FLT [0052]
  • Figure 12 depicts neuron VMM array 1200, which is particularly suited for memory cells 310 as shown in Figure 3 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • VMM array 1200 comprises a memory array 1203 of non-volatile memory cells, reference array 1201 of first non-volatile reference memory cells, and reference array 1202 of second non-volatile reference memory cells.
  • Reference arrays 1201 and 1202 serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3.
  • the first and second non-volatile reference memory cells are diode-connected through multiplexors 1212 (partially shown) with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3.
  • Multiplexors 1212 each include a respective multiplexor 1205 and a cascoding transistor 1204 to ensure a constant voltage on the bitline (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation.
  • the reference cells are tuned to target reference levels.
  • Memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200.
  • memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, for which reference arrays 1201 and 1202 convert these current inputs into the input voltages to supply to the control gates (CG0, CG1, CG2, and CG3) by the weights stored in the memory array and then add all the results (cell currents) to produce the output, which appears on BL0 – BLN, and will be the input to the next layer or input to the final layer.
  • the memory array negates the need for separate multiplication and addition logic circuits and is also power efficient.
  • VMM array 1200 implements uni-directional tuning for non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (such that the wrong value is stored in the cell), the cell is erased and the sequence of partial programming operations starts over.
  • Table No.7 depicts operating voltages and currents for VMM array 1200.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, reference array 1301 or first non-volatile reference memory cells, and reference array 1302 of second non-volatile reference memory cells.
  • EG lines EGR0, EG0, EG1 and EGR1 are run vertically while CG lines CG0, CG1, CG2 and CG3 and SL lines WL0, WL1, WL2 and WL3 are run horizontally.
  • VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bi-directional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to reach the desired amount of charge on the floating gate due to the use of separate EG lines.
  • reference arrays 1301 and 1302 convert input current in the terminal BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells through multiplexors 1314) to be applied to the memory cells in the row direction.
  • the current output (neuron) is in the bit lines BL0 – BLN, where each bit line sums all currents from the non- volatile memory cells connected to that particular bitline.
  • Table No.8 depicts operating voltages and currents for VMM array 1300.
  • the columns in the table indicate the voltages placed on word lines for selected cells, word lines for unselected cells, bit lines for selected cells, bit lines for unselected cells, control gates for selected cells, control gates for unselected cells in the same sector as the selected cells, control gates for unselected cells in a different sector than the selected cells, erase gates for selected cells, erase gates for unselected cells, source lines for selected cells, and source lines for unselected cells.
  • the rows indicate the operations of read, erase, and program.
  • FIG. 23 depicts neuron VMM array 2300, which is particularly suited for memory cells 210 as shown in Figure 2 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • Figure 24 depicts neuron VMM array 2400, which is particularly suited for memory cells 210 as shown in Figure 2, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WLM, respectively, and the outputs OUTPUT0, ...
  • FIG. 25 depicts neuron VMM array 2500, which is particularly suited for memory cells 310 as shown in Figure 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on word lines WL 0 , ..., WL M , respectively, and the outputs OUTPUT 0 , ... OUTPUT N are generated on bit lines BL 0 , ..., BL N .
  • Figure 26 depicts neuron VMM array 2600, which is particularly suited for memory cells 410 as shown in Figure 4, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT 0, ..., INPUT n are received on vertical control gate lines CG0, ..., CGN, respectively, and the outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.
  • Figure 27 depicts neuron VMM array 2700, which is particularly suited for memory cells 410 as shown in Figure 4 and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • Figure 28 depicts neuron VMM array 2800, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • Figure 29 depicts neuron VMM array 2900, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on control gate lines CG 0 , ..., CG M .
  • Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical source lines SL 0 , ..., SL N , respectively, where each source line SL i is coupled to the source lines of all memory cells in column i.
  • Figure 30 depicts neuron VMM array 3000, which is particularly suited for memory cells 310 as shown in Figure 3, memory cells 510 as shown in Figure 5, and memory cells 710 as shown in Figure 7, and is utilized as the synapses and parts of neurons between an input layer and the next layer.
  • the inputs INPUT0, ..., INPUTM are received on control gate lines CG 0 , ..., CG M .
  • Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical bit lines BL 0 , ..., BLN, respectively, where each bit line BLi is coupled to the bit lines of all memory cells in column i.
  • Long Short-Term Memory [0067] The prior art includes a concept known as long short-term memory (LSTM). LSTM units often are used in neural networks. LSTM allows a neural network to remember information over Attorney Docket Number: 351913-980712 predetermined arbitrary time intervals and to use that information in subsequent operations.
  • a conventional LSTM unit comprises a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the time interval that the information is remembered in the LSTM.
  • FIG. 14 depicts an example LSTM 1400.
  • LSTM 1400 in this example comprises cells 1401, 1402, 1403, and 1404.
  • Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c 0 .
  • Cell 1402 receives input vector x 1 , the output vector (hidden state) h 0 from cell 1401 , and cell state c 0 from cell 1401 and generates output vector h 1 and cell state vector c1.
  • Cell 1403 receives input vector x2, the output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402 and generates output vector h2 and cell state vector c2.
  • Cell 1404 receives input vector x 3 , the output vector (hidden state) h 2 from cell 1403, and cell state c 2 from cell 1403 and generates output vector h3. Additional cells can be used, and an LSTM with four cells is merely an example.
  • Figure 15 depicts an example implementation of an LSTM cell 1500, which can be used for cells 1401, 1402, 1403, and 1404 in Figure 14.
  • LSTM cell 1500 receives input vector x(t), cell state vector c(t-1) from a preceding cell, and output vector h(t-1) from a preceding cell, and generates cell state vector c(t) and output vector h(t).
  • LSTM cell 1500 comprises sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • LSTM cell 1500 also comprises tanh devices 1504 and 1505 to apply a hyperbolic tangent function to an input vector, multiplier devices 1506, 1507, and 1508 to multiply two vectors together, and addition device 1509 to add two vectors together.
  • Output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.
  • Figure 16 depicts an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500.
  • LSTM cell 1500 For the reader’s convenience, the same numbering from LSTM cell 1500 is used in LSTM cell 1600.
  • Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each comprise multiple VMM arrays 1601 and activation function blocks 1602.
  • VMM arrays are particular useful in LSTM cells used in certain neural network systems.
  • the multiplier devices 1506, 1507, and 1508 and the addition device 1509 are Attorney Docket Number: 351913-980712 implemented in a digital manner or in an analog manner.
  • the activation function blocks 1602 can be implemented in a digital manner or in an analog manner.
  • An alternative to LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17.
  • sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM arrays 1701 and activation function block 1702) in a time-multiplexed fashion.
  • LSTM cell 1700 also comprises multiplier device 1703 to multiply two vectors together, addition device 1708 to add two vectors together, tanh device 1505 (which comprises activation function block 1702), register 1707 to store the value i(t) when i(t) is output from sigmoid function block 1702, register 1704 to store the value f(t) * c(t-1) when that value is output from multiplier device 1703 through multiplexor 1710, register 1705 to store the value i(t) * u(t) when that value is output from multiplier device 1703 through multiplexor 1710, and register 1706 to store the value o(t) * c ⁇ (t) when that value is output from multiplier device 1703 through multiplexor 1710, and multiplexor 1709.
  • LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602
  • LSTM cell 1700 contains one set of VMM arrays 1701 and activation function block 1702, which are used to represent multiple layers in the example of LSTM cell 1700.
  • LSTM cell 1700 will require less space than LSTM 1600, as LSTM cell 1700 will require 1/4 as much space for VMMs and activation function blocks compared to LSTM cell 1600.
  • LSTM units will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks.
  • Gated Recurrent Units An analog VMM implementation can be utilized for a GRU (gated recurrent unit) system.
  • GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than an LSTM cell.
  • Attorney Docket Number: 351913-980712 [0076]
  • Figure 18 depicts an example GRU 1800.
  • GRU 1800 in this example comprises cells 1801, 1802, 1803, and 1804.
  • Cell 1801 receives input vector x0 and generates output vector h0.
  • Cell 1802 receives input vector x1, the output vector h0 from cell 1801 and generates output vector h 1 .
  • Cell 1803 receives input vector x 2 and the output vector (hidden state) h 1 from cell 1802 and generates output vector h2.
  • Cell 1804 receives input vector x3 and the output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used, and an GRU with four cells is merely an example.
  • Figure 19 depicts an example implementation of a GRU cell 1900, which can be used for cells 1801, 1802, 1803, and 1804 of Figure 18.
  • GRU cell 1900 receives input vector x(t) and output vector h(t-1) from a preceding GRU cell and generates output vector h(t).
  • GRU cell 1900 comprises sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from output vector h(t-1) and input vector x(t).
  • GRU cell 1900 also comprises a tanh device 1903 to apply a hyperbolic tangent function to an input vector, a plurality of multiplier devices 1904, 1905, and 1906 to multiply two vectors together, an addition device 1907 to add two vectors together, and a complementary device 1908 to subtract an input from 1 to generate an output.
  • FIG. 20 depicts a GRU cell 2000, which is an example of an implementation of GRU cell 1900.
  • GRU cell 2000 For the reader’s convenience, the same numbering from GRU cell 1900 is used in GRU cell 2000.
  • sigmoid function devices 1901 and 1902, and tanh device 1903 each comprise multiple VMM arrays 2001 and activation function blocks 2002.
  • VMM arrays are of particular use in GRU cells used in certain neural network systems.
  • the multiplier devices 1904, 1905, 1906, the addition device 1907, and the complementary device 1908 are implemented in a digital manner or in an analog manner.
  • the activation function blocks 2002 can be implemented in a digital manner or in an analog manner.
  • GRU cell 2000 utilizes VMM arrays 2101 and activation function block 2102, which when configured as a sigmoid function applies a number between 0 and 1 to control how much of each component in the input vector is allowed through to the output vector.
  • sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM arrays 2101 and activation function block 2102) Attorney Docket Number: 351913-980712 in a time-multiplexed fashion.
  • GRU cell 2100 also comprises multiplier device 2103 to multiply two vectors together, addition device 2105 to add two vectors together, complementary device 2109 to subtract an input from 1 to generate an output, multiplexor 2104, register 2106 to hold the value h(t-1) * r(t) when that value is output from multiplier device 2103 through multiplexor 2104, register 2107 to hold the value h(t-1) *z(t) when that value is output from multiplier device 2103 through multiplexor 2104, and register 2108 to hold the value h ⁇ (t) * (1-z(t)) when that value is output from multiplier device 2103 through multiplexor 2104.
  • GRU cell 2000 contains multiple sets of VMM arrays 2001 and activation function blocks 2002
  • GRU cell 2100 contains one set of VMM arrays 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100.
  • GRU cell 2100 will require less space than GRU cell 2000, as GRU cell 2100 will require 1/3 as much space for VMMs and activation function blocks compared to GRU cell 2000.
  • GRU systems will typically comprise multiple VMM arrays, each of which uses functionality provided by certain circuit blocks outside of the VMM arrays, such as a summer and activation function block and high voltage generation blocks.
  • the input to the VMM arrays can be an analog level, a binary level, a pulse, a time modulated pulse, or digital bits (in this case a DAC is used to convert digital bits to appropriate input analog level) and the output can be an analog level, a binary level, a timing pulse, pulses, or digital bits (in this case an output ADC is used to convert output analog level into digital bits).
  • each weight W can be implemented by a single memory cell or by a differential cell or by two blend memory cells (average of 2 cells).
  • two memory cells are used to implement a weight W as an average of two cells.
  • Figure 31 depicts VMM system 3100.
  • bit lines are designated as W+ lines, Attorney Docket Number: 351913-980712 that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3101 and 3102.
  • FIG. 32 depicts another example.
  • VMM system 3210 positive weights W+ are implemented in first array 3211 and negative weights W- are implemented in a second array 3212, second array 3212 separate from the first array, and the resulting weights are appropriately combined together by summation circuits 3213.
  • Figure 33 depicts VMM system 3300.
  • VMM system 3300 comprises array 3301 and array 3302.
  • Half of the bit lines in each of array 3301 and 3302 are designated as W+ lines, that is, bit lines connecting to memory cells that will store positive weights W+, and the other half of the bit lines in each of array 3301 and 3302 are designated as W- lines, that is, bit lines connecting to memory cells implementing negative weights W-.
  • the W- lines are interspersed among the W+ lines in an alternating fashion.
  • the subtraction operation is performed by a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3303, 3304, 3305, and 3306.
  • a summation circuit that receives current from a W+ line and a W- line, such as summation circuits 3303, 3304, 3305, and 3306.
  • each W value from each array 3301 and 3302 can be further combined through summation circuits 3307 and 3308, such that each W value is the result of a W value from array 3301 minus a W value from array 3302, meaning that the end result from summation circuits 3307 and 3308 is a differential value of two differential values.
  • Each non-volatile memory cells used in the analog neural memory system is to be erased and programmed to hold a very specific and precise amount of charge, i.e., the number of Attorney Docket Number: 351913-980712 electrons, in the floating gate.
  • each floating gate can hold one of N different values, where N is the number of different weights that can be indicated by each cell.
  • N examples include 16, 32, 64, 128, and 256.
  • Prior art systems require significant area and involve significant latency at the output stage. For example, multiple clock cycles are used to convert analog current received from the VMM array into digital output data.
  • SUMMARY OF THE INVENTION Numerous examples are disclosed of an output circuit and associated methods for a neural network array. BRIEF DESCRIPTION OF THE DRAWINGS [0091]
  • Figure 1 is a diagram that illustrates an artificial neural network.
  • Figure 2 depicts a prior art split gate flash memory cell.
  • Figure 3 depicts another prior art split gate flash memory cell.
  • Figure 4 depicts another prior art split gate flash memory cell.
  • Figure 5 depicts another prior art split gate flash memory cell.
  • Figure 6 is a diagram illustrating the different levels of an artificial neural network utilizing one or more non-volatile memory arrays.
  • Figure 7 is a block diagram illustrating a VMM system.
  • Figure 8 is a block diagram illustrates an example artificial neural network utilizing one or more VMM systems.
  • Figure 9 depicts another example of a VMM system.
  • Figure 10 depicts another example of a VMM system.
  • Figure 11 depicts another example of a VMM system.
  • Figure 12 depicts another example of a VMM system.
  • Figure 13 depicts another example of a VMM system.
  • Figure 14 depicts a prior art long short-term memory system.
  • Figure 15 depicts an example cell for use in a long short-term memory system.
  • Figure 16 depicts an example implementation of the cell of Figure 15.
  • Figure 17 depicts another example implementation of the cell of Figure 15.
  • Figure 18 depicts a prior art gated recurrent unit system.
  • Figure 19 depicts an example cell for use in a gated recurrent unit system.
  • Figure 20 depicts an example implementation t of the cell of Figure 19.
  • Figure 21 depicts another example implementation of the cell of Figure 19.
  • Figure 22 depicts another example of a VMM system.
  • Figure 23 depicts another example of a VMM system.
  • Figure 24 depicts another example of a VMM system.
  • Figure 25 depicts another example of a VMM system.
  • Figure 26 depicts another example of a VMM system.
  • Figure 27 depicts another example of a VMM system.
  • Figure 28 depicts another example of a VMM system.
  • Figure 29 depicts another example of a VMM system.
  • Figure 30 depicts another example of a VMM system.
  • Figure 31 depicts another example of a VMM system.
  • Figure 32 depicts another example of a VMM system.
  • Figure 33 depicts another example of a VMM system.
  • Figure 34 depicts another example of a VMM system.
  • Figure 35 depicts an output circuit for a VMM system.
  • Figure 36A depicts a clock generator.
  • Figure 36B depicts a clock generator.
  • Figure 37 depicts an output circuit for a VMM system.
  • Figure 38A depicts an output circuit for a VMM system.
  • Figure 38B depicts another output circuit for a VMM system.
  • Figure 38C depicts another output circuit for a VMM system.
  • Figure 38D depicts another output circuit for a VMM system.
  • Figure 38E depicts another output circuit for a VMM system.
  • Attorney Docket Number: 351913-980712 [00134]
  • Figure 39A depicts a timing diagram for an output circuit.
  • Figure 39B depicts a timing diagram for another output circuit.
  • Figure 39C depicts a timing diagram for another output circuit.
  • Figure 39D depicts a timing diagram for another output circuit.
  • Figure 40 depicts an output circuit for a VMM system.
  • Figure 41 depicts a reference voltage generator.
  • Figure 42 depicts a successive approximation register analog-to-digital converter.
  • Figure 43 depicts a voltage generator.
  • Figure 44 depicts a voltage generator.
  • FIG. 34 depicts a block diagram of VMM system 3400.
  • VMM system 3400 comprises VMM array 3401, row decoder 3402, high voltage decoder 3403, column decoders 3404, bit line drivers 3405 (such as bit line control circuitry for programming), input circuit 3406, output circuit 3407, control logic 3408, and bias generator 3409.
  • VMM system 3400 further comprises high voltage generation block 3410, which comprises charge pump 3411, charge pump regulator 3412, and high voltage level generator 3413.
  • VMM system 3400 further comprises (program/erase, or weight tuning) algorithm controller 3414, analog circuitry 3415, control engine 3416 (that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), test control logic 3417, and static random access memory (SRAM) block 3418 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial sum output neuron data) or data in for programming (such as data in for a whole row or for multiple rows).
  • program/erase, or weight tuning algorithm controller 3414
  • analog circuitry 3415 that may include functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation
  • test control logic 3417 test control logic 3417
  • SRAM static random access memory
  • the input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters.
  • the input circuit 3406 may implement one or more of normalization, linear or non-linear up/down scaling functions, or arithmetic functions.
  • the input circuit 3406 may implement a temperature compensation Attorney Docket Number: 351913-980712 function for input levels.
  • the input circuit 3406 may implement an activation function such as ReLU or sigmoid.
  • Input circuit 3406 may store digital activation data to be applied as, or combined with, an input signal during a program or read operation.
  • the digital activation data can be stored in registers.
  • Input circuit 3406 may comprise circuits to drive the array terminals, such as CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers.
  • a DAC can be used to convert digital activation data into an analog input voltage to be applied to the array.
  • the output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters.
  • the output circuit 3407 may convert array outputs into activation data.
  • the output circuit 3407 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid.
  • ReLU rectified linear activation function
  • the output circuit 3407 may implement one or more of statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs.
  • the output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same over temperature.
  • the output circuit 3407 may comprise registers for storing output data.
  • Figure 35 depicts output circuit 3500.
  • Output circuit 3500 is an example implementation of output circuit 3407 in Figure 34.
  • Output circuit 3500 comprises reference circuit 3501 and column circuit 3502.
  • a plurality of instantiations of column circuit 3502 are used for a plurality of columns in VMM array 3401, i.e. a respective instantiation of column circuit 3502 for a respective column in VMM array 3401. Eight instantiations of column circuit 3502 are shown in Figure 35, but it is to be understood that there could be many more instantiations and associated columns in a VMM system.
  • Reference circuit 3501 receives a reference current, such as a bitline current, from one or more reference columns of non-volatile memory cells.
  • the reference column can be part Attorney Docket Number: 351913-980712 of VMM array 3401, as shown, or can be located in a separate array.
  • Reference circuit 3501 comprises column multiplexor 3503, current-to-voltage converter 3504, and reference generator 3505. If more than one reference column is connected to reference circuit 3501, then column multiplexor 3503 selects a column and provides the current from that column to current-to- voltage converter 3504, which converts the received current into a voltage.
  • Reference generator 3505 generates voltage references VADCREFs (such as VADCREFH and VADCREFL) used by analog to digital converters (ADCs) 3508, where the voltage references VADCREFs are based on the voltage outputs from current-to-voltage converter 3504.
  • VADCREFs such as VADCREFH and VADCREFL
  • VREFP 0.3V
  • VREFN 0V
  • VCIM 0.15V for a full- scale input voltage of 0.3V for the ADC.
  • the reference voltages for the ADCs 3508 are generated from the voltage output of current-to-voltage converter 3504, which is similar to current-to-voltage converter 3507, resolution of ADCs 3508 is maintained because the reference voltages for the ADCs automatically track any changes due to changes in operating conditions (such as changes in temperature) of current-to-voltage converter 3504 and current-to-voltage converter 3507.
  • Each column circuit 3502 receives current, such as a bitline current, from one or more columns in VMM array 3401.
  • Each column circuit 3502 comprises column multiplexor 3506, current-to-voltage converter 3507, and ADC 3508. If more than one column is connected to column circuit 3502, then column multiplexor 3506 selects a column and provides the current from that column to current-to-voltage converter 3507, which will convert the received current into a voltage, which ADC 3508 converts into a digital output. For example, column circuit 3502 outputs DOUT0x [n:0]. If a single column is connected to column circuit 3502, column multiplexor 3506 is optional.
  • Figures 36A and 36B depict clock generators that are used to generate fast clock signals, meaning clock signals with a faster frequency than the system clock received from a source external to the VMM system, for the circuits described herein.
  • Figure 36A depicts clock generator 3600, which receives a system clock, CLKIN (for example, the system clock received from a source external to the VMM system), an enable signal, EN, and configuration bits, CFGx, and generates a faster clock, CLKOUT, with a Attorney Docket Number: 351913-980712 different clock frequency depending on the configuration bits, CFGx, using a delay-lock loop (DLL) 3601 and clock generator block 3602.
  • CLKIN system clock received from a source external to the VMM system
  • EN enable signal
  • CFGx configuration bits
  • Figure 36B depicts clock generator 3650, which receives a system clock, CLKIN, and generates a faster clock, CLKOUT, using a phase-locked loop (PLL) 3651 and clock generator block 3602.
  • DLL 3601 and PLL 3651 are used to generate precise clocks, respectively faster than system clock CLKIN, that synchronize with input clock CLKIN, for example, clocks that are 2-100 times faster than the input system clock CLKIN.
  • Clock generator blocks 3602 and 3652 are used to generate different clock frequencies in response to configuration bits CFGx using CLK_INT.
  • Figure 37 depicts output circuit 3700, which can be used for an instantiation of column circuit 3502 in Figure 35.
  • Output circuit 3700 is a differential circuit, meaning the circuit output is a function of two inputs.
  • Output circuit 3700 comprises current-to-voltage converter (ITV) 3704 (a first current-to-voltage converter), ITV 3705 (a second current-to- voltage converter), differential input serial approximation register analog-to-digital converter (SAR ADC) 3701, transistors 3713, 3715, 3724, and 3726 (which form a portion of a column multiplexor, which couples a column in a first set of columns to ITV 3704 and couples a column in the second set of columns to ITV 3705), and current sources 3702 and 3703.
  • ITV current-to-voltage converter
  • ITV 3705 a second current-to- voltage converter
  • SAR ADC differential input serial approximation register analog-to-digital converter
  • transistors 3713, 3715, 3724, and 3726 which form a portion of a column multiplexor, which couples a column in a first set of columns to I
  • Current source 3702 represents current drawn by a column in VMM array 3401 that is selected by the column multiplexor, where the column stores W+ values.
  • Current source 3703 represents current drawn by a column in VMM array 3401 that is selected by the column multiplexor, where the column stores W- values.
  • output circuit 3700 can be implemented as a single ended circuit, meaning that one ITV (3704 or 3705) and a single input ADC is used.
  • ITV 3704 comprises switches 3706, 3707, and 3708; integration capacitors 3710 and 3711; NMOS cascoding transistor 3712; and operational amplifier 3714. Prior to a read Attorney Docket Number: 351913-980712 operation, switches 3706, 3707, and 3708 are closed, resulting in the top and bottom plates of integration capacitors 3710 and 3711 being charged to Vsup and VIN+ equal to Vsup.
  • switch 3706 is opened.
  • Current source 3702 draws current, resulting in the voltage of VIN+ (a first voltage) being pulled downward in proportion to the current drawn by current source 3702. That is, VIN+ will equal the initial value of VIN+ before the read operation minus a first discharge value due to the first current, IW+.
  • VIN+ will equal the initial value of VIN+ before the read operation minus a first discharge value due to the first current, IW+.
  • the voltages across the capacitors 3710 and 3711 are sampled into the SAR ADC 3701. After this sampling period, the ADC will start to do conversion of this sampled voltages into digital output bits.
  • capacitor 3711 is a capacitor in the binary capacitor array of the SAR ADC 3701 (that is, ITV 3704 and SAR ADC 3701 share a capacitor to save die space).
  • switches 3707 and 3708 are opened, and SAR ADC 3701 starts the conversion of voltages on capacitor 3711 into digital output bits.
  • ITV 3705 comprises switches 3717, 3718, and 3719; capacitors 3721 and 3722; NMOS cascoding transistor 3723; and operational amplifier 3725.
  • switches 3717, 3718, and 3719 Prior to a read operation, switches 3717, 3718, and 3719 are closed, resulting in the top and bottom plates of integration capacitors 3721 and 3722 being charged to Vsup and VIN- equal to Vsup.
  • switch 3717 is opened.
  • Current source 3703 will draw current, resulting in the voltage of VIN- (a second voltage) being pulled downward in proportion to the current drawn by current source 3703. That is, VIN- will equal the initial value of VIN- before the read operation minus a first discharge value due to the first current, IW-.
  • Capacitors 3721 and 3722 are similar to capacitors 3710 and 3711 in the ITV 3704.
  • Switches 3718 and 3719 are similar to switches 3707 and 3708 in ITV 3704.
  • Bitline regulation circuit for the ITV 3704 includes the operational amplifier 3714, transistor 3712, and transistors 3713 and 3715 which are both turned on when a read operation is desired for the bit line IW+.
  • This circuit imposes a fixed bias on a bitline during a read operation. Specifically, it imposes VREF, which is applied to the positive input terminal of Attorney Docket Number: 351913-980712 operational amplifier 3714, on the bit line during a read operation irrespective of the magnitude of the current drawn by bit line IW+.
  • bitline regulation circuit for the ITV 3705 includes the operational amplifier 3725, transistor 3723, and force and sense transistors 3724 and 3726 which are both turned on when a read operation is desired for the bit line IW-.
  • This circuit imposes VREF, which is applied to the positive input terminal of operational amplifier 3725, on the bit line during a read operation irrespective of the magnitude of the current drawn by bit line IW+
  • SAR ADC 3701 receives differential voltages VIN+ and VIN- and reference voltages VADCREFH and VADCREFL and generates a digital output, DOUT[n:0], based on the difference between VIN+ and VIN-.
  • FIG. 38A depicts output circuit 3800, which can be used for two instantiations of column circuit 3502 in Figure 35.
  • Output circuit 3800 comprises circuit 3801, circuit 3802, and shared capacitor network 3813.
  • Circuits 3801 and 3802 each are identical to output circuit 3700 in Figure 37 except that integration capacitors 3710 and 3721 in output circuit 3700 have been replaced by shared integration capacitors 3803 (a first integration capacitor) and 3804 (a second integration capacitor), respectively, in shared capacitor network 3813; and switches 3805, 3807, 3809, and 3811 used in shared capacitor network 3813 for circuit 3801; and switches 3806, 3808, 3810, and 3812 are used in shared capacitor network 3813 for circuit 3802.
  • Circuit 3801 comprises ITV 3823 (a first current to voltage converter) coupled to IW1+ (a first current) and ITV 3824 (a second current to voltage converter) coupled to IW1- (a second current).
  • Output circuit 3850 has the same design as output circuit 3800 but with 8 ITVs instead of 4 ITVs and 4 SAR ADCs instead of 2 SAR ADCs, using shared capacitor network 3870 that comprises shared capacitors 3871 and 3872 and a series of switches to selectively coupled shared capacitors 3871 and 3872 to ITVs 3851, 3852, 3853, 3854, 3855, 3856, 3857, and 3858.
  • ITV 3851 is coupled to bit line current IW1+ (a first current)
  • ITV 3852 is coupled to bit line current IW1- (a second current)
  • ITV 3853 is coupled to bit line current IW2+ (a third current)
  • ITV 3854 is coupled to bit line current IW2- (a fourth current)
  • ITV 3855 is coupled to bit line current IW3+ (a fifth current)
  • ITV 3856 is coupled to bit line current IW3- (a sixth current)
  • ITV 3857 is coupled to bit line IW4+ (a seventh current)
  • ITV 3858 is coupled to bit line current IW4- (an eighth current).
  • ITVs 3851 and 3852 are coupled to SAR ADC 3861
  • ITVs 3853 and 3854 are coupled to SAR ADC 3862
  • ITVs 3855 and 3856 are coupled to SAR ADC 3863
  • ITVs 3857 and 3858 are coupled to SAR ADC 3864
  • SAR ADC 3861 comprises binary capacitor array (CDAC) 3865
  • SAR ADC 3862 comprises CDAC 3866
  • SAR ADC 3863 comprises CDAC 3867
  • SAR ADC 3864 comprises CDAC 3868.
  • the design of the CDACs is described in greater detail below with reference to Figure 42. [00163]
  • Figure 38C depicts output circuit 3880, which can be used for four instantiations of column circuit 3502 in Figure 35.
  • Output circuit 3880 is identical to output circuit 3850 in Attorney Docket Number: 351913-980712 Figure 38B except that it uses two SAR ADCs (SAR ADCs 3883 and 3884 containing CDACs 3885 and 3886, respectively) instead of four SAR ADCs, which is achieved by the addition of multiplexor 3881, which allows signals from ITVs 3851 and 3852 to be time-multiplexed with signals from ITVs 3853 and 3854 to share SAR ADC 3883, and the addition of multiplexor 3882, which allows signals from ITVs 3855 and 3856 to be time-multiplexed with signals from ITVs 3857 and 3858 to share SAR ADC 3884.
  • SAR ADCs 3883 and 3884 containing CDACs 3885 and 3886, respectively
  • FIG 38D depicts output circuit 3890, which is identical to output circuit 3800 in Figure 38A except that each ITV can be selectively coupled to one of two different bit lines by switches or a multiplexor (not shown).
  • ITV 3823 can be coupled to IW1+ (a first current) or W3+ (a fifth current)
  • ITV 3824 can be coupled to IW1- (a second current) or W3- (a sixth current)
  • ITV 3825 can be coupled to W2+ (a third current) or W4+ (a seventh current)
  • ITV 3826 can be coupled to W2- (a fourth current) or W4- (an eighth current).
  • Figure 38E depicts output circuit 3895, which is similar to output circuit 3890 except the two CDACs 3829 and 3830 are used within a single SAR ADC 3896.
  • Figure 39A depicts timing diagram 3900 for operating output circuit 3850, which contains eight ITVs and four SAR ADCs. There are two main periods. [00167] The first period is the integration or sampling period (comprising sub-periods t1, t2, t3, and t4) where bitline current is integrated by the capacitors.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3851 and 3852 and bitlines IW1+ and IW1- are sampled and held in CDAC 3865.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3853 and 3854 and bitlines IW2+ and IW2- are sampled and held in CDAC 3866.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3855 and 3856 and bitlines IW3+ and IW3- are sampled and held in CDAC 3867.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3851 and 3852 and bitlines IW1+ and IW1- are sampled and held in CDAC 3885.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3853 and 3854 and bitlines IW2+ and IW2- are sampled and held in CDAC 3886.
  • SAR ADC 3883 performs a conversion operation on the value stored in CDAC 3885 during sub-period t1.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3855 and 3856 and bitlines IW3+ and IW3- are sampled and held in CDAC 3885.
  • SAR ADC 3884 performs a conversion operation on the value stored in CDAC 3886 during sub-period t2.
  • shared capacitors 3871 and 3872 are coupled to ITVs 3857 and 3858 and bitlines IW4+ and IW4- are sampled and held in CDAC 3886.
  • SAR ADC 3883 performs a conversion operation on the value stored in CDAC 3885 during sub-period t3.
  • SAR ADC 3884 performs a conversion operation on the value stored in CDAC 3886 during sub-period t4.
  • Figure 39C depicts timing diagram 3940 for operating output circuit 3800 in Figure 38A, which contains four ITVs and two SAR ADCs, where sampling-and-holding occurs on one CDAC while conversion is performed on the other CDAC.
  • shared capacitors 3803 and 3804 are coupled to ITVs 3823 and 3824 and bitlines IW1+ and IW1- are sampled and held in CDAC 3829.
  • shared capacitors 3803 and 3804 are coupled to ITVs 3825 and 3826 and bitlines IW2+ and IW2- are sampled and held in CDAC 3830.
  • SAR ADC 3827 performs a conversion operation on the value stored in CDAC 3829 during sub-period t1.
  • shared capacitors 3803 and 3804 are coupled to ITVs 3827 and 3828 and bitlines IW3+ and IW3- are sampled and held in CDAC 3829.
  • SAR ADC 3828 performs a conversion operation on the value stored in CDAC 3830 during sub-period t2.
  • FIG. 39D depicts timing diagram 3950 for operating output circuit 3890 in Figure 38D, which contains four ITVs selectively coupled to 8 different bit lines and two SAR ADCs.
  • Timing diagram 3950 utilizes a bitline current overlapping technique to reduce settling time. For example, after the output conversion for bitlines IW1+ and IW1-, bitlines IW2+ and IW2- are enabled while bitlines IW1+ and IW1- are still enabled before disabling bitlines IW+ and IW- and starting the conversion process for the bitlines IW2+ and IW2-. This ensures efficiecnt current loading into the ITVs between read operations across multiple bitlines. This is useful for situations where an ITV is shared by multiple bit lines.
  • bitlines IW1+ and IW1- are enabled, shared capacitors 3803 and 3804 are coupled to ITVs 3823 and 3824, bitlines IW1+ and IW1- are sampled and held in CDAC 3829, and SAR ADC 3827 performs a conversion operation on the value stored in CDAC 3829. After the conversion operation, IW2+ and IW2- are enabled while IW1+ and IW1- are still enabled.
  • bitlines IW2+ and IW2- are enabled, shared capacitors 3803 and 3804 are coupled to ITVs 3825 and 3826, bitlines IW2+ and IW2- are sampled and held in CDAC 3830, and SAR ADC 3828 performs a conversion operation on the value stored in CDAC 3830. After the conversion operation, IW3+ and IW3- are enabled while IW2+ and IW2- are still enabled.
  • bitlines IW3+ and IW3- are enabled, shared capacitors 3803 and 3804 are coupled to ITVs 3823 and 3824, bitlines IW3+ and IW3- are sampled and held in CDAC 3829, and SAR ADC 3827 performs a conversion operation on the value stored in CDAC 3829. After the conversion operation, IW4+ and IW4- are enabled while IW3+ and IW3- are still enabled.
  • bitlines IW4+ and IW4- are enabled, shared capacitors 3803 and 3804 are coupled to ITVs 3825 and 3826, bitlines IW4+ and IW4- are sampled and held in Attorney Docket Number: 351913-980712 CDAC 3830, and SAR ADC 3828 performs a conversion operation on the value stored in CDAC 3829.
  • current steering techniques are used in which there is efficient current loading (e.g., from a fixed supply) for the ITV circuits during switching between output operations (current to voltage conversion) for the ITV such as across multiple bit-lines.
  • FIG. 40 depicts output circuit 4000, which can be used for i instantiations of column circuit 3502 of Figure 35.
  • Output circuit 4000 comprises SAR ADC 3701 (or any type of ADC architecture), ITV 3704 for column W+, and ITV 3705 for column W- as in output circuit 3700 described previously for Figure 37.
  • output circuit 4000 can selectively connected to one of i different W+ current sources (current sources 4002-1, ..., 4002-i) by portions 4001-1, ..., 4001-i of a column multiplexor and to one of i different W- current sources (current sources 4004-1, ..., 4004-i) by portions 4003-1, ..., 4003-i of a column multiplexor.
  • One pair of columns are connected to ITV 3704 for column W+, and ITV 3705 for column W- at any given time and all other columns are disconnected from ITV 3704 and ITV 3705 using the multiplexor.
  • FIG. 41 depicts reference voltage generator 4100 to generate VADCREFL and VADCREFH, which are used to generate voltages VREFP, VCIM, and VREFN that are reference voltages used by SAR ADC 3701 as shown in previous figures.
  • Reference voltage generator 4100 is a current-to-voltage converter similar to that shown in Figure 37 and converts a reference current, IBLREF, into voltages VADCREFH and VADCREFL.
  • Reference voltage generator 4100 comprises switches 4101, 4102, 4103, 4104, and 4120; capacitors 4105 and 4106; transistor 4107; operational amplifier 4110; transistors 4108 and 4109; and reference current source 4111.
  • switches 4120, 4101, 4102, 4103, and 4104 are closed, resulting in the top and bottom plates of capacitors 4105 and 4106 being charged to VDDA.
  • switch 4120 is opened.
  • Reference current source 4111 draws a reference current IBLREF, resulting in VADCREFL being pulled downward in proportion to the current drawn by reference current source 4111.
  • FIG. 42 depicts SAR ADC 4200 that is an example of an SAR ADC that can be used for SAR ADC 3701 in Figure 37; SAR ADCs 3827 and 3828 in Figure 38A; SAR ADCs 3861, 3862, 3863, and 3864 in Figure 38B; SAR ADCs 3883 and 3884 in Figure 38C; SAR ADCs 3827 and 3828 in Figure 38D; and SAR ADC 3701 in Figure 40.
  • SAR ADC 4200 comprises CDAC 4201 (which is an example of CDACs 3829, 3830, 3865, 3866, 3867, 3868, 3885, 3886, 3829, and 3830 in Figures 37, 38A, 38B, 38C, 38D, and 40), comparator 4202, SAR logic 4203, switch 4204, and switch 4205.
  • CDAC 4201 optionally, when not performing an operation in SAR ADC 3701, can be used as capacitors 3803 and 3804 in Figure 38A, capacitors 3871 and 3872 in Figures 38B and 38C, and capacitors 3803 and 3804 in Figure 38D.
  • SAR ADC 4200 operates by first sampling the input voltages VIN+ and VIN- into the capacitor array (CDAC) 4201P and 4201N, respectively.
  • SAR logic 4203 will successively convert the voltages into digital bits, starting with the most significant bit and ending with the least significant bit. For example, for an 8-bit ADC, B7 will be converted first and B0 will be converted last. Hence, there are 8 conversion clocks for an 8-bit ADC. For each conversion, the VIN+ will be compared against VIN-, and the comparison decision is used to switch the capacitors associated with the bit for the next bit comparison.
  • FIG 43 depicts voltage generator 4300 that can be used to generate VREFP, VREFN, and VCM that are used by SAR ADC 4200 in Figure 42.
  • Voltage generator 4300 comprises switches 4301, 4302, 4303, and 4304; capacitors 4305 and 4306; switch 4307; variable capacitor 4308; and comparator 4309.
  • the capacitance of capacitor 4305 the capacitance of capacitor 4306.
  • VOUT (VIN2 - VIN1) * (capacitance of capacitor 4305) / (capacitance of capacitor 4306) by switching the switches 4301 to 4304 appropriately.
  • FIG. 44 depicts voltage generator 4400 that can be used to generate VREFP, VREFN, and VCM that are used by SAR ADC 4200 in Figure 42.
  • Voltage generator 4400 comprises clamp 4401 and resistor ladder 4402.
  • Resistor ladder 4402 comprises n+1 resistors coupled in series.
  • Each node will have a different voltage, ranging from VREF at the top node of resistor ladder 4402 to ground at the bottom node of resistor ladder 4402.
  • Appropriate nodes are selected to provide voltages VREFP, VREFN, and VCM for SAR ADC 4200.
  • the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween).
  • adjacent includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between)
  • mounted to includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between)
  • electrically coupled includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
  • forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

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Abstract

Dans un exemple, un système comprend un réseau de multiplication vecteur-matrice comprenant des cellules de mémoire non volatile disposées en lignes et en colonnes, un premier ensemble de colonnes stockant W+ poids et un deuxième ensemble de colonnes stockant W- poids ; et un circuit de sortie destiné à recevoir un premier courant provenant d'une colonne respective dans le premier ensemble de colonnes et un deuxième courant provenant d'une colonne respective dans le deuxième ensemble de colonnes et à générer une première tension et une deuxième tension, le circuit de sortie comprenant un premier convertisseur courant-tension comprenant un premier condensateur d'intégration pour fournir la première tension égale à une tension initiale moins une première valeur de décharge due au premier courant, et un deuxième convertisseur courant-tension comprenant un deuxième condensateur d'intégration pour fournir la deuxième tension égale à la tension initiale moins une deuxième valeur de décharge due au deuxième courant.
PCT/US2023/081167 2023-08-25 2023-11-27 Circuit de sortie pour un réseau de multiplication vecteur-matrice Pending WO2025048866A1 (fr)

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