WO2024138819A1 - Memristor-based charge-type in-memory computation implementation method and unit structure therefor - Google Patents
Memristor-based charge-type in-memory computation implementation method and unit structure therefor Download PDFInfo
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- Deep neural networks have been widely used in artificial intelligence fields such as computer vision and natural language processing.
- traditional hardware platforms have to transfer a large amount of data between computing units and storage units due to the separation of the computing units and storage units, which leads to huge computing delays and power consumption.
- the in-memory computing architecture based on memristors can integrate computing units and storage units, and use the non-volatile characteristics of memristors to effectively reduce data handling during computing, thereby improving the computing energy efficiency and computing power of the system.
- the purpose of the present invention is to propose an efficient charge-type in-memory computing implementation method based on memristors, which converts the resistance state of the memristor into charge and completes the in-memory computing by means of capacitive coupling, so as to effectively alleviate the device fluctuation problem, greatly reduce the current during calculation and improve the calculation parallelism, thereby improving the computing energy efficiency and computing power of the neural network system.
- This structure can be used to implement basic multiplication and addition operations.
- the following is a detailed description of the basic multiplication and addition operations in the neural network as an example.
- the WL in the unit structure is used as the neural network input Input
- the memristor resistance is used as the neural network weight Weight
- the voltage value of the top plate of the capacitor is used as the neural network output Output.
- Table 1 lists the truth tables of input, weight and output values in four cases, where V mid and VH represent voltage values, RH represents memristor high resistance, and RL represents memristor low resistance.
- the unit reset stage completes the reset operation of the unit structure by closing the switch connected to CL. After the CL input voltage VH resets the capacitor in the unit structure to a high potential, the switch is disconnected. At the same time, BL and SL input 0V, so that the gate potential of the second NMOS transistor is 0V, that is, the second NMOS transistor is in the off state and will not leak the charge in the capacitor.
- the gate of the second NMOS transistor will be at a high voltage (High voltage) due to the resistance voltage division of the memristor and the first NMOS transistor, so that the second NMOS transistor is turned on, and the top plate of the capacitor will be set to 0V, that is, the output is 0; in the coupling summation phase, WL and BL both input 0V, so that the gate potential of the second NMOS transistor is 0V, and the second NMOS transistor is in the off state. After the switch is closed, the unit will be capacitively coupled with other units to achieve cumulative summation operations.
- the inputs of all unit structures are set to 0, all switches are closed, the capacitors on the same column will be coupled, and the potential of the mth column after coupling is Vout m ; the coupling result is output to the digital circuit through the ADC circuit, and is processed by the digital circuit outside the array to obtain OUT m .
- weights W 1,1 ⁇ W 128,128 need to be written into the array.
- W n,n is 0, the memristor writes low resistance RL , and when W n,n is 1, the memristor writes high resistance RH (n represents any integer from 1 to 128). After successful writing, calculation can begin.
- the first NMOS transistor is in a closed state during calculation; one end of the memristor R1 is connected to the high bit line BLP, and the other end is connected to the memristor R2; one end of the memristor R2 is connected to the low bit line BLN, and the other end is connected to the memristor R1; the gate of the second NMOS transistor (T2) on the right is connected to the midpoint where the memristors R1 and R2 are connected, the source is connected to the ground, the drain is connected to the top plate of the capacitor, and the bottom plate of the capacitor is grounded; the calculation line CL is connected to the top plate of the capacitor through a switch.
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Abstract
Description
本发明属于新型计算技术领域，具体涉及一种基于忆阻器的电荷型存内计算实现方法及单元结构。The present invention belongs to the field of novel computing technology, and in particular relates to a method and a unit structure for realizing charge-type in-memory computing based on a memristor.
深度神经网络已经广泛地应用在计算机视觉和自然语言处理等人工智能领域。传统硬件平台在处理深度神经网络时，由于计算单元与存储单元的分离，使得大量的数据在两者之间传输，这导致了巨大的计算延迟和功耗开销。基于忆阻器的存内计算架构可以将计算单元和存储单元融合起来，并利用忆阻器的非易失特性，有效减少计算时的数据搬运，进而提高系统的计算能效和算力。Deep neural networks have been widely used in artificial intelligence fields such as computer vision and natural language processing. When processing deep neural networks, traditional hardware platforms have to transfer a large amount of data between computing units and storage units due to the separation of the computing units and storage units, which leads to huge computing delays and power consumption. The in-memory computing architecture based on memristors can integrate computing units and storage units, and use the non-volatile characteristics of memristors to effectively reduce data handling during computing, thereby improving the computing energy efficiency and computing power of the system.
近年来，基于忆阻器的存内计算技术得到了广泛关注。主要利用基尔霍夫电流定律在源线（SL）上实现电流的累加，最后通过模数转换电路输出到下一级。这类方法可以在阵列内实现大规模矩阵向量乘操作，但是仍然存在一些问题：器件涨落问题会使得读出电流产生严重交叠，影响最终计算结果；阵列在工作时，会产生较大的静态电流，这将给阵列及其外围电路带来巨大的能量开销；提高阵列的并行度会继续增大静态电流，所以这类方法会限制阵列的并行度，最终使得阵列的计算算力受限。因此，目前在基于忆阻器的存内计算领域，还没有有效的方法可以减小阵列工作时的静态电流，以提升阵列的计算能效和算力。In recent years, memristor-based in-memory computing technology has received widespread attention. It mainly uses Kirchhoff's current law to realize the accumulation of current on the source line (SL), and finally outputs it to the next level through the analog-to-digital conversion circuit. This type of method can realize large-scale matrix-vector multiplication operations in the array, but there are still some problems: the device fluctuation problem will cause serious overlap of the readout current, affecting the final calculation result; when the array is working, it will generate a large static current, which will bring huge energy overhead to the array and its peripheral circuits; increasing the parallelism of the array will continue to increase the static current, so this type of method will limit the parallelism of the array, and ultimately limit the computing power of the array. Therefore, in the field of memristor-based in-memory computing, there is currently no effective method to reduce the static current of the array when it is working, so as to improve the computing energy efficiency and computing power of the array.
为了克服上述现有忆阻器存内计算技术的不足，本发明的目的是提出一种高效的基于忆阻器的电荷型存内计算实现方法，通过将忆阻器阻态转换成电荷，利用电容耦合的方式完成存内计算，以有效缓解器件涨落问题，极大减小计算时的电流并提高计算并行度，从而提高神经网络系统的计算能效和算力。In order to overcome the shortcomings of the above-mentioned existing memristor in-memory computing technology, the purpose of the present invention is to propose an efficient charge-type in-memory computing implementation method based on memristors, which converts the resistance state of the memristor into charge and completes the in-memory computing by means of capacitive coupling, so as to effectively alleviate the device fluctuation problem, greatly reduce the current during calculation and improve the calculation parallelism, thereby improving the computing energy efficiency and computing power of the neural network system.
本发明的方法分为两部分：（1）通过一类单元结构将忆阻器阻态转换成电荷（该类单元结构不限定于某一种形式，可以包含多个忆阻器、晶体管和电容等）存储在电容中；（2）不同单元结构转换后的电荷通过电容耦合的方式实现计算功能。为了详细说明两部分内容，下面描述的具体单元结构和实现方案仅用以解释本发明基本原理，并不用于限定本发明。The method of the present invention is divided into two parts: (1) converting the resistance state of a memristor into electric charge through a type of unit structure (this type of unit structure is not limited to a certain form and can include multiple memristors, transistors and capacitors, etc.) and storing it in a capacitor; (2) the charges converted by different unit structures are coupled with capacitors to realize the computing function. In order to explain the two parts in detail, the specific unit structure and implementation scheme described below are only used to explain the basic principles of the present invention and are not used to limit the present invention.
本发明将忆阻器阻态转换成电荷的单元结构可以由一个或多个忆阻器、一个或多个晶体管和一个电容组成，例如：图1中所示的由两个NMOS晶体管、一个忆阻器和一个电容组成的2T1R1C单元结构，图7中所示的两个NMOS晶体管、两个忆阻器和1个电容组成的2T2R1C单元结构，图8中所示的三个NMOS晶体管、两个忆阻器和一个电容组成的3T2R1C单元结构。The unit structure of the present invention for converting the resistance state of a memristor into an electric charge can be composed of one or more memristors, one or more transistors and a capacitor, for example: the 2T1R1C unit structure composed of two NMOS transistors, a memristor and a capacitor shown in FIG1 , the 2T2R1C unit structure composed of two NMOS transistors, two memristors and a capacitor shown in FIG7 , and the 3T2R1C unit structure composed of three NMOS transistors, two memristors and a capacitor shown in FIG8 .
下面以如图1所示的2T1R1C单元结构为例来说明本发明存内计算的实现方式。该单元结构由两个NMOS晶体管、一个忆阻器和一个电容组成，其中，第一NMOS晶体管（即图1中的T1）与忆阻器（R）串联，忆阻器的顶电极连接到位线BL，底电极连接到与其串联的NMOS晶体管的漏极，该NMOS晶体管的栅极连接到字线WL，源极连接到源线SL；忆阻器与第一NMOS晶体管相连的中点处连接到第二NMOS晶体管（即图1中的T2）的栅极；第二NMOS晶体管的源极连接到地，漏极连接到电容的顶极板，电容的底极板接地；计算线CL会通过一个开关连接到电容的顶极板。The implementation of the in-memory calculation of the present invention is described below by taking the 2T1R1C unit structure shown in FIG1 as an example. The unit structure is composed of two NMOS transistors, a memristor and a capacitor, wherein the first NMOS transistor (i.e., T1 in FIG1 ) is connected in series with the memristor (R), the top electrode of the memristor is connected to the bit line BL, the bottom electrode is connected to the drain of the NMOS transistor connected in series with it, the gate of the NMOS transistor is connected to the word line WL, and the source is connected to the source line SL; the midpoint where the memristor is connected to the first NMOS transistor is connected to the gate of the second NMOS transistor (i.e., T2 in FIG1 ); the source of the second NMOS transistor is connected to the ground, the drain is connected to the top plate of the capacitor, and the bottom plate of the capacitor is grounded; the calculation line CL is connected to the top plate of the capacitor through a switch.
利用该结构可以实现基本乘加操作。以下以神经网络中的基本乘加操作为例进行详细说明，该单元结构中的WL作为神经网络输入Input，忆阻器阻值作为神经网络权重Weight，电容顶极板的电压值作为神经网络输出Output，该结构可以完成神经网络中的基本乘操作（Output=Input×Weight），累加操作通过并行的多个单元结构间的电容耦合完成（Output sum=Output 1+…+ Output n，n代表大于1的整数）。表1列出了4种情况下的输入、权重和输出值的真值表，其中V mid和VH表示电压值，R H表示忆阻器高阻，R L表示忆阻器低阻。 This structure can be used to implement basic multiplication and addition operations. The following is a detailed description of the basic multiplication and addition operations in the neural network as an example. The WL in the unit structure is used as the neural network input Input, the memristor resistance is used as the neural network weight Weight, and the voltage value of the top plate of the capacitor is used as the neural network output Output. This structure can complete the basic multiplication operation in the neural network (Output = Input × Weight), and the accumulation operation is completed through the capacitive coupling between multiple parallel unit structures (Output sum = Output 1 +…+ Output n , n represents an integer greater than 1). Table 1 lists the truth tables of input, weight and output values in four cases, where V mid and VH represent voltage values, RH represents memristor high resistance, and RL represents memristor low resistance.
表1
Table 1
该单元结构的基本工作原理如图2所示，共分为三个阶段，分别为 单元复位阶段、单元计算阶段和耦合求和阶段。 The basic working principle of the unit structure is shown in FIG2 , which is divided into three stages, namely, the unit reset stage, the unit calculation stage and the coupling summation stage .
单元复位阶段完成单元结构的复位操作，通过闭合与CL连接的开关，CL输入电压VH将单元结构中的电容重置到高电位后，将开关断开；同时BL与SL输入0V，使得第二NMOS晶体管的栅极电位为0V，即第二NMOS 晶体管处于关闭状态，不会将电容内的电荷泄露掉。 The unit reset stage completes the reset operation of the unit structure by closing the switch connected to CL. After the CL input voltage VH resets the capacitor in the unit structure to a high potential, the switch is disconnected. At the same time, BL and SL input 0V, so that the gate potential of the second NMOS transistor is 0V, that is, the second NMOS transistor is in the off state and will not leak the charge in the capacitor.
单元计算阶段完成单元结构的乘法操作，神经网络输入Input中的0和1分别对应WL输入电压0V和V mid，其中V mid会使得第一NMOS晶体管处于半打开状态，使其电阻R T1处于忆阻器高阻和低阻之间，即R L<R T1<R H。神经网络权重0和1分别对应忆阻器阻值R L和R H。BL输入V read，SL输入0V，当输入和权重不同时，第二NMOS晶体管的栅极上形成的电阻分压将不同。当电阻分压为高电压（High voltage）时，会打开第二NMOS晶体管，从而将电容中的电荷清空，使得电容顶极板的电位为0V，即单元结构输出Output为0；当电阻分压为低电压（Low voltage）时，第二NMOS晶体管依然处于关闭状态不变，电容顶极板的电压值仍为VH，即单元结构输出Output为1。 The unit calculation stage completes the multiplication operation of the unit structure. The 0 and 1 in the neural network input Input correspond to the WL input voltage 0V and V mid respectively, where V mid will make the first NMOS transistor in a semi-open state, so that its resistance RT1 is between the high resistance and low resistance of the memristor, that is, RL < RT1 < RH . The neural network weights 0 and 1 correspond to the memristor resistances RL and RH respectively. BL inputs Vread and SL inputs 0V. When the input and weight are different, the resistance voltage division formed on the gate of the second NMOS transistor will be different. When the resistance voltage division is a high voltage (High voltage), the second NMOS transistor will be turned on, thereby clearing the charge in the capacitor, so that the potential of the top plate of the capacitor is 0V, that is, the output Output of the unit structure is 0; when the resistance voltage division is a low voltage (Low voltage), the second NMOS transistor remains in the closed state unchanged, and the voltage value of the top plate of the capacitor is still VH, that is, the output Output of the unit structure is 1.
耦合求和阶段完成多单元结构的输出结果求和操作。与单元复位阶段电位一致，BL和SL输入0V，保持第二NMOS晶体管的栅极电位为0V，即处于关闭状态。同时闭合与CL的开关，如图3所示，通过电容耦合的方式实现多个2T1R1C单元的计算结果的求和操作，最后CL的电位V out即为最终的乘加结果Output sum。 The coupled summation stage completes the summation operation of the output results of the multi-unit structure. Consistent with the potential in the unit reset stage, BL and SL input 0V, keeping the gate potential of the second NMOS transistor at 0V, that is, in the off state. At the same time, the switch with CL is closed, as shown in Figure 3, and the summation operation of the calculation results of multiple 2T1R1C units is realized by capacitive coupling. Finally, the potential V out of CL is the final multiplication and addition result Output sum .
图4为4种不同输入和权重情况下的单元工作原理图，分别为输入1权重1输出1、输入1权重0输出0、输入0权重1输出0和输入0权重0输出0。Figure 4 is a diagram of the unit working principle under four different input and weight conditions, namely input 1 weight 1 output 1, input 1 weight 0 output 0, input 0 weight 1 output 0 and input 0 weight 0 output 0.
输入为1（V mid）和权重为1（R H）时，单元复位阶段会将电容顶极板重置到VH，重置后断开开关；单元计算阶段中，当BL输入V read时，由于WL输入为V mid，使得第一NMOS晶体管的电阻R T1<R H。第二NMOS晶体管的栅极会因为忆阻器与第一NMOS晶体管的电阻分压而处于低电压（Low voltage），使得第二NMOS晶体管关闭，电容顶极板仍然为VH，即输出为1；耦合求和阶段中，WL和BL都输入0V，使得第二NMOS晶体管的栅极电位为0V，第二NMOS晶体管处于关闭状态，闭合开关后，该单元会与其他单元进行电容耦合，实现累加求和操作。 When the input is 1 (V mid ) and the weight is 1 (R H ), the top plate of the capacitor will be reset to VH in the unit reset phase, and the switch will be disconnected after the reset; in the unit calculation phase, when BL inputs V read , since the WL input is V mid , the resistance of the first NMOS transistor RT1 <R H . The gate of the second NMOS transistor will be at a low voltage (Low voltage) due to the resistance voltage division of the memristor and the first NMOS transistor, so that the second NMOS transistor is turned off, and the top plate of the capacitor is still VH, that is, the output is 1; in the coupling summation phase, WL and BL both input 0V, so that the gate potential of the second NMOS transistor is 0V, and the second NMOS transistor is in the off state. After the switch is closed, the unit will be capacitively coupled with other units to achieve cumulative summation operations.
输入为1（V mid）和权重为0（R L）时，单元复位阶段会将电容顶极板重置到VH，重置后断开开关；单元计算阶段中，当BL输入V read时，由于WL输入为V mid，使得第一NMOS晶体管的电阻R T1>R L。第二NMOS晶体管的栅极会因为忆阻器与第一NMOS晶体管的电阻分压而处于高电压（High voltage），使得第二NMOS晶体管打开，电容顶极板会置为0V，即输出为0；耦合求和阶段中，WL和BL都输入0V，使得第二NMOS晶体管的栅极电位为0V，第二NMOS晶体管处于关闭状态，闭合开关后，该单元会与其他单元进行电容耦合，实现累加求和操作。 When the input is 1 (V mid ) and the weight is 0 (R L ), the top plate of the capacitor will be reset to VH in the unit reset phase, and the switch will be disconnected after the reset; in the unit calculation phase, when BL inputs V read , since the WL input is V mid , the resistance of the first NMOS transistor R T1 >R L . The gate of the second NMOS transistor will be at a high voltage (High voltage) due to the resistance voltage division of the memristor and the first NMOS transistor, so that the second NMOS transistor is turned on, and the top plate of the capacitor will be set to 0V, that is, the output is 0; in the coupling summation phase, WL and BL both input 0V, so that the gate potential of the second NMOS transistor is 0V, and the second NMOS transistor is in the off state. After the switch is closed, the unit will be capacitively coupled with other units to achieve cumulative summation operations.
输入为0（0）和权重为1（R H）时，单元复位阶段会将电容顶极板重置到VH，重置后断开开关；单元计算阶段中，当BL输入V read时，由于WL输入为0，第一NMOS晶体管处于关闭状态，使得其电阻R T1>>R H。第二NMOS晶体管的栅极会因为忆阻器与第一NMOS晶体管的电阻分压而处于高电压（High voltage），使得第二NMOS晶体管打开，电容顶极板会置为0V，即输出为0；耦合求和阶段中，WL和BL都输入0V，使得第二NMOS晶体管的栅极电位为0V，第二NMOS晶体管处于关闭状态，闭合开关后，该单元会与其他单元进行电容耦合，实现累加求和操作。 When the input is 0 (0) and the weight is 1 (R H ), the top plate of the capacitor will be reset to VH in the unit reset phase, and the switch will be disconnected after the reset; in the unit calculation phase, when BL inputs V read , since the WL input is 0, the first NMOS transistor is in the off state, making its resistance R T1 >>R H . The gate of the second NMOS transistor will be at a high voltage (High voltage) due to the resistance voltage division of the memristor and the first NMOS transistor, making the second NMOS transistor open, and the top plate of the capacitor will be set to 0V, that is, the output is 0; in the coupling summation phase, WL and BL both input 0V, making the gate potential of the second NMOS transistor 0V, and the second NMOS transistor is in the off state. After closing the switch, the unit will be capacitively coupled with other units to achieve cumulative summation operations.
输入为0（0）和权重为0（R L）时，单元复位阶段会将电容顶极板重置到VH，重置后断开开关；单元计算阶段中，当BL输入V read时，由于WL输入为0，第一NMOS晶体管处于关闭状态，使得其电阻R T1>>R L。第二NMOS晶体管的栅极会因为忆阻器与第一NMOS晶体管的电阻分压而处于高电压（High voltage），使得第二NMOS晶体管打开，电容顶极板会置为0V，即输出为0；耦合求和阶段中，WL和BL都输入0V，使得第二NMOS晶体管的栅极电位为0V，第二NMOS晶体管处于关闭状态，闭合开关后，该单元会与其他单元进行电容耦合，实现累加求和操作。 When the input is 0 (0) and the weight is 0 (R L ), the top plate of the capacitor will be reset to VH in the unit reset phase, and the switch will be disconnected after the reset; in the unit calculation phase, when BL inputs V read , since the WL input is 0, the first NMOS transistor is in the off state, making its resistance R T1 >>R L . The gate of the second NMOS transistor will be at a high voltage (High voltage) due to the resistance voltage division of the memristor and the first NMOS transistor, making the second NMOS transistor open, and the top plate of the capacitor will be set to 0V, that is, the output is 0; in the coupling summation phase, WL and BL both input 0V, making the gate potential of the second NMOS transistor 0V, and the second NMOS transistor is in the off state. After closing the switch, the unit will be capacitively coupled with other units to achieve cumulative summation operations.
图5以3个2T1R1C基本单元为例，说明了多单元并行模式下的电荷型计算的基本原理。在单元复位阶段，所有电容会重置到VH；单元计算阶段时，第1和3单元的计算结果为0，因此将电容内电荷释放掉即置为0V，第2个单元的计算结果为1，电容顶极板电位不变即仍为VH；在耦合求和阶段，3个单元的电容会通过CL进行耦合，最终电位会稳定在1/3VH，即最终乘累加结果为1（3个单元乘累加结果：0对应0，1/3VH对应1，2/3VH对应2，VH对应3）。Figure 5 takes three 2T1R1C basic units as an example to illustrate the basic principle of charge-type calculation in multi-unit parallel mode. In the unit reset stage, all capacitors will be reset to VH; in the unit calculation stage, the calculation results of the 1st and 3rd units are 0, so the charge in the capacitor is released and set to 0V, and the calculation result of the second unit is 1, and the potential of the top plate of the capacitor remains unchanged, that is, it is still VH; in the coupling and summation stage, the capacitors of the three units will be coupled through CL, and the final potential will be stabilized at 1/3VH, that is, the final multiplication and accumulation result is 1 (3 unit multiplication and accumulation results: 0 corresponds to 0, 1/3VH corresponds to 1, 2/3VH corresponds to 2, and VH corresponds to 3).
利用所述单元结构组成的n×m阵列实现公式1所示的向量矩阵乘计算：
公式1
其中，n、m分别代表每一列和每一行上的单元结构个数。
The n×m array composed of the unit structure is used to implement the vector matrix multiplication calculation shown in Formula 1:
Formula 1
Among them, n and m represent the number of unit structures in each column and each row respectively.
下面以图1所示的单元结构为例来说明向量矩阵乘计算的实现方式。参见图6，位于每一列上的n个单元结构通过开关并联到同一根计算线CL，位于每一行的m个单元结构并联到同一根字线WL。在阵列计算前，将权重W
1,1~W
n,m写入到阵列中，W
n,m为0时忆阻器写入低阻R
L，W
n,m为1时忆阻器写入高阻R
H；写入成功后开始计算：
在单元复位阶段所有单元结构的输入置0，所有开关闭合，电容进行复位操作置为VH电位，阵列中的每一根计算线都会连接阵列外的模数转换电路（ADC），每一根计算线都会对应一个ADC，此时ADC处于关闭状态；
在单元计算阶段所有开关断开，电容中的电荷根据输入IN
n的不同进行保持和释放，每一行共享同一个输入，当计算完成后结果将全部存储在电容之中，ADC仍然处于关闭状态；
在耦合求和阶段所有单元结构的输入置0，所有开关闭合，同一列上的电容会进行耦合，第m列耦合后的电位为Vout
m；耦合结果通过ADC电路输出给数字电路，经过阵列外数字电路处理得到OUT
m。
The implementation of vector-matrix multiplication calculation is described below using the cell structure shown in FIG1 as an example. Referring to FIG6 , the n cell structures located in each column are connected in parallel to the same calculation line CL through switches, and the m cell structures located in each row are connected in parallel to the same word line WL. Before array calculation, the weights W 1,1 to W n,m are written into the array. When W n,m is 0, the memristor is written with low resistance RL , and when W n,m is 1, the memristor is written with high resistance RH ; after successful writing, calculation begins:
In the unit reset phase, the inputs of all unit structures are set to 0, all switches are closed, and the capacitors are reset to VH potential. Each calculation line in the array is connected to an analog-to-digital conversion circuit (ADC) outside the array. Each calculation line corresponds to an ADC, and the ADC is in a closed state at this time.
In the unit calculation phase, all switches are turned off, and the charge in the capacitor is held and released according to the different inputs IN n . Each row shares the same input. When the calculation is completed, the results are all stored in the capacitor, and the ADC is still in the off state.
In the coupling summation stage, the inputs of all unit structures are set to 0, all switches are closed, the capacitors on the same column will be coupled, and the potential of the mth column after coupling is Vout m ; the coupling result is output to the digital circuit through the ADC circuit, and is processed by the digital circuit outside the array to obtain OUT m .
除了上面描述的2T1R1C单元结构，还可以采用图7中所示的2T2R1C单元结构和图8中所示3T2R1C单元结构来实现上述计算功能。In addition to the 2T1R1C unit structure described above, the 2T2R1C unit structure shown in FIG. 7 and the 3T2R1C unit structure shown in FIG. 8 may also be used to implement the above-mentioned computing function.
区别于传统将忆阻器阻态转换成电流，再利用基尔霍夫电流定律进行计算的方法，本发明通过将忆阻器阻态转换成电荷，利用电容耦合的方式完成存内计算，该方法可以有效缓解器件涨落问题，极大减小计算时的电流并提高计算并行度。Different from the traditional method of converting the resistance state of a memristor into current and then using Kirchhoff's current law for calculation, the present invention converts the resistance state of a memristor into charge and uses capacitive coupling to complete in-memory calculations. This method can effectively alleviate the device fluctuation problem, greatly reduce the current during calculation and improve the parallelism of calculations.
图1为本发明实施例一所述的2T1R1C基本单元结构图，该类结构将忆阻器阻态转换为电荷。FIG. 1 is a structural diagram of a 2T1R1C basic unit according to a first embodiment of the present invention. This type of structure converts the resistance state of a memristor into electric charge.
图2为本发明2T1R1C基本单元结构工作原理图。FIG. 2 is a diagram showing the working principle of the 2T1R1C basic unit structure of the present invention.
图3为本发明采用2T1R1C基本单元结构在多单元并行模式下的耦合求和阶段工作原理图。FIG3 is a working principle diagram of the coupling summation stage in the multi-unit parallel mode using a 2T1R1C basic unit structure of the present invention.
图4为本发明的2T1R1C基本单元结构在所有4种情况下的工作原理图。FIG. 4 is a diagram showing the working principle of the 2T1R1C basic unit structure of the present invention in all four cases.
图5为本发明在多单元并行模式下的电荷型计算原理图（以3个2T1R1C单元为例）。FIG5 is a schematic diagram of the charge-type calculation principle of the present invention in a multi-unit parallel mode (taking three 2T1R1C units as an example).
图6为本发明实施例一中128×128计算单元完成向量矩阵乘的实施方案，包括（a）单元复位阶段、（b）单元计算阶段和（c）耦合求和阶段。FIG6 is an implementation scheme of the 128×128 computing units completing vector-matrix multiplication in the first embodiment of the present invention, including (a) a unit reset phase, (b) a unit calculation phase, and (c) a coupled summation phase.
图7为本发明实施例二所述2T2R1C基本单元结构图及其工作原理图，包括（a）单元复位阶段、（b）单元计算阶段和（c）耦合求和阶段。FIG. 7 is a structural diagram of a 2T2R1C basic unit and a working principle diagram according to a second embodiment of the present invention, including (a) a unit reset phase, (b) a unit calculation phase, and (c) a coupling summation phase.
图8为本发明实施例三所述3T2R1C基本单元结构图及其工作原理图，包括（a）单元复位阶段、（b）单元计算阶段和（c）耦合求和阶段。FIG8 is a structural diagram of a 3T2R1C basic unit and a working principle diagram according to a third embodiment of the present invention, including (a) a unit reset phase, (b) a unit calculation phase, and (c) a coupling summation phase.
为了更加清楚地阐明本发明的目的、技术方案与优点，下面结合附图，通过具体实施例进一步详细地说明本发明。此处描述的具体实施例仅用以解释本发明，并不用于限定本发明。In order to more clearly illustrate the purpose, technical solutions and advantages of the present invention, the present invention is further described in detail by specific embodiments in conjunction with the accompanying drawings. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
以公式1的向量矩阵乘为例，利用128×128个如图1所示的2T1R1C计算单元实现该计算，其中输入IN 1~IN 128和权重W 1,1~W 128,128均为1 bit，输出OUT 1~OUT 128为7 bit。因为7 bit可以表示128个数，输入IN 1~IN 128和权重W 1,1~W 128,128进行乘加，输出范围是0~128，所以每一个OUT值可以近似用7bit表示。 Taking the vector-matrix multiplication of Formula 1 as an example, the calculation is implemented using 128×128 2T1R1C computing units as shown in Figure 1, where the input IN 1 ~IN 128 and the weight W 1,1 ~W 128,128 are all 1 bit, and the output OUT 1 ~OUT 128 is 7 bits. Because 7 bits can represent 128 numbers, the input IN 1 ~IN 128 and the weight W 1,1 ~W 128,128 are multiplied and added, and the output range is 0~128, so each OUT value can be approximately represented by 7 bits.
在阵列计算前，需要将权重W 1,1~W 128,128写入到阵列中，W n,n为0时忆阻器写入低阻R L，W n,n为1时忆阻器写入高阻R H（n代表1~128的任一整数），写入成功后即可开始计算。 Before array calculation, weights W 1,1 ~W 128,128 need to be written into the array. When W n,n is 0, the memristor writes low resistance RL , and when W n,n is 1, the memristor writes high resistance RH (n represents any integer from 1 to 128). After successful writing, calculation can begin.
如图6中（a）所示，在单元复位阶段所有单元结构的输入置0，所有开关闭合，电容进行复位操作置为VH电位，此时模数转换电路（ADC）处于关闭状态。As shown in FIG. 6 (a), in the unit reset phase, the inputs of all unit structures are set to 0, all switches are closed, and the capacitors are reset to the VH potential. At this time, the analog-to-digital conversion circuit (ADC) is in the off state.
如图6中（b）所示，在单元计算阶段所有开关断开，电容中的电荷会根据输入IN n的不同进行保持和释放，每一行共享同一个输入，当计算完成后结果将全部存储在电容之中，ADC仍然处于关闭状态。 As shown in (b) of Figure 6, during the unit calculation phase, all switches are disconnected, and the charge in the capacitor is retained and released according to the different input IN n . Each row shares the same input. When the calculation is completed, the result will be stored in the capacitor, and the ADC is still in the off state.
如图6中（c）所示，在耦合求和阶段所有单元结构的输入置0，所有开关闭合，同一列上的电容会进行耦合，第n列耦合后的电位为Vout n。耦合结果会通过ADC电路输出给数字电路，经过阵列外数字电路处理得到OUT n。 As shown in (c) of Figure 6, in the coupling summation stage, the inputs of all unit structures are set to 0, all switches are closed, the capacitors on the same column are coupled, and the potential of the nth column after coupling is Vout n . The coupling result is output to the digital circuit through the ADC circuit, and is processed by the digital circuit outside the array to obtain OUT n .
实施例二
如图7所示2T2R1C单元结构为例，该单元结构由两个NMOS晶体管、两个忆阻器和一个电容组成：其中位于左侧的第一NMOS晶体管（T1）的源极连接到源线SL，漏极连接忆阻器R1和R2相连的中点处，栅极连接字线WL，仅用于对忆阻器R1和R2进行编程，计算时第一NMOS晶体管处于关闭状态；忆阻器R1一端连接高位线BLP，另一端连接忆阻器R2；忆阻器R2一端连接低位线BLN，另一端连接忆阻器R1；位于右侧的第二NMOS晶体管（T2）的栅极连接忆阻器R1和R2相连的中点处，源极连接到地，漏极连接到电容的顶极板，电容的底极板接地；计算线CL会通过一个开关连接到电容的顶极板。
Embodiment 2 Taking the 2T2R1C unit structure shown in FIG. 7 as an example, the unit structure is composed of two NMOS transistors, two memristors and a capacitor: the source of the first NMOS transistor (T1) on the left is connected to the source line SL, the drain is connected to the midpoint where the memristors R1 and R2 are connected, and the gate is connected to the word line WL, which is only used to program the memristors R1 and R2. The first NMOS transistor is in a closed state during calculation; one end of the memristor R1 is connected to the high bit line BLP, and the other end is connected to the memristor R2; one end of the memristor R2 is connected to the low bit line BLN, and the other end is connected to the memristor R1; the gate of the second NMOS transistor (T2) on the right is connected to the midpoint where the memristors R1 and R2 are connected, the source is connected to the ground, the drain is connected to the top plate of the capacitor, and the bottom plate of the capacitor is grounded; the calculation line CL is connected to the top plate of the capacitor through a switch.
计算时WL为0，第一NMOS晶体管处于关闭状态，BLP通入高电压Vread，BLN通入低电压如0V，该方案通过R1与R2的电阻分压，最终使得第二NMOS晶体管对电容中的电荷进行保持和清空，实现将忆阻器阻态转换成电荷。During calculation, WL is 0, the first NMOS transistor is in the off state, a high voltage Vread is passed to BLP, and a low voltage such as 0V is passed to BLN. This scheme uses the resistance voltage divider of R1 and R2 to ultimately enable the second NMOS transistor to maintain and clear the charge in the capacitor, thereby converting the resistance state of the memristor into charge.
实施例三
如图8所示3T2R1C单元结构为例，该单元结构由三个NMOS晶体管和两个忆阻器组成：其中忆阻器R1和R2串联，它们上下端分别连接第一和第二NMOS晶体管（T1和T2）的漏极；第一和第二晶体管的栅极分别连接高字线WLP和低字线WLN，源极分别连接高位线BLP和低位线BLN，这两个NMOS晶体管均用于对忆阻器R1和R2进行编程，在计算时两个NMOS晶体管完全打开；位于右侧的第三NMOS晶体管（T3）的栅极连接忆阻器R1和R2相连的中点处，源极连接到地，漏极连接到电容的顶极板，电容的底极板接地；计算线CL会通过一个开关连接到电容的顶极板。
Embodiment 3 Taking the 3T2R1C unit structure shown in FIG8 as an example, the unit structure is composed of three NMOS transistors and two memristors: wherein the memristors R1 and R2 are connected in series, and their upper and lower ends are connected to the drains of the first and second NMOS transistors (T1 and T2) respectively; the gates of the first and second transistors are connected to the high word line WLP and the low word line WLN respectively, and the sources are connected to the high bit line BLP and the low bit line BLN respectively, and the two NMOS transistors are used to program the memristors R1 and R2, and the two NMOS transistors are fully turned on during calculation; the gate of the third NMOS transistor (T3) located on the right is connected to the midpoint where the memristors R1 and R2 are connected, the source is connected to the ground, the drain is connected to the top plate of the capacitor, and the bottom plate of the capacitor is grounded; the calculation line CL is connected to the top plate of the capacitor through a switch.
计算时WLP和WLN输入高电压，将第一和第二NMOS晶体管全部打开，BLP通入高电压Vread，BLN通入低电压如0V，该方案通过R1与R2的电阻分压，最终使得第三NMOS晶体管对电容中的电荷进行保持和清空，实现将忆阻器阻态转换成电荷。During calculation, WLP and WLN input high voltage, turn on the first and second NMOS transistors, pass high voltage Vread to BLP, and pass low voltage such as 0V to BLN. This scheme uses the resistance voltage divider of R1 and R2 to eventually enable the third NMOS transistor to maintain and clear the charge in the capacitor, thereby converting the resistance state of the memristor into charge.
以上实施例仅用以说明本发明的技术方案而非对其进行限制，本领域的普通技术人员可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明的精神和范围，本发明的保护范围应以权利要求所述为准。The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. A person skilled in the art may modify or make equivalent substitutions for the technical solutions of the present invention without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to the claims.
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| CN113342126B (en) * | 2021-07-29 | 2021-11-26 | 中科南京智能技术研究院 | Reconfigurable current mirror weighting circuit based on ReRAM |
| CN114627930B (en) * | 2022-03-21 | 2025-06-10 | 中科南京智能技术研究院 | Single-bit differential SRAM (static random Access memory) storage integrated array and device |
| CN114863964A (en) * | 2022-04-27 | 2022-08-05 | 中国科学院微电子研究所 | In-memory computing circuit, memory and equipment based on local multiply-integral addition structure |
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| CN115273937B (en) * | 2022-06-21 | 2025-10-10 | 昕原半导体(上海)有限公司 | High-speed, low-precision loss MAC array based on resistive random access memory and operation method thereof |
| CN115376581B (en) * | 2022-07-11 | 2023-05-16 | 中国科学院微电子研究所 | Memristor-based in-memory computing array structure |
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2022
- 2022-12-30 CN CN202211713269.5A patent/CN115691613B/en active Active
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- 2023-01-29 WO PCT/CN2023/073681 patent/WO2024138819A1/en not_active Ceased
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| US20170221558A1 (en) * | 2015-04-28 | 2017-08-03 | Hewlett Packard Enterprise Development Lp | Memristor apparatus with variable transmission delay |
| US20180166134A1 (en) * | 2015-06-17 | 2018-06-14 | King Abdullah University Of Science And Technology | Compensated readout of a memristor array, a memristor array readout circuit, and method of fabrication thereof |
| US10804324B1 (en) * | 2019-07-25 | 2020-10-13 | Tetramem Inc. | 1T2R RRAM cell and common reactive electrode in crossbar array circuits |
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| CN114742217A (en) * | 2022-04-22 | 2022-07-12 | 安徽大学 | A memristor-based circuit for VFL-RELU spiking neurons |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115691613A (en) | 2023-02-03 |
| CN115691613B (en) | 2023-04-28 |
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