WO2020068121A1

WO2020068121A1 - Charge metering circuit for memristor

Info

Publication number: WO2020068121A1
Application number: PCT/US2018/053461
Authority: WO
Inventors: Brent Buchanan; Le ZHENG; John Paul Strachan
Original assignee: Hewlett Packard Enterprise Development LP
Current assignee: Hewlett Packard Enterprise Development LP
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2020-04-02
Anticipated expiration: 2021-03-28

Abstract

A charge metering circuit for a memristor includes a switch connected between a stimulus voltage and the memristor. The switch is pulsed on to apply the stimulus voltage to the memristor. The circuit includes a current mirror connected between a low-rail voltage and the memristor and having a primary leg and a secondary leg, and a capacitor connected between a capacitor voltage and the secondary leg. The primary leg pulls a voltage at the memristor to a virtual ground voltage upon pulsing on of the switch, and the secondary leg pulls a current through the capacitor from the capacitor voltage.

Description

CHARGE METERING CIRCUIT FOR MEMRISTOR

BACKGROUND

[0001] A memristor is a passive two-terminal electrical component. When current flows in one direction through the device, electrical resistance increases, whereas when current flows in the opposite direction, resistance decreases. When current is stopped, the component retains the last resistance that it had, and when the flow of charge begins again, the resistance of the circuit will be what it was when it was last active. A digital memristor has a number of discrete states, such as two, whereas an analog memristor has continuous states.

Memristors can be used for main system memory, more generalized storage, as well as for a variety of other more specialized purposes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 is a diagram of an example charge metering circuit for a memristor by which the total charge through the memristor while a stimulus is applied can be measured.

[0003] FIG. 2 is a diagram of an example charge metering circuit that includes the charge metering circuit of FIG. 1 and that can terminate a stimulus applied to a memristor once the total charge through the memristor has reached a threshold.

[0004] FIG. 3 is a diagram of an example charge metering circuit that includes the charge metering circuit of FIG. 1 , which can also terminate a stimulus applied to a memristor when the memristor’s total charge has reached a threshold, and which limits the amount of current through the memristor.

[0005] FIG. 4 is a flowchart of an example method for measuring the total charge through a memristor while a stimulus is applied, and which can be performed in relation to the example circuits of FIGs. 1 , 2, and 3.

[0006] FIG. 5 is a flowchart of an example method for terminating a stimulus applied to a memristor when the total charge through the memristor has reached a threshold, and which can be performed in relation to the example circuits of FIGs. 2 and 3. DETAILED DESCRIPTION

[0007] As noted in the background section, a memristor is an electrical component that can retain its resistance value, and thus its present state, even when current is removed from the device. Therefore, a memristor is a type of non-volatile memory. A memristor has an operational regime with an

approximately linear charge-resistance relationship, so long as the time-integral of the current stays within certain bounds.

[0008] However, knowledge as to how a memristor definitively operates to provide its functionality is not as well developed as knowledge regarding the operation of other devices, such as dynamic random-access memory (DRAM) cells and semiconductor transistors. Therefore, fundamental research regarding memristors is still ongoing. Any new information regarding the operating characteristics of memristors can assist in this endeavor. [0009] A digital memristor has two states corresponding to low resistance and high resistance, which can correlate to the memristor storing logic one and logic zero values, respectively. The polarity of a memristor is said to be set when the memristor transitions from the high resistance state to the low resistance state, and is said to be reset when the memristor transitions from the low resistance state to the high resistance state. A stimulus voltage is applied to a memristor both to read the memristor’s present state and write a new state to the memristor. A write stimulus voltage may be greater than a read stimulus voltage in this respect, or the same stimulus voltage may be applied in both cases, where the stimulus voltage is maintained longer to write to rather than read

the memristor.

[0010] During writes, excess energy provided to a memristor beyond that which is needed to switch a memristor’s current state can damage the device, resulting in poor endurance, poor retention of its current state, as well as other issues. For instance, the on/off ratio - the resistance at which the memristor is in a high resistance state as compared to the resistance at which it is in a low resistance state - may suffer. During reads, if too much energy is provided to a memristor, the memristor may switch states; i.e. , a write may be erroneously performed.

[0011] In some types of computational circuits that employ memristors, fine control of a memristor’s conductance state can be desirable. For example, the conductance states of the memristors may correspond to the weight values within a multiply-accumulate (MAC)/dot product (DP) computation. In this respect, affecting the conductance state using charge packets can be more beneficial than affecting this state using fixed-width voltage pulses.

[0012] Described herein are example charge metering circuits. Such example charge metering circuits can be employed to measure the total charge through a memristor as a stimulus voltage is applied to the memristor. As such, new information regarding the operating characteristics of memristors can be gleaned, assisting in more fully understanding how memristors operate.

[0013] The example charge metering circuits can be employed to terminate the write stimulus voltage being applied to a memristor once the total charge through the memristor has reached a desired amount. Therefore, issues related to providing excess electrical energy to the memristor can be reduced or avoided. Similarly, during reads, the total charge applied to the memristor can be limited to an amount below the amount at which the memristor may switch states.

[0014] FIG. 1 shows an example charge metering circuit 100 for a memristor 106, which may be part of the circuit 100. The circuit 100 measures the total charge through the memristor 106 while a stimulus voltage 104 is being applied to the memristor 106. The stimulus voltage 104 may be a write stimulus voltage to cause the memristor 106 to switch states, or a read stimulus voltage to read the current state of the memristor 106.

[0015] The charge metering circuit 100 includes a switch 102 connected between the stimulus voltage 104 and the memristor 106. The switch 102 may be a p-type transistor, as depicted in FIG. 1 , with its source connected to the stimulus voltage 104 and its drain connected to the top electrode of memristor 106. The switch 102 is pulsed on to apply the stimulus voltage 104 to the memristor 106. In the case where the switch 102 is a p-type transistor, the switch 102 is pulsed on by pulsing the gate of the p-type transistor low.

[0016] The charge metering circuit 100 includes a current mirror 108 connected between the memristor 106 and a low-rail voltage 110. The current mirror 108 includes a primary leg 112 and a secondary leg 114. The current through the secondary leg 114 mirrors the current through the primary leg 112. The primary leg 112 and the secondary leg 114 can be implemented as n-type transistors 124 and 126, respectively, connected as shown in FIG. 1. As such, the gate of the n-type transistor 124 is connected to the drain of the transistor 124, which is connected to the memristor 106. The source of each of the n-type transistors 124 and 126 are connected to the low-rail voltage 110, and the gates of the transistors 124 and 126 are connected to one another, as well as to the drain of the transistor 124.

[0017] The charge metering circuit 100 includes a capacitor 116 connected between a capacitor voltage 118 and the secondary leg 114 of the current mirror 108. In the case where the n-type transistor 126 implements the secondary leg 114, current is drawn through the capacitor 116 resulting in a charge deposited on the capacitor 116. The charge metering circuit 100 can include a switch 120 connected in parallel with the capacitor 116 between the capacitor voltage 118 and the secondary leg 114. The switch 120 is turned on to discharge the capacitor 116 and then turned off prior to the switch 102 being pulsed on. The switch 120 may be implemented as a transistor or in another manner.

[0018] The voltage 104 is the stimulus voltage insofar as the voltage 104 stimulates the memristor 106 to read from or write to the memristor 106. The low-rail voltage 110 is lower than each of the capacitor voltage 118 and the stimulus voltage 104. The low-rail voltage 110 is the source voltage for the n- type transistors 124 and 126, insofar as the voltage 110 is connected to the source of each transistor 124 and 126. The capacitor voltage 118 may be equal to, lower than, or greater than the stimulus voltage 104.

[0019] The charge metering circuit 100 includes an output 122 at a junction of the capacitor 116 and the secondary leg 114 of the current mirror 108. The voltage over the capacitor 116 is proportional to the total charge through the memristor 106 upon application of the stimulus voltage via pulsing on of the switch 102. The voltage over the capacitor 116 is equal to the difference between the capacitor voltage and the voltage at the output 122. As such, the charge metering circuit 100 can measure the total charge through the memristor 106 upon application of the stimulus voltage to the memristor 106, by measuring the voltage at the output 122.

[0020] In operation, the switch 120 is closed and then opened, resulting in a zero voltage over the capacitor 116, and a voltage equal to the voltage 118 appearing at the output 122. The switch 102 is then pulsed on to apply the stimulus voltage 104 to the memristor 106. With current subsequently flowing through the n-type transistor 124, the drain of the transistor 124 settles at about the threshold voltage of the transistor 124. Changes in current flowing through the memristor 106 and thus through the n-type transistor 124 have just a small effect on this voltage, such that the drain of the transistor 124 is effectively at a virtual ground.

[0021] The current flowing through the memristor 106 and the n-type transistor 124 is mirrored from the primary leg 112 of the current mirror 108 (implemented by the transistor 124) to the secondary leg 114 of the current mirror 108 (implemented by the n-type transistor 126). The secondary leg 114 pulls this current through the capacitor 116 from the capacitor voltage 118. That is, the current through the capacitor 116 is equal to the current through the secondary leg 114. Therefore, the current through the capacitor 116 is equal to the current through the memristor 106, since the secondary leg 114 mirrors the current through the primary leg 112, which itself is equal to the current through the memristor 106.

[0022] Pulling the current through the capacitor 116 charges the capacitor, which increases the voltage over the capacitor 116 and hence lowers the voltage at the output 122. The total charge through the memristor 106 is equal to the capacitance of the capacitor 116 multiplied by the difference between the capacitor voltage 118 and the voltage at the output 122. Therefore, charge metering circuit 100 can indirectly measure the total charge through the memristor 106 as the stimulus voltage 104 is being applied to the memristor 106 via direct measurement of the voltage at the output 122. That is, at any time during or after application of the stimulus voltage 104, the total charge through the memristor 106 can be determined.

[0023] In the example of FIG. 1 , the p-type transistor 102 operates in a digital mode, in which the transistor 102 is on or it is off. The switch 120, if implemented as a transistor, similarly operates in a digital mode. By comparison, the n-type transistors 124 and 126 operate in an analog mode.

[0024] The example of FIG. 1 , in the case of a write stimulus voltage, pertains to the case in which the polarity of the memristor 106 is being set. That is, the memristor 106 is transitioned from a high resistance state corresponding to logic zero to a low resistance state corresponding to logic one. Monitoring the total charge through the memristor 106 in this scenario can be useful since there can be a potential for the total charge to exceed a threshold at which the memristor 106 can become damaged, acutely or over time.

[0025] Monitoring the total charge through the memristor 106 in the reset polarity case, in which the memristor 106 is transitioned from the low resistance state to the high resistance state, can be similarly achieved. For instance, the charge metering circuit 100 may be implemented in mirror fashion, at the other end of the memristor 106. In this case, the stimulus voltage 104 and the switch 102 are tied to the bottom electrode of the memristor 106, and the current mirror 108, the capacitor 116, the capacitor voltage 118, the switch 120, and the output

122 are tied to the top electrode of the memristor 106.

[0026] FIG. 2 shows another example charge metering circuit 200 for the memristor 106, which may be part of the circuit 200. The circuit 200 includes the same components as the charge metering circuit 100, and therefore measures the total charge through the memristor 106 while the stimulus voltage 104 is being applied to the memristor 106, in the same way in which the circuit 100 does so. The circuit 200 also terminates the stimulus voltage 104 from the memristor 106 to protect the memristor 106 from conducting a total charge greater than a threshold charge.

[0027] In addition to the components of the charge metering circuit 100, the charge metering circuit 200 includes a switch 202 that controls operation of the switch 102. The switch 202, like the switch 102, can be implemented as a p- type transistor. The p-type transistor of the switch 202 has a source connected to a high-rail voltage 204, which may be equal to the stimulus voltage 104. The p-type transistor of the switch 202 has a drain connected to the gate of the p-type transistor of the switch 102.

[0028] The charge metering circuit 200 includes a switch 206, which can be implemented as an n-type transistor. The n-type transistor has a source connected to the low-rail voltage 110, and a drain connected to the gate of the p- type transistor of the switch 102, and thus to the drain of the p-type transistor of the switch 202. The transistor of the switch 206 has a gate that is pulsed (high) to pulse on the switch 102 to apply the stimulus voltage 104 to the memristor 106. More generally, the switch 206 is pulsed to pulse on the switch 102 to apply the stimulus voltage 104 to the memristor 106.

[0029] The charge metering circuit 200 includes a comparator 208. The comparator 208 has a negative input 210 connected to a reference voltage 212, and a positive input 214 connected to the output 122. The comparator 208 has an output 216 that is connected to the gate of the p-type transistor of the switch 202. The reference voltage 212 is set to the voltage at the output 122 that corresponds to the total charge through the memristor 106 being equal to the threshold charge at which the stimulus voltage 104 is to be terminated (i.e. , removed) from the memristor 106. Therefore, when the voltage at the input 214 drops to equal the reference voltage 212 at the input 210, the stimulus voltage 104 is terminated at the memristor 106.

[0030] In operation, the switch 120 is closed and then opened, resulting in a zero voltage over the capacitor 116. The gate of the n-type transistor of the switch 206 is pulsed high, which pulls the gate of the p-type transistor of the switch 102 low. Parasitic capacitance at the interconnection among the switches 102, 202, and 206 holds the p-type transistor of the switch 102 on after the switch 206 turns off when pulsing is complete.

[0031] The current flowing through the memristor 106 and the n-type transistor 124 is mirrored from the primary leg 112 of the current mirror 108 to the secondary leg 114 of the current mirror 108. The secondary leg 114 pulls this current through the capacitor 116 from the initial capacitor voltage 118. Pulling the current through the capacitor 116 charges the capacitor 116, increasing the voltage over the capacitor 116 and hence lowering the voltage at the output 122. The total charge through the memristor 106 can be indirectly measured by measuring the voltage at the output 122 as in FIG. 1. [0032] The capacitor 116 continues to accumulate charge, such that the voltage over the capacitor 116 increases and the voltage at the output 122 continues to decrease, until the voltage at the output 122 equals the reference voltage 212. Until this occurs, the output 216 of the comparator 208 is high because the voltage at the input 214 (i.e. , equal to the voltage at the output 122) is greater than the reference voltage 212 at the input 210. Because the switch 202 is a p-type transistor, the switch 202 remains off because the gate of this transistor is connected to the output 216 of the comparator 208.

[0033] When the voltage at the output 122 drops to the reference voltage 212, however, the output 216 of the comparator 208 drops low, because the voltage at the input 214 is now lower than the reference voltage 212 at the input 210. Because the switch 202 is a p-type transistor, the output 216 of the comparator 208 turns on the switch 202, which correspondingly turns off the switch 102, which is also implemented as a p-type transistor. The switch 102 turning off terminates the stimulus voltage at the memristor 106, preventing the memristor 106 from having a total charge exceeding a threshold charge corresponding to the voltage at the output 122 equaling the reference

voltage 212.

[0034] The example of FIG. 2, in the case of a write stimulus, pertains to the case in which the polarity of the memristor 106 is being set. Terminating the write stimulus in the reset polarity case can be similarly achieved, by

implementing the charge metering circuit 200 in mirror fashion at the other end of the memristor 106, in a manner as described above in relation to the charge metering circuit 100 of FIG. 1.

[0035] FIG. 3 shows a third example charge metering circuit 300 for the memristor 106, which may be part of the circuit 300. The circuit 300 is similar to the charge metering circuit 200. Therefore in addition to measuring the total charge through the memristor 106 while the stimulus voltage 106 is applied to the memristor 106, the charge metering circuit 300 terminates the stimulus voltage 104 from the memristor 106 to protect the memristor 106 from conducting a total charge greater than a threshold charge. The circuit 300 further maintains current compliance in that the circuit 300 limits the current through the memristor 106 so that the current cannot exceed a threshold.

[0036] The charge metering circuit 300 includes the components of the charge metering circuit 200 except that the circuit 300 does not include the switch 206. Rather, the circuit 300 includes a switch 302, a constant current source 304, and a p-type transistor 306. The switch 302, which may be implemented as a transistor, controls operation of the switch 102, and is pulsed to pulse on the switch 102 to apply the stimulus voltage to the memristor 106.

The constant current source is connected between the low-rail voltage 110 and the drain of transistor 306, and in conjunction with other components of the charge metering circuit 300 limits the current through the memristor 106 when the switch 102 is pulsed on.

[0037] The p-type transistor 306 implements a primary leg 308 and the p- type transistor of the switch 102 a secondary leg 310 of a current mirror 312 between the voltage 104 and the constant current source 304 when the switch 302 is closed. The source of the p-type transistor 306 is connected to the voltage 104. The gate and drain of the p-type transistor 306 are connected to the gate of the p-type transistor of the switch 102 through the switch 302. The gate and drain of the p-type transistor 306 are connected to the constant current source 304 as well. The current flowing through the secondary leg 310 of the current mirror 312 will thus not exceed the current through the primary leg 308 when the switch 302 is closed.

[0038] In operation, the switch 120 is closed and then opened, resulting in a zero voltage over the capacitor 116. The diode-connected p-type transistor 306 naturally settles to the gate voltage necessary for the transistor 306 to conduct the reference current of the current source 304. The switch 302 is pulsed closed, which places p-type transistor 306’s gate voltage on the gate of the p- type transistor of the switch 102 to limit the maximum current through the memristor 106 to the current of the constant current source 304.

[0039] This voltage remains on the parasitic gate capacitance of p-type transistor 102 after the switch 302 opens. Specifically, when the switch 302 is closed, the current through the memristor 106 starts to build while the p-type transistor of the switch 102 is operating in an ohmic region, and then maximizes at no greater than the current of the constant current source 304 when the p-type transistor of the switch 102 transitions to operation in a saturation region. As such, the constant current source 304 effectively sets the current compliance of the memristor 106. [0040] The current flowing through the memristor 106 and the n-type transistor 124 is mirrored from the primary leg 112 of the current mirror 108 to the secondary leg 114 of the current mirror 108. The secondary leg 114 pulls this current through the capacitor 116 from the initial capacitor voltage 118. Pulling the current through the capacitor 116 charges the capacitor 116. As such, the voltage over the capacitor 116 increases and the output voltage122 decreases.

[0041] The total charge through the memristor 106 can be directly measured by measuring the voltage at the output 122 as in FIG. 1. The

capacitor 116 continues to accumulate charge, such that the voltage over the capacitor 116 increases and the voltage at the output 122 continues to decrease, until the voltage at the output 122 equals the reference voltage 212. As in FIG. 2, when the voltage at the output 122 drops to the reference voltage 212, the output 216 of the comparator 208 drops low. The output 216 of the comparator 208 turns on the switch 202, which correspondingly turns off the switch 102, terminating the stimulus voltage at the memristor 106.

[0042] Like the example of FIG. 2, the example of FIG. 3 in the case of a write stimulus pertains to the case in which the polarity of the memristor 106 is being set. Terminating the write stimulus in the reset polarity case can be similarly achieved, by implementing the charge metering circuit 300 in mirror fashion at the other end of the memristor 106. Furthermore, the current compliance provided by the constant current source 304 can be employed without stimulus termination. [0043] The charge metering circuits 100, 200, and 300 that have been described can be implemented in a variety of different ways. A semiconductor wafer may include a number of memory devices that each include an array of memristors 106, among other components. A charge metering circuit can be included in the scribe lines separating the memory devices, where the circuit is connected to a selected number of the memristors 106 of a selected number of the memory devices. The charge metering circuit can thus be used to grade and otherwise test the memory devices before the devices are separated from one another. The charge metering circuit may further be included within the memory devices themselves, to permit post-production grading and testing of the memory devices.

[0044] FIG. 4 shows an example method 400 for measuring the total charge through a memristor while a stimulus is applied to the memristor. The method 400 can be performed using the charge metering circuits 100, 200, and 300. A stimulus voltage 104 is applied to one terminal of the memristor 106

(402), and a primary leg 112 of a current mirror 108 responsively pulls a voltage at the other terminal of memristor 106 to a virtual ground level (404). A voltage at an output at a secondary leg 114 of the current mirror 108 is measured (406), from which the total charge through the memristor 106 can be determined (408). For instance, the voltage over the capacitor 116 can be computed as the voltage at the output 122 minus the initial capacitor voltage 118 (410), with the total charge through the memristor 106 computed as proportional to the computed voltage over the capacitor 116 (412). [0045] FIG. 5 shows an example method 500 for terminating a stimulus applied to a memristor when the total charge through the memristor has reached a threshold. The method 500 can be performed using the charge metering circuits 200 and 300. A stimulus voltage is applied to the memristor 106 (502). A secondary leg 114 of a current mirror 108, pulls current, which mirrors the current through a primary leg 112 of the current mirror 108, through a capacitor 116, which increases a voltage across the capacitor 116 (504) and thus reduces the voltage at an output 122. A comparator 216 compares the voltage at the output 122 to a reference voltage 212 (506). Responsive to the voltage at the output 122 being less than the reference voltage 212, the comparator 208 effectively terminates the stimulus at the memristor 106 (508), protecting the memristor 106 from conducting a total charge greater than a threshold charge corresponding to the reference voltage 212.

[0046] Charge metering circuits for a memristor have been described. The charge metering circuits permit the total charge through the memristor to be accurately measured while the memristor is undergoing application of a stimulus. The charge metering circuits may further terminate the stimulus to prevent the total charge from exceed a threshold charge. The charge metering circuits may also limit the current through the memristor when the stimulus is first applied.

Claims

We claim:

1. A charge metering circuit for a memristor, comprising:

a switch connected between a stimulus voltage and the memristor, the switch pulsed on to apply the stimulus voltage to the memristor;

a current mirror connected between a low-rail voltage and the memristor and having a primary leg and a secondary leg, the primary leg pulling a voltage at the memristor to a virtual ground voltage upon pulsing on of the switch;

a capacitor connected between a capacitor voltage and the secondary leg of the current mirror, the secondary leg pulling a current through the capacitor from the capacitor voltage.

2. The charge metering circuit of claim Error! Reference source not found., wherein the switch is a first switch,

and wherein the charge metering circuit further comprises:

a second switch connected in parallel with the capacitor between the capacitor voltage and the secondary leg of the current mirror, the second switch turned on to discharge the capacitor and then turned off prior to pulsing on of the first switch.

3. The charge metering circuit of claim 1 , further comprising:

an output at a junction of the capacitor and the secondary leg of the current mirror,

wherein a voltage over the capacitor is proportional to a total charge through the memristor after application of the stimulus voltage,

wherein the voltage over the capacitor is equal to a difference between the capacitor voltage and a voltage at the output,

and wherein the charge metering circuit measures the total charge through the memristor.

4. The charge metering circuit of claim 3, wherein the primary leg has a primary current and the secondary leg has a secondary current mirroring the primary current,

wherein the current pulled through the capacitor by the secondary leg from the capacitor voltage is equal to the secondary current through the secondary leg, and wherein pulling of the current through the capacitor charges the capacitor, decreasing the voltage at the output and increasing the voltage over the capacitor.

5. The charge metering circuit of claim 1 , wherein the switch comprises a p-type transistor operating in a digital manner as a binary switch,

and the primary leg and the secondary leg of the current mirror each comprises an n-type transistor operating in an analog manner.

6. The charge metering circuit of claim 1 , wherein the switch is a first switch, and the charge metering circuit further comprises:

a second switch controlling operation of the first switch;

a comparator having: a first input connected to a reference voltage;

a second input connected at a junction of the capacitor and the secondary leg of the current mirror; and

an output that opens the first switch when a voltage at the second input lowers to equal the reference voltage, terminating the stimulus voltage applied to the memristor,

wherein the charge metering circuit protects the memristor from

conducting a total charge greater than a threshold charge by terminating the stimulus voltage applied to the memristor when the voltage at the second input of the comparator equals the reference voltage.

7. The charge metering circuit of claim 6, further comprising:

a third switch controlling operation of the second switch, the third switch pulsed to pulse on the first switch to apply the stimulus voltage to the memristor.

8. The charge metering circuit of claim 7, wherein the first switch comprises a p-type transistor having a source connected to the stimulus voltage, a drain connected to the memristor, and a gate,

wherein the second switch comprises a p-type transistor having a source connected to the stimulus voltage, a drain connected to the gate of the first switch, and a gate connected to the output of the comparator,

wherein the third switch comprises an n-type transistor having a source connected to the low-rail voltage, a drain connected to the gate of the first switch, and a gate that is pulsed to pulse on the first switch to apply the stimulus voltage to the memristor.

9. The charge metering circuit of claim 7, further comprising:

a constant current source connected between the low-rail voltage and the third switch, limiting current through the memristor when the third switch is pulsed on.

10. The charge metering circuit of claim 9, wherein the first switch comprises a first p-type transistor having a source connected to the stimulus voltage, a drain connected to the memristor, and a gate,

wherein the second switch comprises a second p-type transistor having a source connected to the high-rail voltage, a drain connected to the gate of the first switch, and a gate connected to the output of the comparator,

wherein the third switch is connected to the gate of the first switch, and wherein the circuit further comprises:

a third p-type transistor having a source connected to the stimulus voltage, and a drain and a gate connected to the third switch and to the constant current source.

11. The charge metering circuit of claim 10, wherein the current mirror is a first current mirror,

wherein the first p-type transistor and the third p-type transistor form a second current mirror between the high-rail voltage and the constant current source when the third switch is closed, the third p-type transistor acting as a primary leg of the second current mirror and the first p-type transistor acting as a secondary leg of the second current mirror.

12. The charge metering circuit of claim 1 , wherein the switch is a first switch, and the charge metering circuit further comprises:

a second switch controlling operation of the first switch;

a constant current source connected between the low-rail voltage and the second switch, limiting current through the memristor when the second switch is pulsed on,

wherein the first switch comprises a first p-type transistor having a source connected to the stimulus voltage, a drain connected to the memristor, and a gate connected to the constant current source.

13. A method comprising:

applying a stimulus to a memristor;

responsive to application of the stimulus, pulling, by a current mirror connected between a low-rail voltage and the memristor, a voltage at the memristor to a virtual ground voltage;

pulling, by the current mirror, a current through a capacitor connected between a capacitor voltage and the current mirror, increasing an output voltage at the capacitor;

measuring the output voltage; and determining a total charge through the memristor based on the output voltage.

14. The method of claim Error! Reference source not found., wherein determining the total charge through the memristor comprises:

computing a voltage over the capacitor as the capacitor voltage minus the output voltage; and

computing the total charge through the memristor as proportional to the voltage over the capacitor.

15. A method comprising:

applying a stimulus to a memristor;

responsive to application of the stimulus, pulling, by a current mirror connected between a low-rail voltage and the memristor, a current through a capacitor connected between a capacitor voltage and the current mirror, decreasing an output voltage at the capacitor;

comparing, by a comparator, the output voltage to a reference voltage; and

responsive to the comparator determining that the output voltage is less than the reference voltage, terminating the stimulus from the memristor, protecting the memristor from conducting a total charge greater than a threshold charge.