WO2024259832A1 - Complementary storage circuit and memory - Google Patents

Abstract

The present disclosure provides a complementary storage circuit and a memory. The complementary storage circuit comprises storage units distributed in a matrix array, each storage unit comprises at least one group of P-channel field-effect transistors and N-channel field-effect transistors which are alternately connected, sources of the P-channel field-effect transistors are connected to drains of the N-channel field-effect transistors, and drains of the P-channel field-effect transistors are connected to sources of the N-channel field-effect transistors. According to the present disclosure, the density of a storage array can be improved, and the requirements for the driving capability of field-effect transistors are reduced.

Description

Complementary storage circuit and memory

This application claims priority to a patent application filed on June 20, 2023, entitled “Complementary Memory Circuits and Memory” with application number 202310736107.1.

Technical Field

The present disclosure relates to the technical field of semiconductors and CMOS hybrid integrated circuits, and in particular to a complementary memory array circuit and a memory using CMOS.

Background Art

With the continuous development of artificial intelligence and deep learning technology, artificial neural networks have been widely used in natural language processing, image recognition, autonomous driving, graph neural networks and other fields. However, the increasing size of the network has led to a large amount of energy consumption in the transfer of data between memory and traditional computing devices such as CPU and GPU, which is called the von Neumann bottleneck. The most important calculation in the artificial neural network algorithm is the vector matrix multiplication calculation (Vector Matrix Multiplication). Compute-In-Memory based on non-volatile memory (Non-volatile Memory, or non-volatile memory) stores weights in non-volatile memory units and performs simulated vector matrix multiplication calculations in the array, avoiding the frequent transfer of data between memory and computing units, and is considered to be a promising way to solve the von Neumann bottleneck.

At present, non-volatile memory devices such as RRAM, PCRAM, MRAM, FeRAM, FeFET, etc. store weights on the conductivity of the device after the weights are written. The devices are organized in the form of an array, and the input voltage from one end is used as the input of the vector-matrix multiplication. The array is calculated by Ohm's law and Kirchhoff's law, and the current obtained at the other end of the array is the summation result of the vector-matrix multiplication, and the summation result is usually read out using an analog-to-digital converter (ADC).

Among the various new non-volatile memories mentioned above, two-terminal non-volatile memories have attracted extensive attention and research due to their higher theoretical density and reduced process cost brought by simple structure. In practical applications, two-terminal memories need to form a storage array to achieve high-density structure and high-speed reading and writing. The existing methods mainly form a 1-transistor-1 memory (1T1R) array. The transistors in the mainstream method are connected to the memory array. N-type is often used. However, in actual use, on the one hand, due to the low power supply Vdd at advanced nodes, the maximum gate voltage that can be applied by the transistor is limited. On the other hand, when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor. Therefore, there is a problem of insufficient driving current during the operation of the two-terminal memory at advanced nodes, which limits the further reduction of the device size and the improvement of the storage array density.

Summary of the invention

In view of the above problems, the purpose of the present disclosure is to provide a complementary storage circuit and memory to solve the problems of voltage limitation in existing storage circuits, resulting in insufficient driving current, limiting the miniaturization of devices and increasing the density of storage arrays, etc.

The complementary storage circuit provided by the present disclosure includes storage units distributed in a matrix array, and the storage units include at least one group of P-channel field effect transistors and N-channel field effect transistors connected alternately; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; and the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor.

In addition, an optional technical solution is that the gates of N-channel field effect transistors are connected to form word line N, and the gates of P-channel field effect transistors are connected to form word line P; wherein an external pulse generator sends a preset pulse signal on word line N and word line P.

In addition, an optional technical solution is that the drain of the N-channel field effect transistor is connected to the first variable resistor, and the drain of the P-channel field effect transistor is connected to the second variable resistor; the other ends of the first variable resistor and the second variable resistor are respectively connected to the bit lines at corresponding positions.

In addition, an optional technical solution is that the storage unit includes M×N units, where M represents the number of rows and N represents the number of columns; wherein the bit lines of the first variable resistors located in the same row are shared, and the bit lines of the second variable resistors located in the same row are shared; the word lines N of the gates of the N-channel field effect transistors located in the same column are shared, and the word lines P of the gates of the P-channel field effect transistors located in the same column are shared.

In addition, an optional technical solution includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its own original data; in the write 1 mode and the write 0 mode, the specified storage unit is in a state representing 1, and the voltage of the specified storage unit is less than the preset voltage VDD; in the read mode, the source line of the storage unit is connected to the read voltage, so that the read current passes through the storage unit to the bit line, and the corresponding state of the storage unit is read from the bit line.

In addition, an optional technical solution is that in the storage mode, all word lines N, bit lines and source lines are The word line P is connected to GND, and the word line P is connected to a preset voltage VDD; the P-channel field effect transistor and the N-channel field effect transistor are both in the off state.

In addition, an optional technical solution is that in write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the write 1 voltage, and the target memory cell is written to state 1.

In addition, an optional technical solution is that in write 0 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 0 voltage, and the write current flows from the bit line through the target memory cell to the source line, and the target memory cell is written to state 0.

In addition, an optional technical solution is that, in the read mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to the read voltage, the bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the read voltage, the read current passes through the target memory cell to the bit line, and the corresponding state of the memory cell is read from the bit line.

On the other hand, the present disclosure further provides a memory, comprising the complementary memory circuit mentioned above.

Utilizing the complementary storage circuit and memory, the storage unit includes alternately connected P-channel field effect transistors and N-channel field effect transistors; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and a PMOS-like NAND-type storage unit structure is adopted. By using the NAND structure, the possibility of three-dimensional integration is realized, which is conducive to further improving the density of the storage array; at the same time, the introduction of PMOS can also effectively reduce the requirements for the driving capability of the field effect transistor in the case of series connection.

In order to achieve the above and related purposes, one or more aspects of the present disclosure include features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present disclosure in detail. However, these aspects indicate only some of the various ways in which the principles of the present disclosure can be used. In addition, the present disclosure is intended to include all these aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present disclosure, other objects and results of the present disclosure will become more apparent and easier to understand. In the accompanying drawings:

FIG1 is a schematic diagram of a local storage unit structure of a complementary storage circuit according to an embodiment of the present disclosure;

FIG2 is a schematic diagram of a matrix array structure of a complementary memory circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of operating voltages of a complementary memory circuit according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

The maximum gate voltage that can be applied to the transistors in the current N-type transistor storage array is limited, and when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor, so there is a problem of insufficient driving current during the operation of the two-terminal memory at the advanced node. To solve the above problems, the present disclosure provides a complementary storage circuit and a memory, wherein the storage unit includes a P-channel field effect transistor and an N-channel field effect transistor that are alternately connected; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and a PMOS-like NAND-type storage unit structure is adopted. By using the NAND structure, the possibility of three-dimensional integration is realized, which is conducive to further improving the density of the storage array; at the same time, it can also effectively reduce the requirements for the driving ability of the field effect transistor in the case of series connection.

In the description of the present disclosure, the line connecting the gate of the transistor is called the word line (Word Line, WL), the line connecting the source of the transistor is called the source line (Source Line, SL), and the line connecting one end of the device is called the bit line (Bit Line, BL).

To describe the complementary storage circuit and memory in the present disclosure in detail, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

1 and 2 respectively show a schematic structure of a local storage unit and a matrix array structure of a complementary storage circuit according to an embodiment of the present disclosure.

As shown in FIG. 1 and FIG. 2 , the complementary storage circuit of the embodiment of the present disclosure includes a plurality of storage units distributed in a matrix array, and each storage unit further includes at least one group of P-channel field effect transistors (PMOS devices for short) and N-channel field effect transistors (NMOS devices for short) connected alternately; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and the like from top to bottom. The secondary connections form a column of storage circuits.

Among them, the gates of all N-channel field effect transistors are connected to form a word line N (abbreviated as WLN), and the gates of all P-channel field effect transistors are connected to form a word line P (abbreviated as WLP); wherein, an external pulse generator sends a preset pulse signal on the word line N and the word line P, thereby turning on or off the corresponding field effect transistors.

As a specific example, in the complementary storage circuit of the embodiment of the present disclosure, the drain of the N-channel field effect transistor is connected to the first variable resistor, and the drain of the P-channel field effect transistor is connected to the second variable resistor, that is, the first variable resistor is connected in parallel with the source of the P-channel field effect transistor and the drain of the N-channel field effect transistor, and the second variable resistor is connected in parallel with the drain of the P-channel field effect transistor and the source of the N-channel field effect transistor, and the other ends of the first variable resistor and the second variable resistor are respectively connected to the bit lines at corresponding positions.

Specifically, the number of storage cells can be set according to requirements. As an example, the storage cells may include M×N cells, where M represents the number of rows, N represents the number of columns, and both M and N are positive integers; wherein the bit lines of the first variable resistors in the same row are shared, and the bit lines of the second variable resistors in the same row are shared; the word lines N of the gates of the N-channel field effect transistors in the same column are shared, and the word lines P of the gates of the P-channel field effect transistors in the same column are shared, thereby ultimately forming a matrix array structure as shown in Figure 2.

It should be noted that the series structure of the local storage unit of the complementary storage circuit shown in FIG1 can be of any length. In the figure, only four field effect transistors are marked as examples, in which P-channel field effect transistors and N-channel field effect transistors are alternately arranged to form a long string of transistors, and the corresponding field effect transistors are controlled to be turned on by signals on the word line P and the word line N, and the operating voltage applied on the source line and the bit line can complete the reading and writing functions of the storage unit.

Among them, when a positive voltage is input at both ends of the field effect transistor, since the transmission positive voltage Vsg of the P-channel field effect transistor is not affected by the voltage at the other end, its gate-source voltage can reach VDD, and the voltage of the N-channel field effect transistor at this time is VDD-I*R, where I and R represent the current flowing through the N-channel field effect transistor and the device resistance, respectively, and the typical value of I*R is 0.7V. In this case, the saturation current of the PMOS device will be significantly greater than that of the NMOS device of the same size. In other words, its voltage division (or equivalent output resistance) is much smaller than that of the NMOS device when the same current flows.

As a specific example, in the process of operating the memory cell shown in FIG. 1 , when SL0 and SL1 are both connected to positive voltage and all field effect transistors are turned on, for the target device to be operated, it can be regarded as The two SLs drive the target device together through the field effect transistor. Take the series structure including three variable resistors corresponding to BL0~BL2 as an example. For the field effect transistor connected with BL1 in the middle, in the specific structure shown in Figure 1, SL0 is transmitted to the target device after passing through 1 NMOS and 1 PMOS, and SL1 is transmitted to the target device after passing through 1 PMOS and 1 NMOS. If all devices except the target device are floating, it can be regarded as two SLs driving the target device in parallel after passing through 1 NMOS and 1 PMOS respectively.

It can be seen that the complementary storage circuit provided by the present invention has a driving capability that is significantly stronger than that of a storage structure composed entirely of NMOS when SL is connected to a positive voltage. For units with longer lengths, the structure used in the present invention can replace half of the NMOS in the path from each device to the two SL ends with PMOS. Compared with simply using NMOS, the replaced PMOS has better high voltage transmission capability, and the entire circuit has a more balanced driving capability for high and low voltages, thereby alleviating the problem of insufficient driving capability of the original transistor in a certain direction, which is conducive to further improving storage density.

In addition, in the matrix array structure shown in FIG. 2 , there is no special requirement for the connection relationship between the storage cells SL. The storage cell structures can be placed vertically and arranged in an array in the horizontal direction, similar to the 3D-NAND structure. In this case, SL0 and SL1 can form a cross array; or, SL0 is not connected but the SL1 of all cells are connected to form an array structure with a common source at one end, etc.

In a specific embodiment of the present disclosure, the complementary storage circuit has four working modes, namely, a storage mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the storage mode, each storage unit does not work and stores its own original data; in the write 1 mode and the write 0 mode, the specified storage unit is in a state indicating 1, and the voltage of the specified storage unit is less than a preset voltage VDD; in the read mode, the source line of the storage unit is connected to the read voltage, so that the read current passes through the storage unit to the bit line, and the corresponding state of the storage unit is read from the bit line.

Specifically, in the save mode, all word lines N, bit lines and source lines are connected to GND, and word line P is connected to a preset voltage VDD; P-channel field effect transistors and N-channel field effect transistors are both in the off state; in the write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to a write 1 voltage, and the target memory cell is written to state 1; in the write 0 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 0 voltage, and a write current flows from the bit line through the target memory cell to the source line, and the target memory cell is written to state 0. And, in the read mode, word line N is connected to a preset voltage VDD, word line P is connected to GND; Line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to the read voltage, the bit line of the target memory cell is connected to GND, the remaining bit lines are connected to the read voltage, the read current passes through the target memory cell to the bit line, and the corresponding state of the memory cell is read from the bit line.

As a specific example, FIG3 shows a schematic structure of an operating voltage of a complementary storage circuit according to an embodiment of the present disclosure.

As shown in Figures 1 to 3, there are four working modes for the complementary storage circuit, namely, the save mode, the write 1 mode, the write 0 mode and the read mode; it is assumed that when a positive voltage is applied to SL, the memory writes 1, and when a positive voltage is applied to BL, the memory writes 0. VDD and GND are used below to refer to the high level and ground in the circuit, respectively. In addition, it is assumed that all SLs can be independently gated. At this time, the gating function of WLN and WLP turns on only the field effect transistor of the specified storage unit, and the transistors other than the specified unit will be completely turned off. Since no current flows through other transistors, only the operation mode of the specified device of the specified unit with the transistor turned on is described. In addition, for the unit with the transistor turned on, the SLs at both ends are actually directly connected through the turned-on transistor and have the same voltage, so only one SL voltage is needed to refer to the voltage applied to the upper and lower ends of the SL of the turned-on unit.

Specifically, assuming that the operation target device is the device corresponding to BL1 of the leftmost unit, that is, the device in the second row and first column in Figure 2, during the operation, the matrix array is first in an inoperative state, and all storage cells save data, and then the operations of write 1, read, and write 0 are successively performed on the specified cells.

Among them, in the non-working state: all WLN, BL, and SL are connected to GND, and all WLP are connected to VDD. At this time, all transistors are in the off state and the matrix array does not work.

Write 1: WLN is connected to VDD, WLP is connected to GND. After the unit where the target device is located is selected, SL is connected to the write 1 voltage, BL1 is connected to GND, and the other BLs are connected to the write 1 voltage. The voltage connection method of other lines is consistent with the non-working state. At this time, the target storage device is written to state 1.

Read: WLN is connected to VDD, WLP is connected to GND. After the unit where the target device is located is selected, SL is connected to the read voltage, BL1 is connected to GND, and the remaining BLs are connected to the read voltage. The connection method of other lines is consistent with the non-working state. At this time, the read current flows through the target memory to BL1, and the corresponding state of the target device can be read from BL1.

Write 0: Connect WLN to VDD and WLP to GND. After selecting the unit where the target device is located, connect BL1 to the write 0 voltage. The connection method of the remaining lines is consistent with the non-working state. At this time, the write current flows from BL1 through the target memory to SL0 and SL1, and the target device is written to state 0.

It should be noted that the present disclosure only explains the method of operating a single storage unit in an array at a time, and only one row and one column are selected each time. A person with ordinary knowledge in the technical field should understand that the operation method The method can be easily extended to the selection of multiple rows and columns, so that the cells of multiple rows and columns can be read and written in parallel, thereby increasing the data throughput of the array.

Corresponding to the above complementary storage circuit, the present disclosure further provides a memory, including the above complementary storage circuit. The specific embodiments of the memory can refer to the description in the complementary storage circuit embodiment, which will not be described here one by one.

According to the complementary storage circuit and memory disclosed above, a NAND-like storage cell structure of PMOS is adopted. By using the NAND structure, the possibility of three-dimensional integration is realized, which is conducive to further improving the density of the storage array; at the same time, the introduction of PMOS can also effectively reduce the requirements for the driving capability of the field effect transistor in the case of series connection.

It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

A complementary storage circuit, characterized in that it comprises storage cells arranged in a matrix array, wherein the storage cells comprise at least one group of P-channel field effect transistors and N-channel field effect transistors connected alternately; wherein: The source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; The drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor. The complementary memory circuit according to claim 1, characterized in that The gates of the N-channel field effect transistors are connected to form a word line N, and the gates of the P-channel field effect transistors are connected to form a word line P; wherein, An external pulse generator sends a preset pulse signal on the word line N and the word line P. The complementary memory circuit according to claim 2, characterized in that The drain of the N-channel field effect transistor is connected to the first variable resistor, and the drain of the P-channel field effect transistor is connected to the second variable resistor; The other ends of the first variable resistor and the second variable resistor are respectively connected to bit lines at corresponding positions. The complementary storage circuit according to claim 3, characterized in that the storage cells include M×N, wherein M represents the number of rows and N represents the number of columns; wherein, The bit lines of the first variable resistors in the same row are shared, and the bit lines of the second variable resistors in the same row are shared; The gates of the N-channel field effect transistors in the same column share a common word line N, and the gates of the P-channel field effect transistors in the same column share a common word line P. The complementary storage circuit according to claim 4, characterized in that it includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, In the saving mode, each storage unit does not work and saves its own original data; In the write 1 mode and the write 0 mode, the designated storage cell is in a state indicating 1, And the voltage of the designated storage unit is less than a preset voltage VDD; In the read mode, the source line of the memory cell is connected to a read voltage, so that a read current passes through the memory cell to reach the bit line, and the corresponding state of the memory cell is read from the bit line. The complementary memory circuit according to claim 5, characterized in that In the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to a preset voltage VDD; The P-channel field effect transistor and the N-channel field effect transistor are both in an off state. The complementary memory circuit according to claim 5, characterized in that In the write 1 mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; After the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, the target bit line of the target memory cell is connected to GND, and the remaining bit lines are connected to the write 1 voltage, and the target memory cell is written to state 1. The complementary memory circuit according to claim 5, characterized in that In the write 0 mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; After the target memory cell is selected, the source line of the target memory cell is connected to a preset write-0 voltage, a write current flows from the bit line through the target memory cell to the source line, and the target memory cell is written to state 0. The complementary memory circuit according to claim 5, characterized in that In the read mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; After the target memory cell is selected, the source line of the target memory cell is connected to a read voltage, the bit line of the target memory cell is connected to GND, the remaining bit lines are connected to a read voltage, a read current passes through the target memory cell to the bit line, and the corresponding state of the memory cell is read from the bit line. A memory comprising the complementary memory circuit as claimed in any one of claims 1 to 9.