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WO2018126484A1 - Procédé et appareil d'amélioration de détails d'image parallèle reconfigurable - Google Patents

Procédé et appareil d'amélioration de détails d'image parallèle reconfigurable Download PDF

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Publication number
WO2018126484A1
WO2018126484A1 PCT/CN2017/070670 CN2017070670W WO2018126484A1 WO 2018126484 A1 WO2018126484 A1 WO 2018126484A1 CN 2017070670 W CN2017070670 W CN 2017070670W WO 2018126484 A1 WO2018126484 A1 WO 2018126484A1
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buffer
pixel
parallel
mean
detail
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Chinese (zh)
Inventor
刘壮
郭若杉
谭吉来
李瑞玲
韩睿
李晨
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Institute of Automation of Chinese Academy of Science
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Institute of Automation of Chinese Academy of Science
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
    • H04N23/12—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with one sensor only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals

Definitions

  • the present invention relates to the field of video image processing, and in particular, to a reconfigurable parallel image detail enhancement method and apparatus.
  • one of the mainstream development directions of video technology is ultra high definition (4K resolution) display technology.
  • 4K resolution 4K resolution
  • the number of pixels in 4K video is increased from 2M to 8M, which puts higher requirements on the image quality and performance of image enhancement algorithms.
  • the traditional video image detail enhancement solution is mainly designed for the requirements of HD and the following standards.
  • 4K image processing requirements it is very likely to have insufficient processing power; at the same time, 4K ultra-high definition images can bring more detailed picture effects. Therefore, when the existing detail enhancement algorithm is applied to a 4K resolution image, negative effects such as overshoot may be more noticeable to the viewer.
  • an aspect of the present invention provides a reconfigurable parallel image detail enhancement method, including the following steps:
  • Step 1 loading the image data to be processed into a buffer;
  • the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N;
  • the pixel lattice is detachable a plurality of one-dimensional lattices comprising N pixel points;
  • Step 2 performing horizontal and vertical filtering on each pixel to be enhanced in the one-dimensional lattice to obtain detailed signals in two directions;
  • Step 3 nucleating the detail signal in two directions, filtering out the minute detail signal introduced by the image noise;
  • Step 4 controlling the intensity of the enhanced detail signal by performing gray scale symmetry on both sides of the neighborhood of the pixel to be enhanced and the signal intensity of the pixel to be enhanced, performing overshoot suppression, and completing two overshoot suppression
  • the detail signals are added to obtain the detail signals of the N pixels;
  • Step 5 further performing amplitude suppression on the detail signal obtained in step 4.
  • Step 6 Step 1 to step 5 are performed on each one-dimensional lattice in the image data to be processed in sequence, and the detail enhancement of the image data to be processed is completed.
  • the buffer comprises NM buffer units of size N pixels; the buffer is provided with 4 read ports and 4 write ports.
  • the filtering in the horizontal and vertical directions corresponds to a horizontal NH-order and a vertical NV-order one-dimensional filter, respectively calculating left and right (NH-1)/2 pixels and upper and lower respectively.
  • (NV-1)/2 pixels of gray combined with the gray value of the pixel to obtain the detail signal in both directions of the pixel.
  • the buffer is a multi-granular discrete memory structure.
  • the filtering in the horizontal and vertical directions is specifically performing spatial convolution of the filtering template and the image data, and the filtering result is expressed as:
  • (i, j) represents the pixel point in the i-th row and j-th column position in the image data
  • DEH(i, j) represents the horizontal filtering result at (i, j)
  • DEV(i, j) represents (i , j) vertical filtering results
  • P (i, j) represents the pixel gray level at the i-th row and j-th column position of the image
  • FH (k) represents the k-th element of the horizontal template
  • FV (t) represents the vertical template t elements.
  • the overshoot suppression in step 4 is to separately process the horizontal detail signal and the vertical detail signal, and then add the two detail signals that have been overshoot suppressed to obtain the final detail signal by:
  • Step 41 using the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels of the point, the absolute difference operation is obtained, that is, the left and right sides are obtained ( NH-1)/2 and upper and lower (NV-1)/2 total four sets of grayscale absolute difference;
  • Step 42 Calculate the mean values of the four groups of absolute differences: Mean_L, Mean_R, Mean_T, and Mean_B, that is, the mean value of the four gray scale differences between the top and bottom of the point;
  • Step 43 calculating a first overshoot suppression factor alpha and a second overshoot suppression factor beta, the formula is
  • ka is the set coefficient and Y_abs_mean is the absolute difference of the mean difference of the gray scale absolute, ie
  • the detail signal strength de de_h+de_v, where de_h is the detail signal strength in the horizontal direction and de_v is the detail signal strength in the vertical direction.
  • the amplitude suppression in step 5 is as follows:
  • Step 51 multiplying de_ss by the detail enhancement coefficient gain to obtain an enhanced detail signal de_gain
  • Step 52 and performing amplitude suppression according to the following formula, and obtaining a final detail signal de_final;
  • Th is the set threshold and Max_de is the set maximum.
  • the parameter pre-loading step includes: loading the curing parameters in the preset horizontal and vertical filtering, nucleation filtering, overshoot suppression and amplitude suppression to the general buffer Device.
  • the image data to be processed in step 1 is obtained by sequentially splitting the image data according to the pixel matrix of R*Q; the method is loaded into the buffer in step 1, and the method is:
  • the image data to be processed is sequentially selected and processed through steps 2 to 6, until all the image data to be processed is processed.
  • a reconfigurable parallel image detail enhancement apparatus comprising: a local memory, a memory access control unit, a general purpose buffer, a parallel arithmetic logic unit ALU, a state machine, and a parallel multiplication Accumulator MAC;
  • the local memory is configured to save input and output image data and parameters required by a parallel video image contrast enhancement algorithm, and the memory supports parallel access;
  • the memory access control unit is configured to exchange data between the local memory and the general buffer
  • the general purpose buffer is used to buffer all data and intermediate results required for a complete processing flow, and the buffer can be directly indexed by an address;
  • the parallel arithmetic logic unit is configured to perform non-multiply-like arithmetic and logic operations involved in a parallel video image contrast enhancement algorithm; the degree of parallelism is N;
  • the state machine for generating control signals for all functional components
  • the parallel multiply accumulator is configured to perform a multiplication correlation operation, and the degree of parallelism is N;
  • the state machine is respectively connected to the parallel arithmetic logic unit, the memory access control unit, the general buffer, and the parallel multiply accumulator through a communication line; the local memory is connected to the memory access control unit through a communication line; the universal buffer is communicated
  • the lines are respectively connected to the memory access control unit, the parallel arithmetic logic unit, and the parallel multiply accumulator; the parallel arithmetic logic unit is connected to the parallel multiply accumulator via a communication line.
  • FIG. 1 is a schematic structural diagram of a reconfigurable parallel image detail enhancement apparatus of the present invention
  • FIG. 2 is a flow chart of a parallel image detail enhancement method provided by the present invention.
  • FIG. 3 is a schematic diagram of a buffer of a general buffer in accordance with an embodiment of the present invention.
  • 4 is a diagram showing an example of horizontal 7th-order filtering and vertical 5th-order filtering
  • FIG. 5 is a diagram showing an example of coring filtering noise reduction according to an embodiment of the present invention.
  • 6(a) to (d) are diagrams showing an example of a scene in which an overshoot phenomenon is likely to occur
  • FIG. 7 is a diagram showing an example of an overshoot suppression factor alpha calculation curve in accordance with an embodiment of the present invention.
  • FIG. 8 is a diagram showing an example of an overshoot suppression factor beta calculation curve in accordance with an embodiment of the present invention.
  • FIG. 9 is a diagram showing an example of an overshoot suppression process in accordance with an embodiment of the present invention.
  • Figure 10 is an illustration of interpolation along an edge in accordance with an embodiment of the present invention.
  • a reconfigurable parallel image detail enhancement apparatus of the present invention includes a local memory, a memory access control unit, a general purpose buffer, an parallel arithmetic logic unit (ALU), a state machine, and a parallel multiply accumulator (MAC);
  • ALU parallel arithmetic logic unit
  • MAC parallel multiply accumulator
  • the local memory is configured to save input and output image data and parameters required by a parallel video image contrast enhancement algorithm, and the memory supports parallel access;
  • the memory access control unit is used for data exchange between the local memory and the general buffer; in this embodiment, three memory access control units with completely identical functions are used, which breaks through the bottleneck of the memory access;
  • the general purpose buffer is used to buffer all data and intermediate results required for a complete processing flow, and the buffer can be directly indexed by an address;
  • the parallel arithmetic logic unit is configured to perform non-multiply-like arithmetic and logic operations involved in a parallel video image contrast enhancement algorithm; the degree of parallelism is N;
  • the state machine for generating control signals for all functional components
  • the parallel multiply accumulator is configured to perform a multiplication correlation operation, and the degree of parallelism is N;
  • the state machine is respectively connected to the parallel arithmetic logic unit, the memory access control unit, the general buffer, and the parallel multiply accumulator through a communication line; the local memory is connected to the memory access control unit through a communication line; the universal buffer is communicated
  • the lines are respectively connected to the memory access control unit, the parallel arithmetic logic unit, and the parallel multiply accumulator; the parallel arithmetic logic unit is connected to the parallel multiply accumulator via a communication line.
  • the device When the enhancement algorithm needs to be changed, the device only needs to reprogram the state machine, generate a new control signal, and update the algorithm parameters in the local memory to quickly implement the algorithm iteration without redesigning the manufacturing hardware circuit.
  • the invention also proposes a reconfigurable parallel image detail enhancement method, as shown in FIG. 2, comprising the following steps:
  • Step 1 data buffering: loading the image data to be processed into a buffer; the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; Split into multiple one-dimensional lattices containing N pixel points;
  • Step 2 filtering: performing horizontal and vertical filtering on each pixel to be enhanced in the one-dimensional lattice, and acquiring detailed signals in two directions;
  • Step 3 noise reduction: nucleating and filtering the detail signal in two directions, filtering out the minute detail signal introduced by the image noise;
  • Step 4 Overshoot suppression: the gray level symmetry on both sides of the neighborhood of the pixel to be enhanced and the detail signal strength of the pixel to be enhanced are used to control the enhanced detail signal strength, and the overshoot suppression is performed, and the overshoot is completed.
  • the two detail signals of the suppression are added to obtain the detail signals of the N pixel points;
  • Step 5 amplitude suppression: further performing amplitude suppression on the detail signal obtained in step 4;
  • Step 6 Cache data update: by updating the data in the buffer, step 1 to step 5 of each one-dimensional lattice in the image data to be processed are sequentially processed to complete the detail enhancement of the image data to be processed.
  • the embodiment further includes a parameter pre-loading step before the step 1, the parameter pre-loading step includes: loading the curing parameters in the preset horizontal and vertical filtering, nucleation filtering, overshoot suppression and amplitude suppression to the general buffer. Device.
  • This step belongs to the initialization phase of the apparatus of the present invention, and the curing parameters such as the filter coefficients in the horizontal and vertical directions, the thresholds used in the nucleation filtering, the overshoot suppression, and the amplitude suppression are preloaded into the general purpose buffer.
  • the general-purpose buffer (represented by a capital letter M) has a total of NM buffer units of size N pixels, and is equipped with four read ports (r0, r1, r2, r3) and four.
  • the write port (w0, w1, w2, w3) can carry high-speed read and write operations.
  • the general-purpose buffer M supports direct reading and writing of NM buffer units by using serial numbers, which facilitates the repeated use of data.
  • the universal buffer used in the present invention operates in synchronization with the arithmetic unit, thereby avoiding the problem that the high-speed arithmetic unit waits for the low-speed storage unit.
  • the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; the pixel lattice is detachable Divided into a plurality of one-dimensional lattices containing N pixel points.
  • the invention provides a processing method with parallelism of N, that is equivalent to N filters working at the same time, so it is necessary to buffer the NH column N pixels or NV rows N pixels in the general buffer before performing filtering.
  • the parallel processing apparatus and method of the present invention can be regarded as an apparatus and method for processing N-dimensional vector data, and thus the present invention will be described in detail from the viewpoint of the operation of the N-dimensional vector in the subsequent part of this document.
  • the algorithm of the present invention involves parallel processing of a column of pixels, that is, column access is required for the memory, and the conventional memory does not support an efficient column-by-column access mode. Therefore, the device of the present invention employs a multi-granular discrete memory.
  • the structure please refer to "Patent No. 201110460585.1, the name is multi-granular parallel storage system and memory”.
  • the image detail enhancement method of the invention first needs to obtain the detail signals in the horizontal and vertical directions by filtering, and specifically adopts a one-dimensional filter of horizontal NH order and vertical NV order to realize the extraction of the detail signal.
  • the higher the filter order the stronger the extraction ability of the detail signal.
  • the negative effects such as the overshoot effect are more obvious.
  • the level 5 or 7 is usually adopted.
  • Figure 4 is a single pixel horizontal 7th order vertical 5th order filter Wave diagram. Each time a detail signal of one pixel is acquired, the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels are required.
  • the invention realizes the extraction of the detail signal by two horizontal and vertical one-dimensional filters, and the specific operation is to spatially convolve the filtering template and the image, and the specific description is as follows:
  • the horizontal filter template is FH
  • the vertical filter template is FV
  • FH(k) is used to represent the kth element of the horizontal template
  • FV(t) is the tth element of the vertical template
  • P(i,j) is the i-th line of the image.
  • the pixel gray level at the j column position, the horizontal filtering result DEH(i,j) at the (i,j) pixel point and the vertical filtering result DEV(i,j) can be expressed as the formula (1), the formula (2) :
  • FH(0) and FV(0) correspond to the intermediate position elements of the filtering template.
  • the present invention employs parallel processing, so each element of the filtered template can be considered as an N-dimensional vector, and P can be regarded as the gradation of successive N pixels of the ith row or the j-th column.
  • the vector multiplication involved in the method of the present invention is different from the mathematical outer product or inner product.
  • the vector multiplication is to multiply the corresponding position elements of two identical dimensional vectors, and the result is still an N dimension. vector.
  • a two-dimensional vector is taken as an example for simplicity.
  • a1, a2, b1, and b2 are real numbers
  • a1b1 and a2b2 represent real products.
  • the device of the present invention When the filtering operation is performed, the device of the present invention firstly sends the image data to be processed and the filter coefficients in the buffer in the general buffer to the register of the MAC, and the MAC has four equivalent registers of width N, To complete the N-dimensional vector multiplication and accumulation operations, the result of the multiply-accumulate operation can be returned to the general purpose buffer to facilitate being called again or directly to other computing components for subsequent processing.
  • the invention uses the nucleation filtering to suppress the noise contained in the extracted detail signal.
  • the nucleation filtering principle is: the default detail signal is superimposed with a relatively small noise signal, so the detail signal is subtracted by a known nuclear filtering threshold. Smaller value, that is, no noisysy detail signal.
  • the specific operation is to first judge the positive and negative of the detail signal and obtain the symbol flag. If the signal is positive, the flag is 1, otherwise it is -1; then the absolute value of the detail signal is taken, and the absolute value is subtracted
  • the nucleation filter threshold, for non-positive results, is all considered to be 0; finally, the subtraction result is multiplied by the sign bit to obtain a noise reduction result.
  • Figure 5 is a schematic diagram of the input-output relationship of the nucleation filter.
  • This step involves (in comparison with zero) the absolute value, the subtraction method, the maximum value and the multiplication operation. Except for the multiplication operation, the rest of the operations are performed by the parallel arithmetic logic unit ALU. Similar to MAC, ALU also has four fully equivalent N-dimensional vector registers, which can perform arithmetic and logic operations on N data at the same time.
  • the invention controls the amplitude of the detail enhancement according to the size of the detail signal and the gray level symmetry of the corresponding pixel point neighborhood, thereby implementing overshoot suppression.
  • the overshoot phenomenon usually occurs in areas where the gradation changes greatly (that is, the details are rich) and the gray scale is asymmetrical.
  • Fig. 6(a) to (d) show four cases in which the horizontal direction is asymmetrical and prone to overshoot, and the vertical direction is similar.
  • the strategy for overshoot suppression of the present invention is to separately process the horizontal detail signal and the vertical detail signal, and then add the two detail signals that have been overshoot suppressed to obtain the final detail signal.
  • the specific method is as follows:
  • Step 41 using the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels of the point, the absolute difference operation is obtained, that is, the left and right sides are obtained ( NH-1)/2 and upper and lower (NV-1)/2 total four sets of grayscale absolute difference;
  • Step 42 Calculate the mean values of the four groups of absolute differences: Mean_L, Mean_R, Mean_T, and Mean_B, that is, the mean value of the four gray scale differences between the top and bottom of the point;
  • step 43 the first overshoot suppression factor alpha is obtained by using the curve shown in FIG. 7, as shown in formula (3).
  • ka is the set coefficient and Y_abs_mean is the absolute difference of the grayscale absolute difference mean, ie
  • the second overshoot suppression factor beta related to the detail signal strength is calculated by the following formula, as shown in formula (4);
  • the X of de_ss_X in Fig. 9 represents h or v, that is, a detail signal in the horizontal or vertical direction.
  • Step 51 amplifying the overshoot suppression detail signal de_ss by multiplying de_ss by the detail enhancement coefficient gain in the MAC to obtain an enhanced detail signal de_gain;
  • step 52 the result is output to the ALU, and the amplitude suppression is performed according to the curve shown in FIG. 10 in the ALU, and the final detail signal de_final is obtained, as shown in the formula (5).
  • Th is the set threshold and Max_de is the set maximum.
  • Yout and Yin are the pixel gradation of the output and the pixel gradation of the input, respectively. Yout first outputs to the general purpose buffer, which is then stored by the fetch control unit into the local memory.
  • steps 1 to 5 of each of the one-dimensional lattices in the image data to be processed are sequentially processed to complete the detail enhancement of the image data to be processed.
  • the above process explains the complete processing flow of the present invention.
  • the invention realizes the reuse of hardware resources by programming the state machine and using the general buffer design, and avoids the design of the traditional dedicated circuit scheme when running the complex algorithm.
  • the shortcomings of long stream period and high version iteration cost are the shortcomings of long stream period and high version iteration cost.

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Abstract

La présente invention concerne un procédé d'amélioration de détails d'image parallèle reconfigurable. Le procédé consiste à précharger un paramètre, mettre des données en tampon, exécuter un filtrage horizontal et vertical, exécuter un filtrage central, supprimer un dépassement, supprimer une amplitude, et mettre à jour de données en cache. La présente invention concerne en outre un appareil d'amélioration de détails d'image parallèle reconfigurable. L'appareil comprend une mémoire locale, une unité de commande d'accès à la mémoire, un tampon général, une unité logique arithmétique parallèle (ALU), un automate à états, et un accumulateur-multiplicateur parallèle (MAC). La présente invention améliore un signal de détails d'image qui éclaircit une zone texturée et améliore l'efficacité d'utilisation de données correspondantes, réduit l'interaction de données entre un composant opérationnel et une mémoire périphérique, abaisse la pression de bande passante d'accès à la mémoire, et permet de réutiliser des ressources matérielles.
PCT/CN2017/070670 2017-01-09 2017-01-09 Procédé et appareil d'amélioration de détails d'image parallèle reconfigurable Ceased WO2018126484A1 (fr)

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CN111754413A (zh) * 2019-03-29 2020-10-09 北京京东尚科信息技术有限公司 图像处理方法、装置、设备及存储介质
CN112486903A (zh) * 2020-12-18 2021-03-12 清华大学 可重构处理单元、可重构处理单元阵列及其运行方法

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CN112486903A (zh) * 2020-12-18 2021-03-12 清华大学 可重构处理单元、可重构处理单元阵列及其运行方法

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