WO2018126484A1 - Reconfigurable parallel image detail enhancing method and apparatus - Google Patents

Abstract

The present invention relates to a reconfigurable parallel image detail enhancing method, comprising: parameter pre-loading, data buffering, horizontal and vertical filtering, coring filtering, overshoot suppression, amplitude suppression and cached data updating. The present invention further relates to a reconfigurable parallel image detail enhancing apparatus, comprising a local memory, a memory access control unit, a general buffer, a parallel arithmetic logic unit (ALU), a state machine and a parallel multiply-accumulator (MAC). The present invention enhances an image detail signal, so that a textured area is more clear, and improves the data usage efficiency of same, reduces the data interaction between an operational component and a peripheral memory, lowers the memory access bandwidth pressure, and can achieve the repeated utilization of hardware resources.

Description

Reconfigurable parallel image detail enhancement method and device Technical field

The present invention relates to the field of video image processing, and in particular, to a reconfigurable parallel image detail enhancement method and apparatus.

Background technique

At present, one of the mainstream development directions of video technology is ultra high definition (4K resolution) display technology. Compared with high-definition (1920*1080) video, the number of pixels in 4K video is increased from 2M to 8M, which puts higher requirements on the image quality and performance of image enhancement algorithms.

The traditional video image detail enhancement solution is mainly designed for the requirements of HD and the following standards. In the face of 4K image processing requirements, it is very likely to have insufficient processing power; at the same time, 4K ultra-high definition images can bring more detailed picture effects. Therefore, when the existing detail enhancement algorithm is applied to a 4K resolution image, negative effects such as overshoot may be more noticeable to the viewer.

In addition, since the conventional solution usually adopts a dedicated integrated circuit chip of a curing algorithm as a specific implementation scheme, the cost pressure is huge when faced with the need for algorithm upgrade.

Therefore, it is necessary to propose a new video image detail enhancement solution. The requirement of the scheme is that 1 can improve the image sharpness, and 2 negative effects such as overshoot and noise amplification caused by detail enhancement are better suppressed. 3 to meet the processing needs of real-time ultra-high-definition video stream, 4 under the premise of cost control, with the potential for algorithm upgrade.

Summary of the invention

In order to solve the above problems in the prior art, an aspect of the present invention provides a reconfigurable parallel image detail enhancement method, including the following steps:

Step 1: loading the image data to be processed into a buffer; the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; the pixel lattice is detachable a plurality of one-dimensional lattices comprising N pixel points;

Step 2: performing horizontal and vertical filtering on each pixel to be enhanced in the one-dimensional lattice to obtain detailed signals in two directions;

Step 3, nucleating the detail signal in two directions, filtering out the minute detail signal introduced by the image noise;

Step 4: controlling the intensity of the enhanced detail signal by performing gray scale symmetry on both sides of the neighborhood of the pixel to be enhanced and the signal intensity of the pixel to be enhanced, performing overshoot suppression, and completing two overshoot suppression The detail signals are added to obtain the detail signals of the N pixels;

Step 5, further performing amplitude suppression on the detail signal obtained in step 4;

Step 6: Step 1 to step 5 are performed on each one-dimensional lattice in the image data to be processed in sequence, and the detail enhancement of the image data to be processed is completed.

Preferably, the buffer comprises NM buffer units of size N pixels; the buffer is provided with 4 read ports and 4 write ports.

Preferably, the filtering in the horizontal and vertical directions corresponds to a horizontal NH-order and a vertical NV-order one-dimensional filter, respectively calculating left and right (NH-1)/2 pixels and upper and lower respectively. (NV-1)/2 pixels of gray, combined with the gray value of the pixel to obtain the detail signal in both directions of the pixel.

Preferably, the buffer is a multi-granular discrete memory structure.

Preferably, the filtering in the horizontal and vertical directions is specifically performing spatial convolution of the filtering template and the image data, and the filtering result is expressed as:

Where (i, j) represents the pixel point in the i-th row and j-th column position in the image data, DEH(i, j) represents the horizontal filtering result at (i, j), and DEV(i, j) represents (i , j) vertical filtering results, P (i, j) represents the pixel gray level at the i-th row and j-th column position of the image, FH (k) represents the k-th element of the horizontal template, and FV (t) represents the vertical template t elements.

Preferably, the overshoot suppression in step 4 is to separately process the horizontal detail signal and the vertical detail signal, and then add the two detail signals that have been overshoot suppressed to obtain the final detail signal by:

Step 41, using the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels of the point, the absolute difference operation is obtained, that is, the left and right sides are obtained ( NH-1)/2 and upper and lower (NV-1)/2 total four sets of grayscale absolute difference;

Step 42: Calculate the mean values of the four groups of absolute differences: Mean_L, Mean_R, Mean_T, and Mean_B, that is, the mean value of the four gray scale differences between the top and bottom of the point;

Step 43, calculating a first overshoot suppression factor alpha and a second overshoot suppression factor beta, the formula is

Alpha=ka*Y_abs_mean

Where ka is the set coefficient and Y_abs_mean is the absolute difference of the mean difference of the gray scale absolute, ie |Mean_L-Mean_R| or |Mean_T-Mean_B|, de is the detail signal strength, and kb is the set positive coefficient.

In step 44, the overshoot suppression factor s=1-alpha×beta is calculated, overcharge suppression is performed, and the detail signal de_ss=de×s after overshoot suppression is obtained.

Preferably, the detail signal strength de=de_h+de_v, where de_h is the detail signal strength in the horizontal direction and de_v is the detail signal strength in the vertical direction.

Preferably, the amplitude suppression in step 5 is as follows:

Step 51, multiplying de_ss by the detail enhancement coefficient gain to obtain an enhanced detail signal de_gain;

Step 52, and performing amplitude suppression according to the following formula, and obtaining a final detail signal de_final;

Where Th is the set threshold and Max_de is the set maximum.

Preferably, the output value after amplitude suppression in step 5 is Yout=Yin+de_final, where Yout and Yin are the pixel gradation of the output and the pixel gradation of the input, respectively.

Preferably, before the step 1, a parameter pre-loading step is further included, the parameter pre-loading step includes: loading the curing parameters in the preset horizontal and vertical filtering, nucleation filtering, overshoot suppression and amplitude suppression to the general buffer Device.

Preferably, the image data to be processed in step 1 is obtained by sequentially splitting the image data according to the pixel matrix of R*Q; the method is loaded into the buffer in step 1, and the method is:

According to the splitting order of the image data, the image data to be processed is sequentially selected and processed through steps 2 to 6, until all the image data to be processed is processed.

In another aspect of the present invention, a reconfigurable parallel image detail enhancement apparatus is further provided, comprising: a local memory, a memory access control unit, a general purpose buffer, a parallel arithmetic logic unit ALU, a state machine, and a parallel multiplication Accumulator MAC;

The local memory is configured to save input and output image data and parameters required by a parallel video image contrast enhancement algorithm, and the memory supports parallel access;

The memory access control unit is configured to exchange data between the local memory and the general buffer;

The general purpose buffer is used to buffer all data and intermediate results required for a complete processing flow, and the buffer can be directly indexed by an address;

The parallel arithmetic logic unit is configured to perform non-multiply-like arithmetic and logic operations involved in a parallel video image contrast enhancement algorithm; the degree of parallelism is N;

The state machine for generating control signals for all functional components;

The parallel multiply accumulator is configured to perform a multiplication correlation operation, and the degree of parallelism is N;

The state machine is respectively connected to the parallel arithmetic logic unit, the memory access control unit, the general buffer, and the parallel multiply accumulator through a communication line; the local memory is connected to the memory access control unit through a communication line; the universal buffer is communicated The lines are respectively connected to the memory access control unit, the parallel arithmetic logic unit, and the parallel multiply accumulator; the parallel arithmetic logic unit is connected to the parallel multiply accumulator via a communication line.

The invention has the following beneficial effects:

1. Enhance the image detail signal to make the texture area clearer;

2. Enhance the details while effectively reducing noise and overshoot;

3. It is easy to optimize and upgrade the image processing algorithm in the later stage;

4. Improve the efficiency of data usage, reduce data interaction between computing components and peripheral memory, and reduce the pressure of memory access bandwidth;

5. Reuse of hardware resources by controlling the functional components by using general-purpose buffers and state machines.

DRAWINGS

1 is a schematic structural diagram of a reconfigurable parallel image detail enhancement apparatus of the present invention;

2 is a flow chart of a parallel image detail enhancement method provided by the present invention;

3 is a schematic diagram of a buffer of a general buffer in accordance with an embodiment of the present invention;

4 is a diagram showing an example of horizontal 7th-order filtering and vertical 5th-order filtering;

FIG. 5 is a diagram showing an example of coring filtering noise reduction according to an embodiment of the present invention; FIG.

6(a) to (d) are diagrams showing an example of a scene in which an overshoot phenomenon is likely to occur;

7 is a diagram showing an example of an overshoot suppression factor alpha calculation curve in accordance with an embodiment of the present invention;

8 is a diagram showing an example of an overshoot suppression factor beta calculation curve in accordance with an embodiment of the present invention;

9 is a diagram showing an example of an overshoot suppression process in accordance with an embodiment of the present invention;

Figure 10 is an illustration of interpolation along an edge in accordance with an embodiment of the present invention.

detailed description

Preferred embodiments of the present invention are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present invention, and are not intended to limit the scope of the present invention.

A reconfigurable parallel image detail enhancement apparatus of the present invention, as shown in FIG. 1, includes a local memory, a memory access control unit, a general purpose buffer, an parallel arithmetic logic unit (ALU), a state machine, and a parallel multiply accumulator ( MAC);

The local memory is configured to save input and output image data and parameters required by a parallel video image contrast enhancement algorithm, and the memory supports parallel access;

The memory access control unit is used for data exchange between the local memory and the general buffer; in this embodiment, three memory access control units with completely identical functions are used, which breaks through the bottleneck of the memory access;

The general purpose buffer is used to buffer all data and intermediate results required for a complete processing flow, and the buffer can be directly indexed by an address;

The parallel arithmetic logic unit is configured to perform non-multiply-like arithmetic and logic operations involved in a parallel video image contrast enhancement algorithm; the degree of parallelism is N;

The state machine for generating control signals for all functional components;

The parallel multiply accumulator is configured to perform a multiplication correlation operation, and the degree of parallelism is N;

The state machine is respectively connected to the parallel arithmetic logic unit, the memory access control unit, the general buffer, and the parallel multiply accumulator through a communication line; the local memory is connected to the memory access control unit through a communication line; the universal buffer is communicated The lines are respectively connected to the memory access control unit, the parallel arithmetic logic unit, and the parallel multiply accumulator; the parallel arithmetic logic unit is connected to the parallel multiply accumulator via a communication line.

When the enhancement algorithm needs to be changed, the device only needs to reprogram the state machine, generate a new control signal, and update the algorithm parameters in the local memory to quickly implement the algorithm iteration without redesigning the manufacturing hardware circuit.

The invention also proposes a reconfigurable parallel image detail enhancement method, as shown in FIG. 2, comprising the following steps:

Step 1, data buffering: loading the image data to be processed into a buffer; the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; Split into multiple one-dimensional lattices containing N pixel points;

Step 2: filtering: performing horizontal and vertical filtering on each pixel to be enhanced in the one-dimensional lattice, and acquiring detailed signals in two directions;

Step 3, noise reduction: nucleating and filtering the detail signal in two directions, filtering out the minute detail signal introduced by the image noise;

Step 4: Overshoot suppression: the gray level symmetry on both sides of the neighborhood of the pixel to be enhanced and the detail signal strength of the pixel to be enhanced are used to control the enhanced detail signal strength, and the overshoot suppression is performed, and the overshoot is completed. The two detail signals of the suppression are added to obtain the detail signals of the N pixel points;

Step 5, amplitude suppression: further performing amplitude suppression on the detail signal obtained in step 4;

Step 6: Cache data update: by updating the data in the buffer, step 1 to step 5 of each one-dimensional lattice in the image data to be processed are sequentially processed to complete the detail enhancement of the image data to be processed.

The embodiment further includes a parameter pre-loading step before the step 1, the parameter pre-loading step includes: loading the curing parameters in the preset horizontal and vertical filtering, nucleation filtering, overshoot suppression and amplitude suppression to the general buffer. Device.

1, parameter preloading

This step belongs to the initialization phase of the apparatus of the present invention, and the curing parameters such as the filter coefficients in the horizontal and vertical directions, the thresholds used in the nucleation filtering, the overshoot suppression, and the amplitude suppression are preloaded into the general purpose buffer.

3 is a general purpose buffer in accordance with an embodiment of the present invention. As shown in FIG. 3, the general-purpose buffer (represented by a capital letter M) has a total of NM buffer units of size N pixels, and is equipped with four read ports (r0, r1, r2, r3) and four. The write port (w0, w1, w2, w3) can carry high-speed read and write operations. The general-purpose buffer M supports direct reading and writing of NM buffer units by using serial numbers, which facilitates the repeated use of data. The universal buffer used in the present invention operates in synchronization with the arithmetic unit, thereby avoiding the problem that the high-speed arithmetic unit waits for the low-speed storage unit.

2, data buffering

Obtaining a plurality of image data to be processed according to the pixel matrix of R*Q in sequence, and sequentially selecting the image data to be processed to be loaded into the buffer according to the splitting order of the image data, and adopting steps 2~Step 6 processing until all the image data to be processed is processed; the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; the pixel lattice is detachable Divided into a plurality of one-dimensional lattices containing N pixel points.

The invention provides a processing method with parallelism of N, that is equivalent to N filters working at the same time, so it is necessary to buffer the NH column N pixels or NV rows N pixels in the general buffer before performing filtering. . Meanwhile, the parallel processing apparatus and method of the present invention can be regarded as an apparatus and method for processing N-dimensional vector data, and thus the present invention will be described in detail from the viewpoint of the operation of the N-dimensional vector in the subsequent part of this document.

The algorithm of the present invention involves parallel processing of a column of pixels, that is, column access is required for the memory, and the conventional memory does not support an efficient column-by-column access mode. Therefore, the device of the present invention employs a multi-granular discrete memory. For the structure, please refer to "Patent No. 201110460585.1, the name is multi-granular parallel storage system and memory".

3, filtering

The image detail enhancement method of the invention first needs to obtain the detail signals in the horizontal and vertical directions by filtering, and specifically adopts a one-dimensional filter of horizontal NH order and vertical NV order to realize the extraction of the detail signal. In general, the higher the filter order, the stronger the extraction ability of the detail signal. Correspondingly, the negative effects such as the overshoot effect are more obvious. Considering the above two points and signal symmetry, the level 5 or 7 is usually adopted. Step, vertical filter of 3 or 5 steps to achieve the best effect, Figure 4 is a single pixel horizontal 7th order vertical 5th order filter Wave diagram. Each time a detail signal of one pixel is acquired, the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels are required.

The invention realizes the extraction of the detail signal by two horizontal and vertical one-dimensional filters, and the specific operation is to spatially convolve the filtering template and the image, and the specific description is as follows:

If the horizontal filter template is FH, the vertical filter template is FV, FH(k) is used to represent the kth element of the horizontal template, FV(t) is the tth element of the vertical template, and P(i,j) is the i-th line of the image. The pixel gray level at the j column position, the horizontal filtering result DEH(i,j) at the (i,j) pixel point and the vertical filtering result DEV(i,j) can be expressed as the formula (1), the formula (2) :

Among them, FH(0) and FV(0) correspond to the intermediate position elements of the filtering template.

The present invention employs parallel processing, so each element of the filtered template can be considered as an N-dimensional vector, and P can be regarded as the gradation of successive N pixels of the ith row or the j-th column. In addition, the vector multiplication involved in the method of the present invention is different from the mathematical outer product or inner product. In this method, the vector multiplication is to multiply the corresponding position elements of two identical dimensional vectors, and the result is still an N dimension. vector. Here, a two-dimensional vector is taken as an example for simplicity. The vector a=(a1, a2), b=(b1, b2), then the vector multiplication a*b=(a1b1, a2b2). Where a1, a2, b1, and b2 are real numbers, and a1b1 and a2b2 represent real products.

When the filtering operation is performed, the device of the present invention firstly sends the image data to be processed and the filter coefficients in the buffer in the general buffer to the register of the MAC, and the MAC has four equivalent registers of width N, To complete the N-dimensional vector multiplication and accumulation operations, the result of the multiply-accumulate operation can be returned to the general purpose buffer to facilitate being called again or directly to other computing components for subsequent processing.

4, noise reduction

The invention uses the nucleation filtering to suppress the noise contained in the extracted detail signal. The nucleation filtering principle is: the default detail signal is superimposed with a relatively small noise signal, so the detail signal is subtracted by a known nuclear filtering threshold. Smaller value, that is, no Noisy detail signal. The specific operation is to first judge the positive and negative of the detail signal and obtain the symbol flag. If the signal is positive, the flag is 1, otherwise it is -1; then the absolute value of the detail signal is taken, and the absolute value is subtracted The nucleation filter threshold, for non-positive results, is all considered to be 0; finally, the subtraction result is multiplied by the sign bit to obtain a noise reduction result. Figure 5 is a schematic diagram of the input-output relationship of the nucleation filter.

This step involves (in comparison with zero) the absolute value, the subtraction method, the maximum value and the multiplication operation. Except for the multiplication operation, the rest of the operations are performed by the parallel arithmetic logic unit ALU. Similar to MAC, ALU also has four fully equivalent N-dimensional vector registers, which can perform arithmetic and logic operations on N data at the same time.

5, overshoot suppression

The invention controls the amplitude of the detail enhancement according to the size of the detail signal and the gray level symmetry of the corresponding pixel point neighborhood, thereby implementing overshoot suppression. In general, as shown in Figures 6(a), 6(b), 6(c), and 6(d), the overshoot phenomenon usually occurs in areas where the gradation changes greatly (that is, the details are rich) and the gray scale is asymmetrical. . Fig. 6(a) to (d) show four cases in which the horizontal direction is asymmetrical and prone to overshoot, and the vertical direction is similar.

The strategy for overshoot suppression of the present invention is to separately process the horizontal detail signal and the vertical detail signal, and then add the two detail signals that have been overshoot suppressed to obtain the final detail signal. The specific method is as follows:

Step 41, using the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels of the point, the absolute difference operation is obtained, that is, the left and right sides are obtained ( NH-1)/2 and upper and lower (NV-1)/2 total four sets of grayscale absolute difference;

Step 42: Calculate the mean values of the four groups of absolute differences: Mean_L, Mean_R, Mean_T, and Mean_B, that is, the mean value of the four gray scale differences between the top and bottom of the point;

In step 43, the first overshoot suppression factor alpha is obtained by using the curve shown in FIG. 7, as shown in formula (3).

Alpha=ka*Y_abs_mean (3)

Where ka is the set coefficient and Y_abs_mean is the absolute difference of the grayscale absolute difference mean, ie |Mean_L-Mean_R| or |Mean_T-Mean_B|.

At the same time, the second overshoot suppression factor beta related to the detail signal strength is calculated by the following formula, as shown in formula (4);

Where de is the detail signal strength and kb is the set positive coefficient. Figure 8 shows the graphical representation of the beta calculation formula.

Step 44: When the device of the present invention performs overshoot suppression, the gray value of the loaded NH column or NV row pixel may be directly obtained from the general buffer, and the two suppression factors are calculated by using the gray scale data, and according to Alpha and beta calculate the overshoot control factor s=1-alpha×beta, thereby performing overshoot suppression, and obtaining the overshoot suppression detail signal de_ss=de×s.

Since the present invention performs overshoot suppression for both directions, the final detail signals de_ss=de_ss_h+de_ss_v, de_ss_h, and de_ss_v represent the detailed signal strengths of the horizontal and vertical direction overshoot suppression, respectively. The X of de_ss_X in Fig. 9 represents h or v, that is, a detail signal in the horizontal or vertical direction.

In conjunction with the reconfigurable parallel image detail enhancement apparatus of the present invention, the specific execution flow is shown in FIG. 9, including: loading image data to the ALU; calculating grayscale absolute value difference, and outputting the result to the MAC; absolute difference accumulation, and outputting the result to the ALU; Calculate the absolute difference mean and further calculate the absolute difference of the absolute difference mean; Ka is loaded to the MAC, the alpha is calculated, and the result is retained in the MAC register; the denoised detail signals de and kb are loaded into the MAC to calculate the beta; the alpha and beta are calculated The product is output to the ALU; the overshoot control factor s=1-alpha×beta is calculated, and the result is output to the MAC; the detailed signal de_ss_X=de_X×s after the overshoot suppression is calculated, and the result is output to the MAC.

6, amplitude suppression

The details of the overshoot suppression signal may still be too strong, resulting in image over-enhancement, which affects the viewing quality. Therefore, it is also necessary to control the amplitude of the enhanced detail signal. This step is divided into two processes:

Step 51, amplifying the overshoot suppression detail signal de_ss by multiplying de_ss by the detail enhancement coefficient gain in the MAC to obtain an enhanced detail signal de_gain;

In step 52, the result is output to the ALU, and the amplitude suppression is performed according to the curve shown in FIG. 10 in the ALU, and the final detail signal de_final is obtained, as shown in the formula (5).

Where Th is the set threshold and Max_de is the set maximum.

The final output is Yout=Yin+de_final. Where Yout and Yin are the pixel gradation of the output and the pixel gradation of the input, respectively. Yout first outputs to the general purpose buffer, which is then stored by the fetch control unit into the local memory.

7, cache data update

After completing the detail enhancement of the N pixels, it is necessary to update the data of the buffer in the general buffer, read the next N data, and replace the first one of the NH or NV N-dimensional vectors in the buffer, which is physically applicable. Think of the sliding of the filter window.

By updating the data in the buffer, steps 1 to 5 of each of the one-dimensional lattices in the image data to be processed are sequentially processed to complete the detail enhancement of the image data to be processed.

The above process explains the complete processing flow of the present invention. The invention realizes the reuse of hardware resources by programming the state machine and using the general buffer design, and avoids the design of the traditional dedicated circuit scheme when running the complex algorithm. The shortcomings of long stream period and high version iteration cost.

A person skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process and related description of the device described above can refer to the corresponding process in the foregoing method embodiments, and details are not described herein again.

Those skilled in the art should appreciate that the elements and method steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, in order to clearly illustrate electronic hardware and software. Interchangeability, the composition and steps of the various examples have been generally described in terms of function in the above description. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present invention.

Heretofore, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the drawings, but it is obvious to those skilled in the art that the scope of the present invention is obviously not limited to the specific embodiments. Those skilled in the art can make equivalent changes or substitutions to the related technical features without departing from the principles of the present invention, and the technical solutions after the modifications or replacements fall within the scope of the present invention.

Claims (12)

A reconfigurable parallel image detail enhancement method, comprising the steps of: Step 1: loading the image data to be processed into a buffer; the image data to be processed is a pixel matrix of R*Q, wherein the value of R or Q is equal to the degree of parallelism N; the pixel lattice is detachable a plurality of one-dimensional lattices comprising N pixel points; Step 2: performing horizontal and vertical filtering on each pixel to be enhanced in the one-dimensional lattice to obtain detailed signals in two directions; Step 3, nucleating the detail signal in two directions, filtering out the minute detail signal introduced by the image noise; Step 4: controlling the intensity of the enhanced detail signal by performing gray scale symmetry on both sides of the neighborhood of the pixel to be enhanced and the signal intensity of the pixel to be enhanced, performing overshoot suppression, and completing two overshoot suppression The detail signals are added to obtain the detail signals of the N pixels; Step 5, further performing amplitude suppression on the detail signal obtained in step 4; Step 6: Step 1 to step 5 are performed on each one-dimensional lattice in the image data to be processed in sequence, and the detail enhancement of the image data to be processed is completed. The method of claim 1 wherein said buffer comprises NM buffer units of size N pixels; said buffer being provided with 4 read ports and 4 write ports. The method according to claim 2, wherein the filtering in the horizontal and vertical directions corresponds to a one-dimensional filter of horizontal NH order and vertical NV order, respectively calculating left and right pixel points ( The gray scale of NH-1)/2 and each of the upper and lower (NV-1)/2 pixels is combined with the gray value of the pixel to obtain the detail signal in both directions of the pixel. The method of claim 3 wherein said buffer is a multi-granular discrete memory structure. The method according to claim 4, wherein the filtering in the horizontal and vertical directions is specifically performing spatial convolution of the filtering template and the image data, and the filtering result is represented by for:

Where (i, j) represents the pixel point in the i-th row and j-th column position in the image data, DEH(i, j) represents the horizontal filtering result at (i, j), and DEV(i, j) represents (i , j) vertical filtering results, P (i, j) represents the pixel gray level at the i-th row and j-th column position of the image, FH (k) represents the k-th element of the horizontal template, and FV (t) represents the vertical template t elements. The method according to claim 5, wherein said overshoot suppression in step 4 separately processes the horizontal detail signal and the vertical detail signal, and then adds the two detail signals subjected to overshoot suppression to obtain The final detail signal, the specific method is: Step 41, using the gray value of the pixel to be processed and the gray level of each of the left and right (NH-1)/2 and the upper and lower (NV-1)/2 pixels of the point, the absolute difference operation is obtained, that is, the left and right sides are obtained ( NH-1)/2 and upper and lower (NV-1)/2 total four sets of grayscale absolute difference; Step 42: Calculate the mean values of the four groups of absolute differences: Mean_L, Mean_R, Mean_T, and Mean_B, that is, the mean value of the four gray scale differences between the top and bottom of the point; Step 43, calculating a first overshoot suppression factor alpha and a second overshoot suppression factor beta, the formula is Alpha=ka*Y_abs_mean

Where ka is the set coefficient and Y_abs_mean is the absolute difference of the mean difference of the gray scale absolute, ie |Mean_L-Mean_R| or |Mean_T-Mean_B|, de is the detail signal strength, and kb is the set positive coefficient. In step 44, the overshoot suppression factor s=1-alpha×beta is calculated, overcharge suppression is performed, and the detail signal de_ss=de×s after overshoot suppression is obtained. The method according to claim 6, characterized in that said detail signal strength de = de_h + de_v, wherein de_h is the detail signal strength in the horizontal direction and de_v is the detail signal strength in the vertical direction. The method according to claim 7, wherein said amplitude suppression in step 5 is as follows: Step 51, multiplying de_ss by the detail enhancement coefficient gain to obtain an enhanced detail signal de_gain; Step 52, and performing amplitude suppression according to the following formula, and obtaining a final detail signal de_final;

Where Th is the set threshold and Max_de is the set maximum. The method according to claim 8, wherein the output value after the amplitude suppression in step 5 is Yout=Yin+de_final, wherein Yout and Yin are respectively the output pixel gradation and the input pixel gradation. The method according to any one of claims 1 to 9, further comprising a parameter preloading step before the step 1, the parameter preloading step comprising: filtering and nucleating filtering in a preset horizontal and vertical direction. The cure parameters in overshoot suppression and amplitude suppression are loaded into the general purpose buffer. The method according to any one of claims 1 to 9, wherein the image data to be processed in step 1 is obtained by sequentially splitting the image data according to a pixel matrix of R*Q; Load into the buffer by: According to the splitting order of the image data, the image data to be processed is sequentially selected and processed through steps 2 to 6, until all the image data to be processed is processed. A reconfigurable parallel image detail enhancement device, comprising: local memory, memory access control unit, general purpose buffer, parallel arithmetic logic unit ALU, shape State machine, parallel multiply accumulator MAC; The local memory is configured to save input and output image data and parameters required by a parallel video image contrast enhancement algorithm, and the memory supports parallel access; The memory access control unit is configured to exchange data between the local memory and the general buffer; The general purpose buffer is used to buffer all data and intermediate results required for a complete processing flow, and the buffer can be directly indexed by an address; The parallel arithmetic logic unit is configured to perform non-multiply-like arithmetic and logic operations involved in a parallel video image contrast enhancement algorithm; the degree of parallelism is N; The state machine for generating control signals for all functional components; The parallel multiply accumulator is configured to perform a multiplication correlation operation, and the degree of parallelism is N; The state machine is respectively connected to the parallel arithmetic logic unit, the memory access control unit, the general buffer, and the parallel multiply accumulator through a communication line; the local memory is connected to the memory access control unit through a communication line; the universal buffer is communicated The lines are respectively connected to the memory access control unit, the parallel arithmetic logic unit, and the parallel multiply accumulator; the parallel arithmetic logic unit is connected to the parallel multiply accumulator via a communication line.

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