[go: up one dir, main page]

WO2017017771A1 - Élément photovoltaïque et son procédé de fabrication - Google Patents

Élément photovoltaïque et son procédé de fabrication Download PDF

Info

Publication number
WO2017017771A1
WO2017017771A1 PCT/JP2015/071294 JP2015071294W WO2017017771A1 WO 2017017771 A1 WO2017017771 A1 WO 2017017771A1 JP 2015071294 W JP2015071294 W JP 2015071294W WO 2017017771 A1 WO2017017771 A1 WO 2017017771A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
copper
transparent conductive
amorphous semiconductor
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2015/071294
Other languages
English (en)
Japanese (ja)
Inventor
公一 橋本
小林　英治
誠治 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Choshu Industry Co Ltd
Original Assignee
Choshu Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Choshu Industry Co Ltd filed Critical Choshu Industry Co Ltd
Priority to JP2015560461A priority Critical patent/JP6053082B1/ja
Priority to PCT/JP2015/071294 priority patent/WO2017017771A1/fr
Priority to TW105123720A priority patent/TW201719914A/zh
Publication of WO2017017771A1 publication Critical patent/WO2017017771A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photovoltaic device and a manufacturing method thereof.
  • solar cells have attracted particular attention as clean power generation means that does not generate CO 2 or other greenhouse gases, or as power generation means with high operational safety that can replace nuclear power generation.
  • a solar cell photovoltaic element
  • a cell having a layer structure in which a transparent conductive film is provided on the outer surface is widely used, and a collecting electrode for collecting generated electricity is disposed on the outer surface of the transparent conductor. ing.
  • the collector electrode disposed on the outer surface is linear, and the amount of light taken in can be increased by thinning the collector electrode.
  • a method of forming a thinned collector electrode a method of forming a collector electrode by plating using a resist film (also referred to as a mask) has been developed (see Japanese Patent Application Laid-Open No. 2010-98232).
  • a resist film also referred to as a mask
  • the silver plating electrode layer is formed by plating.
  • silver cyanide or the like is usually used as a plating solution, and it is desirable to form a plating layer made of another metal from the viewpoint of safety.
  • the present invention has been made based on the circumstances as described above, and an object of the present invention is to provide a photovoltaic device that has a small contact resistance of the collector electrode and can improve conversion efficiency by thinning the collector electrode, and a method for manufacturing the photovoltaic device. Is to provide.
  • the present invention made in order to solve the above problems has a layer structure having a transparent conductive film as at least one outer layer and generating an electromotive force by light irradiation, and a line disposed on the outer surface of the transparent conductive film And a collector layer, the collector electrode being laminated on the outer surface of the transparent conductive film, and a barrier layer containing silver, at least one of palladium and gallium, and copper, and It is characterized by having a copper layer laminated on the outer surface of this barrier layer and containing copper as a main component.
  • the barrier layer containing silver, at least one of palladium and gallium, and copper.
  • the barrier layer itself having such a composition also has a small increase in resistance due to oxidation.
  • the diffusion of the copper layer is also suppressed by this barrier layer. Therefore, according to the photovoltaic device, since the increase in resistance can be suppressed while increasing the amount of light taken in by thinning the collector electrode, the conversion efficiency can be increased.
  • the collector electrode further has a coating layer laminated on the outer surface of the copper layer.
  • a coating layer By having a coating layer, oxidation of the copper layer surface can be suppressed, and as a result, a decrease in conversion efficiency can be suppressed.
  • the coating layer contains tin as a main component.
  • the surface oxidation of the copper layer can be effectively suppressed by the coating layer containing tin as a main component.
  • tin has a high light reflectance, light reflected on the outer surface of the transparent conductive film is easily reflected again on the back surface of the coating film, and the amount of light taken up can be increased.
  • wettability during soldering can be improved.
  • the layer structure includes a p-type or n-type crystal semiconductor substrate, and a first intrinsic amorphous semiconductor layer and a p-type amorphous layer stacked on one surface side of the crystal semiconductor substrate in the following order: A semiconductor layer, and an n-layer-side intermediate layer and an n-type amorphous semiconductor layer stacked in the following order on the other surface side of the crystalline semiconductor substrate, the n-layer-side intermediate layer comprising:
  • the second intrinsic amorphous semiconductor layer or a high resistance n-type amorphous semiconductor layer having a higher resistivity than the n-type amorphous semiconductor layer is preferable.
  • the inventor improves the passivation capability of an intrinsic amorphous semiconductor layer or the like that suppresses carrier recombination by annealing, and the output of the photovoltaic device We know that the characteristics will increase.
  • the collector electrode of the photovoltaic device since the collector electrode of the photovoltaic device has the barrier layer, oxidation and diffusion of the copper layer can be suppressed even by annealing, and the increase in contact resistance of the collector electrode is small. Therefore, conversion efficiency and the like can be further increased by employing the photovoltaic element as a heterojunction element.
  • Another invention made in order to solve the above-mentioned problem is to have a transparent conductive film as at least one outermost layer, and silver, palladium, and gallium on the outer surface of the layer structure in which electromotive force is generated by light irradiation.
  • a step of laminating a metal film containing at least one kind and copper, a step of forming a resist film on a part of the outer surface of the metal film, and a plating treatment to include copper as a main component in the exposed portion of the outer surface of the metal film A step of laminating a copper layer, a step of laminating a coating layer on the outer surface of the copper layer by plating, a step of removing the resist film, and a step of removing the metal film in a region where the resist film has been removed. It is a manufacturing method of the photovoltaic device provided in this order.
  • a photovoltaic device having a high conversion efficiency can be obtained by reducing the contact resistance of the collector electrode and thinning the collector electrode.
  • a step of annealing the layer structure after the metal film removing step By performing the annealing in this manner, the performance of the heterojunction photoelectric conversion element can be improved, and the oxidation and diffusion of the copper layer are suppressed even if the annealing is performed. A conversion element can be obtained.
  • main component means a component having the highest content on a mass basis.
  • the “amorphous system” in the amorphous semiconductor layer includes not only a completely amorphous body but also a microcrystal existing in an amorphous body.
  • intrinsic in an intrinsic amorphous semiconductor layer means that impurities are not intentionally doped, and there are impurities that are originally included in the raw material or impurities that are unintentionally mixed in the manufacturing process. It also includes the meaning.
  • the contact resistance of the collector electrode is small, and the conversion efficiency can be increased by thinning the collector electrode. Moreover, according to the manufacturing method of the photovoltaic device of this invention, such a photovoltaic device can be manufactured.
  • FIG. 1 is a schematic cross-sectional view of a photovoltaic device according to an embodiment of the present invention.
  • 2A to 2F are schematic cross-sectional views showing a method for manufacturing the photovoltaic device shown in FIG.
  • FIG. 3 is a graph showing the results of contact resistance measurement in the example.
  • the photovoltaic element 10 in FIG. 1 includes a layer structure 11 that generates an electromotive force when irradiated with light.
  • the layer structure 11 includes an n-type crystal semiconductor substrate 12 and a first intrinsic amorphous semiconductor layer 13 stacked in the following order on one surface side (the upper side in FIG. 1) of the n-type crystal semiconductor substrate 12.
  • the p-type amorphous semiconductor layer 14 and the first transparent conductive film 15 and the n-layer side intermediate layer laminated in the following order on the other surface side (lower side in FIG. 1) of the n-type crystal semiconductor substrate 12 A layer 16, an n-type amorphous semiconductor layer 17, and a second transparent conductive film 18.
  • the first transparent conductive film 15 and the second transparent conductive film 18 are the outermost layers of the layer structure 11.
  • the photovoltaic element 10 has a plurality of linear shapes disposed on the outer surface (front surface and back surface) of the layer structure 11, that is, on the outer surface of the first transparent conductive film 15 and the outer surface of the second transparent conductive film 18.
  • a collector electrode 19 is provided.
  • the “outer surface” refers to the surface opposite to the n-type crystal semiconductor substrate 12 with the n-type crystal semiconductor substrate 12 as the center. Further, the “inner surface” refers to a surface on the n-type crystal semiconductor substrate 12 side.
  • the n-type crystal semiconductor substrate 12 is formed from an n-type crystal semiconductor.
  • An n-type crystal semiconductor is usually a crystal formed by adding a trace amount of a pentavalent element to a semiconductor such as silicon.
  • Examples of the crystal semiconductor constituting the n-type crystal semiconductor substrate 12 include SiC and SiGe in addition to silicon (Si), but silicon is preferable from the viewpoint of productivity.
  • the n-type crystal semiconductor substrate 12 may be a single crystal or a polycrystal.
  • a pyramidal fine concavo-convex structure is formed on both surfaces of the n-type crystal semiconductor substrate 12.
  • the height and size of the uneven structure may be uneven, and adjacent uneven parts may overlap.
  • a vertex and a trough part may be roundish.
  • the height of the unevenness is about several ⁇ m to several tens of ⁇ m.
  • Such a concavo-convex structure can be obtained, for example, by immersing the substrate material in an etching solution containing about 1 to 5% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
  • the average thickness of the n-type crystal semiconductor substrate 12 is not particularly limited.
  • the upper limit of the average thickness is, for example, 300 ⁇ m, and preferably 200 ⁇ m. Moreover, as this minimum, it can be set as 50 micrometers, for example.
  • the first intrinsic amorphous semiconductor layer 13 is a layer interposed between the n-type crystal semiconductor substrate 12 and the p-type amorphous semiconductor layer 14 and functions as a passivation layer that suppresses carrier recombination. It is a layer to do.
  • the first intrinsic amorphous semiconductor layer 13 is usually made of silicon. With such an intrinsic amorphous semiconductor layer, carrier recombination can be suppressed and output characteristics can be improved.
  • the average thickness of the first intrinsic amorphous semiconductor layer 13 can be, for example, 1 nm or more and 10 nm or less.
  • the p-type amorphous semiconductor layer 14 is usually an amorphous layer obtained by adding a small amount of a trivalent element to silicon.
  • the average thickness of the p-type amorphous semiconductor layer 14 can be, for example, 1 nm or more and 20 nm or less.
  • the n-layer-side intermediate layer 16 is a layer interposed between the n-type crystal semiconductor substrate 12 and the n-type amorphous semiconductor layer 17 and functions as a passivation layer that suppresses carrier recombination.
  • the n-layer side intermediate layer 16 is a second intrinsic amorphous semiconductor layer or a high-resistance n-type amorphous semiconductor layer having a higher resistivity than the n-type amorphous semiconductor layer 17.
  • this layer is usually made of silicon.
  • the n-layer side intermediate layer 16 is a high-resistance n-type amorphous semiconductor layer, it is usually an amorphous layer obtained by adding a trace amount of a pentavalent element to silicon.
  • the high-resistance n-type amorphous semiconductor layer has a higher resistance than the n-type amorphous semiconductor layer 17 because the addition amount of the pentavalent element (dopant amount) is smaller.
  • an n-layer side intermediate layer 16 intrinsic amorphous semiconductor layer or high resistance n-type amorphous semiconductor layer
  • carrier recombination can be suppressed and output characteristics can be improved.
  • middle layer 16 it is 1 nm or more and 10 nm or less, for example.
  • the n-type amorphous semiconductor layer 17 is usually an amorphous layer obtained by adding a trace amount of a pentavalent element to silicon.
  • the average thickness of the n-type amorphous semiconductor layer 17 can be, for example, 1 nm or more and 20 nm or less.
  • the transparent conductive material constituting the first transparent conductive film 15 and the second transparent conductive film 18 examples include indium tin oxide (ITO), indium tungsten oxide (IWO), and indium cerium oxide (ICO). Can be mentioned. Although it does not restrict
  • Each collector electrode 19 is a layer structure having a barrier layer 20, a copper layer 21, and a coating layer 22.
  • the barrier layer 20 is laminated on the outer surface of the transparent conductive film (the first transparent conductive film 15 and the second transparent conductive film 18).
  • the barrier layer 20 contains silver (Ag), at least one of palladium (Pd) and gallium (Ga), and copper (Cu).
  • the barrier layer 20 containing such a component exhibits a good barrier property between the copper layer 21 and the first transparent conductive film 15 or the second transparent conductive film 18, Oxidation due to the contact of can be suppressed.
  • the barrier layer 20 itself having such a composition has a small increase in resistance due to oxidation.
  • the barrier layer 20 can also suppress the diffusion of copper forming the copper layer 21. Furthermore, by forming the barrier layer 20 from such components, the copper layer 21 can be efficiently laminated on the barrier layer 20 by plating or the like.
  • the barrier layer 20 is preferably made of an Ag—Pd—Cu-based or Ag—Ga—Cu-based silver alloy containing Ag as a main component and added with at least one of Pd and Ga and Cu.
  • the barrier layer 20 may contain both Pd and Ga, and the total content of Pd and Ga can be, for example, 0.2 atomic% or more and 5 atomic% or less.
  • the barrier layer 20 As content of Cu in the barrier layer 20, it is 0.1 atomic% or more and 5 atomic% or less, for example.
  • the barrier layer 20 can function more favorably as the barrier layer of the copper layer 21.
  • the barrier layer 20 may contain other components as long as the effects of the present invention are not impaired.
  • the average thickness of the barrier layer 20 is not particularly limited, but the lower limit is preferably, for example, 10 nm, more preferably 20 nm, and further preferably 30 nm.
  • the upper limit is preferably 300 nm, more preferably 150 nm, and even more preferably 100 nm.
  • productivity is reduced, for example, it is not easy to remove unnecessary portions (etch back) in the manufacturing process.
  • the copper layer 21 is laminated on the outer surface of the barrier layer 20.
  • the copper layer 21 contains copper (Cu) as a main component.
  • Cu copper
  • average thickness of the copper layer 21 Although it does not specifically limit as average thickness of the copper layer 21, For example, they are 1 micrometer or more and 50 micrometers or less. When the average thickness of the copper layer 21 is less than the above lower limit, sufficient conductivity, current collection, and the like may not be exhibited. On the other hand, when the average thickness of the copper layer 21 exceeds the above upper limit, there is a possibility that the cost is high and the productivity is lowered.
  • the covering layer 22 is preferably laminated on the outer surface of the copper layer 21.
  • the coating layer 22 can prevent the surface of the copper layer 21 from being oxidized.
  • the covering layer 22 is usually made of metal. Although it does not specifically limit as a metal which forms the coating layer 22, It is preferable that the coating layer 22 contains tin (Sn) as a main component. Since Sn has a high light reflectivity, for example, light reflected on the outer surface of the first transparent conductive film 15 is easily reflected again on the back surface (inner surface) of the coating film 22, and the amount of light taken in can be increased. Further, by using Sn for the coating layer 22, the wettability of the solder can be improved.
  • Sn in coating layer 22 As a minimum of content of Sn in coating layer 22, it is 80 mass%, for example, 95 mass% is preferred and 99 mass% is more preferred. This upper limit may be 100% by weight. However, the coating layer 22 may contain other components other than Sn as long as the effects of the present invention are not impaired.
  • average thickness of the coating layer 22 Although it does not specifically limit as average thickness of the coating layer 22, For example, they are 0.5 micrometer or more and 5 micrometers or less. When the average thickness of the coating layer 22 is less than the lower limit, a sufficient function may not be exhibited. On the contrary, when the average thickness of the coating layer 22 exceeds the upper limit, there is a possibility that the cost is increased and the productivity is lowered.
  • the plurality of linear collector electrodes 19 are arranged in parallel to each other.
  • the lower limit of the line width of the collector electrode 19 is preferably 5 ⁇ m, for example, and more preferably 10 ⁇ m.
  • the upper limit of the line width is preferably 100 ⁇ m, for example, and more preferably 50 ⁇ m.
  • the pitch of the collector electrodes 19 (the distance between the centers of the adjacent collector electrodes 19) is not particularly limited, but the lower limit is preferably 0.5 mm and more preferably 1 mm. On the other hand, as this upper limit, 10 mm is preferable and 5 mm is more preferable. By setting the pitch of the collector electrodes 19 within the above range, it is possible to secure current collecting properties while increasing the amount of light taken in.
  • the light incident surface may be on the first transparent conductive film 15 side or the second transparent conductive film 18 side. It may be used to receive light from both sides.
  • the photovoltaic elements 10 are usually used by connecting a plurality thereof in series. By using a plurality of photovoltaic elements 10 connected in series, the generated voltage can be increased.
  • the method for manufacturing the photovoltaic device 10 includes a step of obtaining the layer structure 11 and a step of forming the collector electrode 19.
  • the layer structure 11 can be obtained by a known method. Specifically, a step of laminating the first intrinsic amorphous semiconductor layer 13 on one surface side of the n-type crystal semiconductor substrate 12, and p A step of laminating the type amorphous semiconductor layer 14, a step of laminating the first transparent conductive film 15, a step of laminating the n-layer side intermediate layer 16 on the other surface side of the n-type crystal semiconductor substrate 12, and a step of laminating the n-type amorphous semiconductor layer 17 and a step of laminating the second transparent conductive film 18.
  • the order of the steps is not particularly limited as long as the order in which the layer structure of the layer structure 11 can be obtained.
  • Examples of a method for stacking the first intrinsic amorphous semiconductor layer 13 and the n-layer side intermediate layer 16 as the intrinsic amorphous semiconductor layer include known methods such as chemical vapor deposition.
  • Examples of chemical vapor deposition include plasma CVD and catalytic CVD (also called hot wire CVD).
  • a mixed gas of SiH 4 and H 2 can be used as the source gas.
  • the p-type amorphous semiconductor layer 14 and the n-type amorphous semiconductor layer 17 are stacked by a known method such as chemical vapor deposition similar to the stacking of the intrinsic amorphous semiconductor layer. A film can be formed.
  • a mixed gas of SiH 4 , H 2, and B 2 H 6 can be used as the source gas.
  • a mixed gas of SiH 4 , H 2, and PH 3 can be used in the n-type amorphous semiconductor layer 17, for example.
  • the n-layer side intermediate layer 16 as the high-resistance n-type amorphous semiconductor layer can also be formed by a known method such as chemical vapor deposition.
  • the high resistance n-type amorphous semiconductor layer can be formed by reducing the amount of dopant compared to the n-type amorphous semiconductor layer 17.
  • a high resistance n is obtained by forming a film with an introduction amount of PH 3 as a dopant based on SiH 4 being 1000 ppm or less.
  • Type amorphous semiconductor layers can be obtained.
  • the amount (concentration) of PH 3 introduced when the high resistance n-type amorphous semiconductor layer is formed is the amount introduced (concentration) when the n-type amorphous semiconductor layer 17 is formed. 1/100 or more and 1/5 or less.
  • Examples of the method for laminating the first transparent conductive film 15 and the second transparent conductive film 18 include a sputtering method, a vacuum deposition method, an ion plating method (reactive plasma deposition method), and the like. And the ion plating method are preferred.
  • the sputtering method is excellent in film thickness controllability and the like, and can be performed at a lower cost than the ion plating method.
  • the ion plating method it is possible to perform film formation while suppressing generation of defects.
  • the collector electrode 19 can be formed, for example, by performing the following steps (a) to (f) in this order.
  • Step (a) of laminating a metal film containing silver, at least one of palladium and gallium, and copper on the outer surface of the layer structure 11 Forming a resist film on a part of the outer surface of the metal film (b); Step (c) of laminating a copper layer containing copper as a main component on the exposed portion of the outer surface of the metal film by plating. Step (d) of laminating a coating layer on the outer surface of the copper layer by plating. Removing the resist film (e) Step (f) of removing the metal film in the region where the resist film has been removed;
  • each step will be described with reference to FIG.
  • a metal film 30 containing silver, at least one of palladium and gallium, and copper is laminated on the outer surface of the layer structure 11 (see FIG. 2A).
  • the outermost layer of the layer structure 11 is the first transparent conductive film 15 or the second transparent conductive film 18 (not shown in FIG. 2).
  • the metal film 30 becomes the barrier layer 20 of the photovoltaic device 10 of FIG.
  • the method for laminating the metal film 30 is not particularly limited, but it can be suitably laminated by sputtering. This sputtering can be performed using a sputtering target made of the composition of the barrier layer 20. Alternatively, a sputtering target of each element constituting the barrier layer 20 may be used, and the film may be formed by simultaneously controlling the discharge amount and performing sputtering.
  • a resist film 31 is formed on a part of the outer surface of the metal film 30 (see FIG. 2B).
  • the resist film 31 is also referred to as a mask, a plating resist, or the like, and a portion where the resist film 31 is not stacked is a portion where the collector electrode 19 is formed.
  • the resist film 31 can be formed by, for example, ink jet printing.
  • the material for forming the resist film 31 is not particularly limited, and a commonly used inorganic material or organic material can be used. As the resist material, it is preferable to use paraffin wax when the resist film 31 is formed by ink jet printing.
  • the resist film 31 When the heated molten paraffin wax is printed on the surface of the metal film 30 by ink jet printing, the paraffin wax is cured on the surface of the metal film after printing. As a result, the resist film 31 having a steep side surface can be efficiently formed. Further, the resist film 31 formed of paraffin wax can be easily removed. Note that the resist film 31 may be formed of other materials such as a photoresist material.
  • step (c) a copper layer 21 containing copper as a main component is laminated on the exposed portion of the outer surface of the metal film 30 by plating (see FIG. 2C).
  • This copper plating can be performed by a known method such as a sulfate bath.
  • Step (d) In the step (d), a coating layer 22 is laminated on the outer surface of the copper layer 21 by plating (see FIG. 2D).
  • This plating treatment can be performed by a known method. For example, when tin plating is performed, it can be performed by a sulfate bath or the like.
  • step (e) the resist film 31 is removed (see FIG. 2E).
  • the removal of the resist film 31 can be performed using an acid solution, an alkaline solution, or the like.
  • the resist film 31 can be efficiently removed with, for example, an aqueous potassium hydroxide solution.
  • concentration of this aqueous potassium hydroxide solution is, for example, about 1% by mass to 5% by mass.
  • Step (f) In the step (f), the metal film 30 in a region where the resist film 31 is removed, that is, a region where the copper layer 21 is not laminated is removed (etched back) (see FIG. 2F). Thereby, the collector electrode 19 is formed.
  • the removal of the metal film 30 can be performed with an etching solution that can dissolve the metal film 30.
  • an etchant include a phosphoric acid aqueous solution.
  • the phosphoric acid content is 50% by mass or more and 70% or less
  • the nitric acid content is 0.1% by mass or more and 9.9% by mass or less
  • the acetic acid content is 10% by mass or more.
  • An aqueous solution having a content of 30% by mass or less and an ammonium fluoride content of 0.1% by mass to 2.0% by mass is preferable.
  • the collector electrode 19 shown in FIG. 2F obtained by such a process has a shape in which the upper surface is slightly wider than the bottom surface and the side surface is slightly curved in a concave shape.
  • the light reflected by the outer surface of the transparent conductive film is reflected again by the side surface of the collector electrode 19 or the like, and easily enters the transparent conductive film. As a result, the amount of light taken in can be increased.
  • the manufacturing method further includes a step of annealing the layer structure 11 after removing the metal film 30 in the region where the copper layer 21 is not laminated.
  • a step of annealing the passivation ability of the first intrinsic amorphous semiconductor layer 13 and the like can be improved, and the output characteristics of the heterojunction photoelectric conversion element can be improved.
  • the collector electrode 19 is also annealed. However, even if this annealing is performed, oxidation and diffusion of the copper layer 21 are suppressed by the barrier layer 20, so that the resistance does not increase greatly and power generation A photoelectric conversion element having excellent efficiency can be obtained.
  • the conditions for the annealing treatment are not particularly limited.
  • the treatment temperature may be 150 ° C. or higher and 250 ° C. or lower.
  • the processing time can be 10 minutes or more and 1 hour or less.
  • the collector electrode on the back side of the collector electrodes on both sides may be formed of a metal or the like laminated on the entire surface.
  • a metal silver, an Ag—Pd—Cu alloy, an Ag—Ga—Cu alloy, or the like can be preferably used.
  • a p-type crystal semiconductor substrate may be used.
  • a transparent conductive film may be formed at least on the incident surface side, and the transparent conductive film may not be formed on the back surface side.
  • generation of defect levels can be suppressed and conversion efficiency can be increased.
  • Example 1 First transparent conductive film / p-type amorphous silicon layer / first intrinsic amorphous silicon layer / n-type crystalline silicon substrate / second intrinsic amorphous silicon layer (n-layer side intermediate layer) A layer structure composed of / n-type amorphous silicon layer / second transparent conductive film was prepared.
  • n-type crystal silicon substrate a single crystal substrate having a fine concavo-convex structure (texture structure) having innumerable pyramid shapes on both surfaces was used. This concavo-convex structure was formed by immersing the substrate material in an etching solution containing about 3% by mass of sodium hydroxide and anisotropically etching the (100) plane of the substrate material.
  • Each silicon layer was laminated by a plasma CVD method.
  • Each transparent conductive film was laminated by sputtering using indium oxide containing 3% by mass of tin oxide (a sputtering target of Umicore).
  • the p-type amorphous silicon layer, the first intrinsic amorphous silicon layer, the n-type crystalline silicon substrate, the second intrinsic amorphous silicon layer, and the n-type amorphous silicon layer are respectively It corresponds to a p-type amorphous semiconductor layer, a first intrinsic amorphous semiconductor layer, an n-type crystal semiconductor substrate, a second intrinsic amorphous semiconductor layer, and an n-type amorphous semiconductor layer.
  • a plurality of linear collector electrodes (line width 30 ⁇ m, pitch 2 mm) were formed on the outer surfaces of the first transparent conductive film and the second transparent conductive film by the following method.
  • an Ag—Pd—Cu-based metal film having an average thickness of 50 nm was formed on both surfaces of the layer structure by sputtering using an APC-TR target manufactured by Furuya Metal Co., Ltd.
  • a resist film for plating was formed on the metal film by ink jet printing.
  • a copper plating layer having an average thickness of about 4 ⁇ m was formed on the exposed metal film by plating.
  • a tin plating layer having an average thickness of about 1 ⁇ m was formed on the copper plating layer by plating.
  • the paraffin wax which is a resist film was removed by immersing in a 3 mass% potassium hydroxide solution at 25 ° C. for 1 minute.
  • the exposed metal film was removed by dipping in a phosphoric acid aqueous solution for 10 seconds. Thereafter, annealing was performed at 200 ° C. for 30 minutes. Thereby, the photovoltaic device of Example 1 was obtained.
  • Example 2 Using an AGC target (Ag: 97.0 to 99.7% by mass, Ga: 0.2 to 1.5% by mass, Cu: 0.1 to 1.5% by mass) by sputtering on both sides of the layer structure A photovoltaic device of Example 2 was obtained in the same manner as Example 1 except that an Ag—Ga—Cu-based metal film having an average thickness of 50 nm was formed.
  • AGC target Al: 97.0 to 99.7% by mass, Ga: 0.2 to 1.5% by mass, Cu: 0.1 to 1.5% by mass
  • Comparative Example 1 A photovoltaic device of Comparative Example 1 was obtained in the same manner as Example 1 except that the collector electrode (line width 80 ⁇ m, pitch 2 mm) was formed by screen printing using a silver paste.
  • Comparative Example 2 A photovoltaic device of Comparative Example 1 was obtained in the same manner as in Example 1 except that the collector electrode (line width: 30 ⁇ m, pitch: 2 mm) was formed by screen printing using a silver paste.
  • Example 1 As shown in Table 1, it can be seen that the photovoltaic elements of Example 1 and Example 2 have a large curve factor and excellent conversion efficiency.
  • test film (average thickness 50 nm) was formed on the surface of the transparent conductive film made of indium oxide containing 3% by mass of tin oxide by sputtering, and then annealed (200 ° C., 30 minutes). The contact resistivity of each test film before and after annealing was measured. The measurement results are shown in FIG.
  • the test films 1 and 2 (Ag—Pd—Cu alloy film) were formed using the APC-TR target used in Example 1.
  • Test films 3 and 4 (Ag—Ga—Cu alloy films) were formed using the AGC target used in Example 2.
  • Test film 1 Ag—Pd—Cu alloy (before annealing)
  • Test film 2 Ag—Pd—Cu alloy (after annealing)
  • Test film 3 Ag—Ga—Cu alloy (before annealing)
  • Test film 4 Ag—Ga—Cu alloy (after annealing)
  • Test film 5 Al—Ni alloy (before annealing)
  • Test film 6 Al—Ni alloy (after annealing)
  • Test film 8 Mo (after annealing) All annealing treatments were performed at 200 ° C. for 30 minutes.
  • an Al—Ni alloy generally used as a barrier metal has a high resistance (test film 5), and the resistance is further increased by annealing treatment (test film 6). ).
  • Mo is used (test films 7 and 8)
  • the resistance is lower than that of the Al—Ni alloy, but it is difficult to deposit a copper layer on the Mo by plating.
  • the photovoltaic device of the present invention can increase the conversion efficiency and can be suitably used for photovoltaic power generation.
  • Photoelectric power generation element 11
  • Layer structure 12 N-type crystalline semiconductor substrate 13 1st intrinsic amorphous semiconductor layer 14 p-type amorphous semiconductor layer 15 1st transparent conductive film 16 n layer side intermediate
  • Collector electrode 20 Barrier layer 21 Copper layer 22 Coating layer 30
  • Metal film 31 Resist film

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne : un élément photovoltaïque qui présente une faible résistance de contact dans une électrode de collecte, et qui peut augmenter le rendement de conversion étant donné que l'électrode de collecte est formée avec des fils minces ; et un procédé de fabrication de l'élément photovoltaïque. L'élément photovoltaïque est pourvu : d'un corps structural en couches qui comporte un film conducteur transparent au moins comme couche la plus à l'extérieur d'un côté et qui génère une force électromotrice par exposition à un rayonnement lumineux ; et d'une électrode de collecte linéaire agencée sur la surface extérieure du film conducteur transparent. L'électrode de collecte est caractérisée en ce qu'elle comprend : une couche barrière qui est stratifiée sur la surface extérieure du film conducteur transparent et qui contient de l'argent, du cuivre, et du palladium et/ou du gallium ; et une couche de cuivre qui est stratifiée sur la surface extérieure de la couche barrière et dont l'ingrédient principal est le cuivre. De préférence, le corps structural en couches comprend en outre : un substrat semi-conducteur cristallin du type p ou du type n ; une première couche de semi-conducteur véritablement amorphe et une couche de semi-conducteur amorphe du type p qui sont stratifiées dans cet ordre sur un côté de surface du substrat semi-conducteur cristallin ; et une couche intermédiaire côté couche n et une couche de semi-conducteur amorphe du type n qui sont stratifiées dans cet ordre sur l'autre côté de surface du substrat semi-conducteur cristallin.
PCT/JP2015/071294 2015-07-27 2015-07-27 Élément photovoltaïque et son procédé de fabrication Ceased WO2017017771A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015560461A JP6053082B1 (ja) 2015-07-27 2015-07-27 光発電素子及びその製造方法
PCT/JP2015/071294 WO2017017771A1 (fr) 2015-07-27 2015-07-27 Élément photovoltaïque et son procédé de fabrication
TW105123720A TW201719914A (zh) 2015-07-27 2016-07-27 光發電元件及其製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/071294 WO2017017771A1 (fr) 2015-07-27 2015-07-27 Élément photovoltaïque et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2017017771A1 true WO2017017771A1 (fr) 2017-02-02

Family

ID=57582224

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/071294 Ceased WO2017017771A1 (fr) 2015-07-27 2015-07-27 Élément photovoltaïque et son procédé de fabrication

Country Status (3)

Country Link
JP (1) JP6053082B1 (fr)
TW (1) TW201719914A (fr)
WO (1) WO2017017771A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563345A (zh) * 2020-12-09 2021-03-26 西安交通大学 一种匀化平面型光导开关电场的外导体电极结构及光导开关器件和方法
JPWO2023157935A1 (fr) * 2022-02-16 2023-08-24

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117202A (ja) * 1997-06-26 1999-01-22 Kyocera Corp 太陽電池素子
JP2003297158A (ja) * 2002-04-01 2003-10-17 Canon Inc グリッド電極を有する透明導電膜及びその製造方法
JP2006295197A (ja) * 2005-04-14 2006-10-26 E I Du Pont De Nemours & Co 導電性厚膜組成物、それから形成される電極および太陽電池
WO2012001857A1 (fr) * 2010-06-21 2012-01-05 三菱電機株式会社 Dispositif photovoltaïque
JP2014241392A (ja) * 2012-10-02 2014-12-25 株式会社カネカ 結晶シリコン太陽電池の製造方法、太陽電池モジュールの製造方法、結晶シリコン太陽電池並びに太陽電池モジュール

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2992464B2 (ja) * 1994-11-04 1999-12-20 キヤノン株式会社 集電電極用被覆ワイヤ、該集電電極用被覆ワイヤを用いた光起電力素子及びその製造方法
JP4078589B2 (ja) * 2002-07-23 2008-04-23 富士電機ホールディングス株式会社 太陽電池モジュールとその製造方法
JPWO2011132707A1 (ja) * 2010-04-20 2013-07-18 京セラ株式会社 太陽電池素子およびそれを用いた太陽電池モジュール

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1117202A (ja) * 1997-06-26 1999-01-22 Kyocera Corp 太陽電池素子
JP2003297158A (ja) * 2002-04-01 2003-10-17 Canon Inc グリッド電極を有する透明導電膜及びその製造方法
JP2006295197A (ja) * 2005-04-14 2006-10-26 E I Du Pont De Nemours & Co 導電性厚膜組成物、それから形成される電極および太陽電池
WO2012001857A1 (fr) * 2010-06-21 2012-01-05 三菱電機株式会社 Dispositif photovoltaïque
JP2014241392A (ja) * 2012-10-02 2014-12-25 株式会社カネカ 結晶シリコン太陽電池の製造方法、太陽電池モジュールの製造方法、結晶シリコン太陽電池並びに太陽電池モジュール

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563345A (zh) * 2020-12-09 2021-03-26 西安交通大学 一种匀化平面型光导开关电场的外导体电极结构及光导开关器件和方法
JPWO2023157935A1 (fr) * 2022-02-16 2023-08-24
WO2023157935A1 (fr) * 2022-02-16 2023-08-24 株式会社マテリアル・コンセプト Photopile

Also Published As

Publication number Publication date
JP6053082B1 (ja) 2016-12-27
TW201719914A (zh) 2017-06-01
JPWO2017017771A1 (ja) 2017-07-27

Similar Documents

Publication Publication Date Title
JP5019397B2 (ja) 太陽電池およびその製造方法
US10090428B2 (en) Solar cell and method for manufacturing the same
US20160197207A1 (en) Solar cell, solar cell module, and manufacturing method of solar cell
JP5174635B2 (ja) 太陽電池素子
JP2011238903A (ja) 太陽電池格子構造およびその製造方法
WO2017002927A1 (fr) Batterie solaire et module de batterie solaire
WO2010119512A1 (fr) Dispositif photovoltaïque et son procédé de fabrication
TWI761662B (zh) 太陽能電池之製造方法
JP2010123859A (ja) 太陽電池素子および太陽電池素子の製造方法
CN107210331A (zh) 太阳能电池及其制造方法
WO2014189058A1 (fr) Pile solaire, module de pile solaire et leurs procédés de fabrication respectifs
JP2012204660A (ja) 光起電力装置およびその製造方法、光起電力モジュール
JPWO2019163647A1 (ja) 太陽電池の製造方法
JP6053082B1 (ja) 光発電素子及びその製造方法
JP2018041753A (ja) 光発電素子及びその製造方法
WO2019138613A1 (fr) Procédé de fabrication d'une cellule solaire
JP6502147B2 (ja) 太陽電池の製造方法および太陽電池モジュールの製造方法
JP5987127B1 (ja) 光発電素子及びその製造方法
JPWO2019163648A1 (ja) 太陽電池の製造方法
JP2018190819A (ja) 光発電素子及びその製造方法
JP6143520B2 (ja) 結晶シリコン系太陽電池およびその製造方法
JP5971499B2 (ja) 太陽電池及びその製造方法
JP7237920B2 (ja) 太陽電池の製造方法
JP2018041787A (ja) 光発電素子の製造方法
WO2020022044A1 (fr) Procédé de fabrication de cellule solaire

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2015560461

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15899604

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15899604

Country of ref document: EP

Kind code of ref document: A1