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WO2017010029A1 - Dispositif de conversion photoélectrique - Google Patents

Dispositif de conversion photoélectrique Download PDF

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Publication number
WO2017010029A1
WO2017010029A1 PCT/JP2016/002259 JP2016002259W WO2017010029A1 WO 2017010029 A1 WO2017010029 A1 WO 2017010029A1 JP 2016002259 W JP2016002259 W JP 2016002259W WO 2017010029 A1 WO2017010029 A1 WO 2017010029A1
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Prior art keywords
photoelectric conversion
semiconductor layer
semiconductor substrate
amorphous semiconductor
region
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PCT/JP2016/002259
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English (en)
Japanese (ja)
Inventor
伸 難波
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Panasonic Intellectual Property Management Co Ltd
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Panasonic Intellectual Property Management Co Ltd
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Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/70—Surface textures, e.g. pyramid structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a photoelectric conversion device.
  • a photoelectric conversion device for solar cells expected as a new energy source, a photoelectric conversion device in which a semiconductor thin film such as amorphous or microcrystal is laminated on a semiconductor substrate is used.
  • the photoelectric conversion device converts incident sunlight into photoelectric carriers.
  • the present invention is to provide a photoelectric conversion device with improved conversion efficiency.
  • One embodiment of a photoelectric conversion device includes a first conductivity type semiconductor substrate, a second conductivity type first amorphous semiconductor layer formed on the semiconductor substrate, and a first amorphous semiconductor. And a first crystal in contact with both the semiconductor substrate and the first surface electrode in the first amorphous semiconductor layer. Provide an area.
  • a photoelectric conversion device with improved conversion efficiency can be provided.
  • FIG. 1 is a diagram illustrating a schematic configuration of a photoelectric conversion apparatus 100 according to the embodiment.
  • FIG. 2 is an enlarged view of a broken line portion of FIG.
  • FIG. 3 is a flowchart showing a manufacturing process of the photoelectric conversion device 100 according to the embodiment.
  • FIG. 4A is a top view of the surface of the semiconductor substrate 10 after Step 1 is finished.
  • FIG. 4B is a cross-sectional view of the surface of the semiconductor substrate 10 after Step 1 is finished.
  • FIG. 5 is a cross-sectional view of the surface of the semiconductor substrate 10 before and after performing step 2.
  • FIG. 6 is an enlarged view on the p side in the cross-sectional view of the structure according to the present embodiment after step 4 has been completed.
  • FIG. 7 is an enlarged view of a broken line portion in FIG.
  • FIG. 1 is a diagram illustrating a schematic configuration of a photoelectric conversion apparatus 100 according to an embodiment.
  • the photoelectric conversion device 100 includes an n-type semiconductor substrate 10, a p-side photoelectric conversion region 20 formed on the first main surface of the semiconductor substrate 10, and the first main substrate of the semiconductor substrate 10.
  • a grid electrode 40 formed on the surface electrode 30.
  • FIG. 2 is an enlarged view of a broken line portion of FIG.
  • the material used for the semiconductor substrate 10 may be a material used for a general semiconductor element.
  • an n-type single crystal silicon substrate is used as the first conductivity type semiconductor substrate 10.
  • an uneven shape 60 is formed on the surface of the semiconductor substrate 10.
  • the p-side photoelectric conversion region 20 formed on the first main surface of the semiconductor substrate 10 may be a single layer or may be formed by stacking a plurality of amorphous semiconductor layers having different compositions.
  • a p-type amorphous semiconductor layer 20p is stacked on a substantially intrinsic i-type amorphous semiconductor layer 20i, and the p-side photoelectric conversion region 20 is formed by the two layers.
  • the n-side photoelectric conversion region 22 formed on the second main surface of the semiconductor substrate 10 may be a single layer, or a plurality of amorphous semiconductor layers having different compositions may be stacked.
  • an n-type amorphous semiconductor layer 22n is stacked on a substantially intrinsic i-type amorphous semiconductor layer 22i, and the n-side photoelectric conversion region 22 is formed by the two layers.
  • a surface electrode 30 made of a transparent conductive oxide film layer is provided on the p-side photoelectric conversion region 20 and the n-side photoelectric conversion region 22, a surface electrode 30 made of a transparent conductive oxide film layer is provided.
  • the grid electrode 40 formed by applying and sintering a resin paste in which conductive particles are dispersed is formed.
  • the photoelectric conversion device 100 is formed in the p-side photoelectric conversion region 20 at the same time as the p-side photoelectric conversion region 20 and has a crystalline region 50 (having higher conductivity than the p-side photoelectric conversion region 20). (Described later).
  • FIG. 3 is a flowchart showing manufacturing steps of the photoelectric conversion device 100 according to this embodiment. Hereinafter, each process will be described in detail.
  • Step 1 Preparation of crystalline silicon substrate having uneven surface
  • a semiconductor substrate 10 made of n-type single crystal silicon having a plane orientation [100] is prepared. After removing the contamination of the surface of the semiconductor substrate 10 by various cleanings, an uneven shape 60 constituted by quadrangular pyramids arranged two-dimensionally is formed on the surface.
  • the semiconductor substrate 10 is immersed in an alkaline aqueous solution containing at least one of sodium hydroxide (NaOH), potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH) for a predetermined time.
  • concentration of the alkaline aqueous solution is about 0.1 to 10% by weight, and the temperature during immersion is not particularly limited.
  • the surface of the semiconductor substrate 10 made of single crystal silicon is anisotropically etched, and the concavo-convex shape 60 is formed.
  • FIG. 4A is a top view of the surface side of the semiconductor substrate 10 after Step 1 is finished.
  • FIG. 4B is a cross-sectional view of the front surface side of the semiconductor substrate 10 after Step 1 is finished. More specifically, FIG. 4A shows a state where a large number of uneven shapes 60 made of uniform quadrangular pyramids are formed on the surface of the semiconductor substrate 10 by anisotropic etching.
  • 4B is a cross-sectional view taken along the line IVB-IVB in FIG. 4A.
  • the back side of the semiconductor substrate 10 has a similar shape. In this concavo-convex shape, the slope 70 of the quadrangular pyramid is the (111) plane among the crystal planes of single crystal silicon.
  • the height of the quadrangular pyramids constituting the uneven shape 60 is, for example, about 1 to 10 ⁇ m, and the distance between adjacent quadrangular pyramids, that is, the distance between the apexes of the quadrangular pyramids is, for example, about 1 to 10 ⁇ m.
  • a portion between adjacent quadrangular pyramids is referred to as a valley portion 80a.
  • Step 2 Post-processing of the semiconductor substrate 10
  • An isotropic etching process is performed on the semiconductor substrate 10 on which the concavo-convex shape 60 is formed by wet etching using a chemical etching solution.
  • FIG. 5 is a cross-sectional view of the surface of the semiconductor substrate 10 before and after performing step 2.
  • the sharp valley portion 80a becomes a valley portion 80b having an arc shape or a flat shape.
  • a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO 3 ) is used as the chemical etching solution.
  • the method of isotropic etching is not limited to this, and dry etching using a mixed gas of tetrafluoromethane (CF 4 ) and oxygen (O 2 ) may be used.
  • CF 4 tetrafluoromethane
  • O 2 oxygen
  • the width of the valley portion 80b and the curvature of the arc can be adjusted.
  • the slope portion 70 of the concavo-convex shape 60 is the (111) plane, whereas the valley portion 80b becomes a crystal plane close to (100) by isotropic etching.
  • the valley 80a changes to a shape like the valley 80b, and at the same time, the peak of the convex part may be an arc shape or a flat shape.
  • the crystal plane is close to (100).
  • Step 3 Oxidation treatment of semiconductor substrate 10
  • the semiconductor substrate 10 that has undergone the process 2 is further treated with an oxidizing chemical to form a silicon dioxide film on the surface of the semiconductor substrate 10.
  • the oxidizing chemical include ozone water and nitric acid aqueous solution, but a method of exposing to air or an ozone atmosphere may be used for simplicity.
  • the semiconductor substrate 10 after step 2 is immersed in 5% concentration ozone water for about 5 minutes.
  • the oxidation rate varies depending on the crystal orientation exposed on the surface of the semiconductor substrate 10.
  • the quadrangular pyramid slope portion 70 that is, the region having the plane orientation (111)
  • the valley portion 80b that is, the region close to the plane orientation (100)
  • a silicon dioxide film is formed.
  • FIG. 6 is an enlarged view on the p side in the cross-sectional view of the structure according to the present embodiment after step 4 has been completed.
  • the p-side photoelectric conversion region 20 is formed by laminating an i-type amorphous semiconductor layer 20i and a p-type amorphous semiconductor layer 20p.
  • the i-type amorphous semiconductor layer 20i is, for example, an amorphous intrinsic silicon semiconductor thin film containing hydrogen.
  • the intrinsic semiconductor thin film means that the concentration of the p-type or n-type dopant contained is 5 ⁇ 10 18 / cm 3 or less, or when the p-type and n-type dopants are contained at the same time.
  • the i-type amorphous semiconductor layer 20i be thin to suppress light absorption as much as possible, and thick enough to sufficiently passivate the surface of the semiconductor substrate 10.
  • the i-type amorphous semiconductor layer 20i has a thickness of 1 nm to 25 nm, preferably 5 nm to 10 nm.
  • the i-type amorphous semiconductor layer 20i can be formed by plasma enhanced chemical vapor deposition (PECVD), Cat-CVD (Catalytic Chemical Vapor Deposition), sputtering, or the like.
  • PECVD plasma enhanced chemical vapor deposition
  • it is formed using a method such as an RF (Radio Frequency) plasma CVD method, a VHF (Very High Frequency) plasma CVD method, or a microwave plasma CVD method.
  • RF plasma CVD Radio Frequency
  • VHF Very High Frequency
  • microwave plasma CVD a case where RF plasma CVD is used will be described.
  • the i-type amorphous semiconductor layer 20i is supplied into the film formation chamber by diluting, for example, a silicon-containing gas such as silane (SiH 4 ) with hydrogen gas at a ratio shown in Table 1. Then, it can be formed by applying RF high-frequency power to parallel plate electrodes or the like to turn the silicon-containing gas into plasma and supplying it to the film-forming surface of the heated semiconductor substrate 10.
  • the substrate temperature during film formation is preferably 120 ° C. to 300 ° C.
  • the RF power density is preferably 1 mW / cm 2 to 30 mW / cm 2 .
  • a p-type amorphous semiconductor layer 20p is stacked on the i-type amorphous semiconductor layer 20i.
  • the p-type amorphous semiconductor layer 20p is an amorphous semiconductor layer containing a p-type conductive dopant.
  • the p-type amorphous semiconductor layer 20p is an amorphous p-type silicon semiconductor thin film containing hydrogen.
  • the p-type amorphous semiconductor layer 20p is formed so that the concentration of the p-type dopant in the film is higher than that of the i-type amorphous semiconductor layer 20i.
  • the p-type amorphous semiconductor layer 20p is thinned so as to suppress light absorption as much as possible, while carriers generated in the semiconductor substrate 10 are effectively separated at the pn junction, and the generated carriers are surface electrodes. It is preferable to increase the thickness so that it can be efficiently collected by 30.
  • the p-type amorphous semiconductor layer 20p has a thickness of 1 nm to 25 nm, preferably 5 nm to 10 nm.
  • the p-type amorphous semiconductor layer 20p is formed using a method similar to that of the i-type amorphous semiconductor layer 20i after adding a certain proportion of p-type dopant diborane (B 2 H 6 ).
  • a silicon-containing gas such as silane (SiH 4 ) and a p-type dopant-containing gas such as diborane (B 2 H 6 ) are supplied after being diluted with hydrogen gas. At this time, it is preferable to add about 0.1% to 10% of diborane with respect to silane.
  • the p-type amorphous semiconductor layer 20p is formed by applying RF high-frequency power to parallel plate electrodes or the like to turn the silicon-containing gas into plasma and heating the semiconductor substrate 10 that has been heated. It is formed on the i-type amorphous semiconductor layer 20i by supplying a plasma-containing silicon-containing gas.
  • the substrate temperature during film formation is preferably 120 ° C. to 300 ° C.
  • the RF power density is preferably 1 mW / cm 2 to 30 mW / cm 2 .
  • the film formation conditions of the i-type amorphous semiconductor layer 20i and the p-type amorphous semiconductor layer 20p in this embodiment are conditions that allow relatively easy crystal growth (including microcrystals), and as described above, the p-side When the photoelectric conversion region 20 is formed, the p-side photoelectric conversion region 20 including a part of the crystal region 50 is formed. At this time, the crystal region 50 exists in both the i-type amorphous semiconductor layer 20 i and the p-type amorphous semiconductor layer 20 p and is in contact with both the semiconductor substrate 10 and the surface electrode 30.
  • the n-side photoelectric conversion region 22 is formed by stacking a substantially intrinsic i-type amorphous semiconductor layer 22i and an n-type amorphous semiconductor layer 22n.
  • the i-type amorphous semiconductor layer 22i is, for example, an amorphous intrinsic silicon semiconductor thin film containing hydrogen.
  • the intrinsic semiconductor thin film means that the concentration of the p-type or n-type dopant contained is 5 ⁇ 10 18 / cm 3 or less, or when the p-type and n-type dopants are contained at the same time.
  • a semiconductor thin film having a concentration difference between them of 5 ⁇ 10 18 / cm 3 or less.
  • the i-type amorphous semiconductor layer 22i is preferably thin so as to suppress light absorption as much as possible, and thick enough to sufficiently passivate the surface of the semiconductor substrate 10.
  • the i-type amorphous semiconductor layer 22i has a thickness of 1 nm to 25 nm, preferably 5 nm to 10 nm.
  • the i-type amorphous semiconductor layer 22i can be formed by plasma enhanced chemical vapor deposition (PECVD), Cat-CVD, sputtering, or the like.
  • PECVD plasma enhanced chemical vapor deposition
  • it is formed using a method such as an RF plasma CVD method, a VHF plasma CVD method, or a microwave plasma CVD method.
  • the i-type amorphous semiconductor layer 22i is supplied with a silicon-containing gas such as silane (SiH 4 ) diluted with hydrogen and supplied with RF high-frequency power or the like to parallel plate electrodes or the like. It is formed by supplying plasma-ized silicon-containing gas onto the film-forming surface of the heated semiconductor substrate 10.
  • the dilution rate of the silicon-containing gas when forming the i-type amorphous semiconductor layer 22i is lower than that when forming the i-type amorphous semiconductor layer 20i.
  • the substrate temperature during the film formation of the i-type amorphous semiconductor layer 22i is also 150 ° C. or higher and 250 ° C. or lower.
  • the RF power density is 1 mW / cm 2 or more and 10 mW / cm 2 or less.
  • the n-type amorphous semiconductor layer 22n is an amorphous semiconductor layer containing an n-type conductive dopant.
  • the n-type amorphous semiconductor layer 22n is formed so that the concentration of the n-type dopant in the film is higher than that of the i-type amorphous semiconductor layer 22i.
  • the n-type amorphous semiconductor layer 22n is thinned so as to suppress light absorption as much as possible, while the carriers generated in the semiconductor substrate 10 are generated while being effectively separated by the BSF (Back Surface Field) structure. It is preferable to increase the thickness so that the carriers are efficiently collected by the surface electrode 30.
  • the thickness of the n-type amorphous semiconductor layer 22n is 1 nm to 25 nm, preferably 5 nm to 10 nm.
  • the n-type amorphous semiconductor layer 22n is formed using a method similar to that for the i-type amorphous semiconductor layer 22i after adding an n-type dopant in a certain ratio.
  • an n-type dopant-containing gas such as phosphine (PH 3 ) is diluted with hydrogen and supplied to a silicon-containing gas such as silane (SiH 4 ). At this time, it is preferable to add about 0.1% to 10% of diborane with respect to silane.
  • the n-type amorphous semiconductor layer 22n is formed by applying RF high-frequency power to parallel plate electrodes or the like to turn a silicon-containing gas into plasma, and heating the heated semiconductor substrate 10 It is formed on the i-type amorphous semiconductor layer 22i by supplying a plasma-ized silicon-containing gas.
  • the substrate temperature during film formation is 150 ° C. or more and 250 ° C. or less, and the RF power density is 1 mW / cm 2 or more and 10 mW / cm 2 or less.
  • a surface electrode 30 made of a transparent conductive oxide film is formed on the photoelectric conversion region 20 on the p side and the photoelectric conversion region 22 on the n side.
  • the surface electrode 30 is made of a metal oxide represented by indium tin oxide (ITO), and is formed by a vapor deposition method, a sputtering method, or the like.
  • the surface electrode 30 collects conductive carriers in the p-side photoelectric conversion region 20 and the n-side photoelectric conversion region 22 onto the surface of the photoelectric conversion element 100.
  • the grid electrode 40 for further collecting the conductive carriers collected by the surface electrode 30 and taking out the conductive carriers to the outside of the photoelectric conversion element.
  • the grid electrode 40 is obtained by printing a thermosetting resin paste containing conductive particles such as Ag (silver) particles as a filler on the surface electrode 30 by screen printing or the like, and sintering and drying. Formed.
  • the method of forming the grid electrode 40 is not limited to this, and a grid electrode or the like mainly composed of Cu (copper) may be formed using an electrolytic plating technique. In either case, adjacent photoelectric conversion elements are electrically connected by connecting a wiring material (not shown) to the grid electrode 40 when processing the photoelectric conversion elements into a solar cell module.
  • the photoelectric conversion apparatus 100 of this embodiment is formed by the above processes.
  • FIG. 7 is an enlarged view of a broken line portion in FIG.
  • the photoelectric conversion device 100 includes the p-side photoelectric conversion region 20 on the semiconductor substrate 10, and the p-side photoelectric conversion region 20 is a crystal with high crystallinity as illustrated in FIG. 7.
  • Region 50 is provided therein.
  • the crystal region 50 has a columnar shape, is unevenly distributed in the valley 80b in the uneven shape 60 formed on the surface of the semiconductor substrate 10, and is on the p-side photoelectric conversion region so as to be in contact with both the semiconductor substrate 10 and the surface electrode 30. 20 is penetrated.
  • the crystal regions 50 exist in a dispersed manner without covering the entire valley portion 80b.
  • the crystal region 50 is observed by a transmission electron microscope (TEM), and is observed as a dark region in the dark field image as compared with the amorphous semiconductor layer forming the p-side photoelectric conversion region 20.
  • TEM transmission electron microscope
  • the reason why the p-side photoelectric conversion region 20 having the crystal region 50 localized in the recesses can be formed by the above manufacturing method is considered as follows.
  • the crystal plane of the sloped portion 70 of the quadrangular pyramid which is the convex portion of the concavo-convex shape 60 is (111).
  • the crystal plane of the valley 80b formed by performing isotropic etching in step 2 after the formation of the concavo-convex shape 60 is not (111) but close to (100).
  • the oxidation rate varies depending on the crystal plane exposed on the surface of the semiconductor substrate 10. For this reason, when the semiconductor substrate 10 having two types of crystal planes exposed on the surface is subjected to an oxidation treatment using the method described in this embodiment, the crystal plane is compared with a region close to (100). Thus, the oxidation rate of the region which is the crystal plane (111) is increased. That is, when considered per unit time, the silicon dioxide (SiO 2 ) film formed on the slope portion 70 of the quadrangular pyramid is thicker than the silicon dioxide (SiO 2 ) film formed on the valley portion 80 b.
  • the PECVD condition for forming the p-type photoelectric conversion region in the present embodiment has a high hydrogen dilution rate. That is, the mixed gas of silane (SiH 4 ) gas and hydrogen gas is a condition in which a relatively large amount of hydrogen gas is contained. Under such PECVD conditions, generation of hydrogen radicals is promoted, and crystal growth and microcrystal growth are promoted. The reason is as follows.
  • the arrangement of atoms constituting the film follows the arrangement of atoms exposed on the surface of the substrate. That is, even if an amorphous semiconductor layer is stacked on a crystal substrate with an unstrained crystal plane exposed using the conditions in this embodiment, a layer with high crystallinity as a whole is easily formed.
  • strain may be formed on the surface, or a substance different from the substrate may be formed on the substrate so as not to be affected by crystals on the substrate surface.
  • a gas containing silicon is laminated on the semiconductor substrate 10 in which the silicon dioxide (SiO 2 ) films formed by the sloped portion and the valley portion 80b of the concavo-convex shape 60 are different.
  • the crystal region 50 is unevenly distributed in the valley portion 80b where the silicon dioxide (SiO 2 ) film is thinner than the slope portion 70 of the concavo-convex shape 60.
  • the crystal region 50 thus formed is superior in conductivity as compared with the amorphous semiconductor layer forming the p-side photoelectric conversion region 20. Therefore, the higher the proportion of the crystal region 50 present in the p-side photoelectric conversion region 20, the lower the resistance loss in the film thickness direction of the p-side photoelectric conversion region 20. This effect appears as an increase in the value of the fill factor (FF) in the characteristic parameter when the output of the solar cell is measured.
  • FF fill factor
  • the passivation ability of the p-side photoelectric conversion region 20 is superior to the passivation ability of the crystal region 50. Therefore, if the area where the crystal region 50 is in contact with the semiconductor substrate 10 becomes too large, the passivation effect cannot be maintained and the open circuit voltage (Voc) is lowered.
  • the crystal region 50 is unevenly distributed in the valley 80 b of the semiconductor substrate 10. That is, the fill factor (FF) is increased to prevent the open circuit voltage (Voc) from decreasing.
  • FF fill factor
  • Voc open circuit voltage
  • the semiconductor substrate 10 made of n-type single crystal silicon has been described.
  • the semiconductor substrate 10 made of p-type single crystal silicon may be used.
  • the configuration of the present embodiment is applied to the n-side photoelectric conversion region 22 having a conductivity type opposite to that of the semiconductor substrate 10.
  • the crystal region 50 may also be provided in the n-side photoelectric conversion region 22.
  • the surface electrode 30 is formed between the p-side photoelectric conversion region 20 and the n-side photoelectric conversion region 22 and the grid electrode 40, but the surface electrode 30 is not formed. Also good. That is, the p-side photoelectric conversion region 20 and the n-side photoelectric conversion region 22 may be in direct contact with the grid electrode 40.
  • the p-side photoelectric conversion region 20 is configured by laminating an i-type amorphous semiconductor layer 20i and a p-type amorphous semiconductor layer 20p. Only the semiconductor layer 20p may not include the i-type amorphous semiconductor layer 20i. Even when the semiconductor substrate 10 and the p-side photoelectric conversion region 20 are in direct contact with each other, it is better to provide a crystal region in contact with both the semiconductor substrate 10 and the surface electrode 30 as shown in this embodiment. F. Has the effect of increasing. Similarly, the n-side photoelectric conversion region 22 may include only the n-type amorphous semiconductor layer 22n and may not include the i-type amorphous semiconductor layer 22i.
  • both surfaces may be light incident surfaces.

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Abstract

Ce dispositif de conversion photoélectrique (100) est pourvu d'un substrat semi-conducteur (10) d'un premier type de conductivité, d'une région de conversion photoélectrique côté p (20) d'un second type de conductivité formée sur le substrat semi-conducteur (10), et d'une électrode de surface (30) formée sur la région de conversion photoélectrique côté p (20), une région cristalline (50) qui entre en contact à la fois avec le substrat semi-conducteur (10) et l'électrode de surface (30) étant disposée dans la région de conversion photoélectrique côté p (20).
PCT/JP2016/002259 2015-07-13 2016-05-09 Dispositif de conversion photoélectrique Ceased WO2017010029A1 (fr)

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JP2015139296 2015-07-13

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018180486A1 (fr) * 2017-03-29 2018-10-04 パナソニック株式会社 Cellule solaire et procédé de production de cellule solaire
JP2018195827A (ja) * 2017-05-19 2018-12-06 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法

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Publication number Priority date Publication date Assignee Title
WO2013111312A1 (fr) * 2012-01-26 2013-08-01 三菱電機株式会社 Dispositif photovoltaïque, procédé de fabrication de celui-ci et module photovoltaïque
WO2014155833A1 (fr) * 2013-03-28 2014-10-02 三洋電機株式会社 Batterie solaire

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013111312A1 (fr) * 2012-01-26 2013-08-01 三菱電機株式会社 Dispositif photovoltaïque, procédé de fabrication de celui-ci et module photovoltaïque
WO2014155833A1 (fr) * 2013-03-28 2014-10-02 三洋電機株式会社 Batterie solaire

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018180486A1 (fr) * 2017-03-29 2018-10-04 パナソニック株式会社 Cellule solaire et procédé de production de cellule solaire
JPWO2018180486A1 (ja) * 2017-03-29 2019-11-07 パナソニック株式会社 太陽電池セル及び太陽電池セルの製造方法
US11430904B2 (en) 2017-03-29 2022-08-30 Panasonic Holdings Corporation Solar cell and method of manufacturing solar cell
JP2018195827A (ja) * 2017-05-19 2018-12-06 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法
CN108963013A (zh) * 2017-05-19 2018-12-07 Lg电子株式会社 太阳能电池及其制造方法
JP2020098929A (ja) * 2017-05-19 2020-06-25 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法
CN108963013B (zh) * 2017-05-19 2022-05-27 Lg电子株式会社 太阳能电池及其制造方法
JP7185818B2 (ja) 2017-05-19 2022-12-08 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法

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