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WO2013071513A1 - Lcd数据驱动ic输出补偿电路、补偿方法及液晶显示器 - Google Patents

Lcd数据驱动ic输出补偿电路、补偿方法及液晶显示器 Download PDF

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Publication number
WO2013071513A1
WO2013071513A1 PCT/CN2011/082434 CN2011082434W WO2013071513A1 WO 2013071513 A1 WO2013071513 A1 WO 2013071513A1 CN 2011082434 W CN2011082434 W CN 2011082434W WO 2013071513 A1 WO2013071513 A1 WO 2013071513A1
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WIPO (PCT)
Prior art keywords
output
flip
delay control
flop
shift
Prior art date
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PCT/CN2011/082434
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English (en)
French (fr)
Inventor
廖良展
林柏伸
郭东胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to DE201111105725 priority Critical patent/DE112011105725T5/de
Priority to US13/380,043 priority patent/US8791893B2/en
Publication of WO2013071513A1 publication Critical patent/WO2013071513A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the invention relates to the field of liquid crystal display technology, in particular to an LCD data driving IC output compensation circuit, a compensation method and a liquid crystal display which are advantageous for a narrow bezel design of a liquid crystal display.
  • the data line 2 in the liquid crystal panel is in the slave data drive IC (Integrated In the circuit, when the output of the circuit, the signal of each data line 2 reaches each pixel of each line at the same time, the impedance of each data line 2 should be substantially the same when the lines are routed.
  • the output channels of the current data driving IC3 are basically simultaneous output, which will cause EMI (Electro) to be generated when all the output channels are simultaneously turned on, because a large current needs to be supplied to the glass substrate.
  • EMI Electro
  • Magnetic Interference the problem of electromagnetic interference
  • the main object of the present invention is to provide an LCD data driving IC output compensation circuit, a compensation method, and a liquid crystal display, which are intended to reduce the wiring space of the glass substrate and facilitate the narrow bezel design of the liquid crystal display.
  • an LCD data driving IC output compensation circuit comprising: a data driving IC, a plurality of first switching units, and a delay control unit, wherein:
  • the data driving IC includes a plurality of output channels, wherein the plurality of output channels are respectively connected to pixel electrodes of corresponding rows in the glass substrate through the data lines, for outputting a charging signal, and charging the pixel electrodes of the corresponding rows;
  • the first switch unit is correspondingly disposed on each of the output channels, and is connected to the corresponding delay control unit, configured to control, according to the delay control signal generated by the delay control unit, the first switch unit An output channel that outputs the charging signal at a predetermined delay;
  • the delay control unit is configured to generate a corresponding delay control signal according to the impedance value of the corresponding data line, and control the corresponding first switch unit to be turned on at a predetermined delay to make the charging time of each of the pixel electrodes equal.
  • the delay control unit includes a shift trigger, and a second switch unit, wherein the first and second switch units are MOS tubes, wherein:
  • each shift flip-flop has a first input end, a second input end and an output end, except for the first input end of the shift flip-flop of the first stage Connect the external high/low level trigger signal input terminal to receive the high/low level trigger signal of the external input, and the first input terminals of the remaining level shift triggers are respectively connected to the shift trigger of the previous stage.
  • the first input end of the first stage shift flip-flop is also respectively connected to the gates of the respective second switch units; the second input end of each shift flip-flop is connected to a clock controller, each shift The output ends of the flip-flops are respectively connected to the drains of the corresponding second switch units and the gates of the corresponding first switch units; the sources of the respective second switch units are grounded;
  • the drains of the respective first switching units are connected to the corresponding output channels, and the sources of the respective first switching units are connected to the corresponding pixel electrodes;
  • each shift flip-flop When the first input end of the first stage shift flip-flop receives the high level trigger signal, each shift flip-flop generates a predetermined delay delay control signal according to the frequency of the clock control signal generated by the clock controller. Opening the corresponding first switch unit step by step; when the first input end of the first stage shift trigger receives the low level trigger signal, each shift trigger control opens the second switch unit connected thereto, and controls The corresponding first switching unit is turned off.
  • the impedance value of the data line decreases stepwise along the symmetry of the two ends of the data driving IC.
  • the data driving IC has n output channels, the first switching unit corresponds to n; when the output channels are even, the delay control unit is n/2, which are cascaded with each other.
  • the shift flip-flop includes n/2 stages; each stage shift flip-flop is connected with a second switch unit, and the output ends of the first-stage shift flip-flops are respectively connected to the first and nth first switch units a gate of the second stage shifting flip-flop is respectively connected to the gates of the second and n-1th first switching units, and so on, wherein n is a natural number;
  • the delay control unit is (n+1)/2, and the shift flip-flops that are cascaded with each other include (n+1)/2 levels; each The stage shifting trigger is connected to a second switching unit, and the output ends of the first stage shifting flip-flops are respectively connected to the gates of the first and nth first switching units; the output ends of the second-stage shifting flip-flops are respectively Connecting the gates of the second and n-1th first switching units, and so on, the output of the nth stage shifting flip-flop is connected to the gates of the (n+1)/2th first switching unit, wherein n is a natural number.
  • the data driving IC has n output channels, the first switching unit corresponds to n; the delay control unit is n, and the shift triggers cascaded with each other are n levels, each The first shifting trigger is connected to a second switching unit, the output of the first stage shifting trigger is connected to the gate of the first first switching unit, and the output of the second stage shifting trigger is connected to the second The gate of the first switching unit, and so on, the output of the nth stage shifting flip-flop is connected to the gate of the nth first switching unit.
  • the high/low level trigger signal is a charging signal output by the data driving IC.
  • the cascaded shift flip-flop is a shift register in the data drive IC.
  • the clock controller is built in the data driving IC.
  • the invention also provides an LCD data driving IC output compensation method, comprising the following steps:
  • the delay control unit controls the clock controller to generate a corresponding delay control signal according to the impedance value of each data line between the data driving IC and the pixel electrode of the corresponding row on the glass substrate, and sends the corresponding delay control signal to the output channel corresponding to the data driving IC.
  • the first switching unit on the output channel corresponding to the data driving IC controls the output channel where the first switching unit is located to output a charging signal to a corresponding pixel electrode according to the delay control signal, so that each corresponding row The charging time of one of the pixel electrodes is equal.
  • the method further includes: when the delay control unit receives the high level trigger signal, each delay control unit generates a corresponding delay control signal according to the frequency of the clock control signal output by the clock controller, step by step Opening a corresponding first switch unit, so that the output channel corresponding to the first switch unit outputs a charging signal to a corresponding pixel electrode according to a predetermined delay; when the delay control unit receives a low level trigger signal, each delay The control unit controls to close the corresponding first switching unit.
  • the impedance value of the data line decreases stepwise along the symmetry of the two ends of the data driving IC.
  • the invention also provides a liquid crystal display comprising a data driving IC output compensation circuit, the data driving IC output compensation circuit comprising: a data driving IC, a plurality of first switching units and a delay control unit, wherein:
  • the data driving IC includes a plurality of output channels, wherein the plurality of output channels are respectively connected to pixel electrodes of corresponding rows in the glass substrate through the data lines, for outputting a charging signal, and charging the pixel electrodes of the corresponding rows;
  • the first switch unit is correspondingly disposed on each of the output channels, and is connected to the corresponding delay control unit, configured to control, according to the delay control signal generated by the delay control unit, the first switch unit An output channel that outputs the charging signal at a predetermined delay;
  • the delay control unit is configured to generate a corresponding delay control signal according to the impedance value of the corresponding data line, and control the corresponding first switch unit to be turned on at a predetermined delay to make the charging time of each of the pixel electrodes equal.
  • the delay control unit includes a shift trigger, and a second switch unit, wherein the first and second switch units are MOS tubes, wherein:
  • each shift flip-flop has a first input end, a second input end and an output end, except for the first input end of the shift flip-flop of the first stage Connect the external high/low level trigger signal input terminal to receive the high/low level trigger signal of the external input, and the first input terminals of the remaining level shift triggers are respectively connected to the shift trigger of the previous stage.
  • the first input end of the first stage shift flip-flop is also respectively connected to the gates of the respective second switch units; the second input end of each shift flip-flop is connected to a clock controller, each shift The output ends of the flip-flops are respectively connected to the drains of the corresponding second switch units and the gates of the corresponding first switch units; the sources of the respective second switch units are grounded;
  • the drains of the respective first switching units are connected to the corresponding output channels, and the sources of the respective first switching units are connected to the corresponding pixel electrodes;
  • each shift flip-flop When the first input end of the first stage shift flip-flop receives the high level trigger signal, each shift flip-flop generates a predetermined delay delay control signal according to the frequency of the clock control signal generated by the clock controller. Opening the corresponding first switch unit step by step; when the first input end of the first stage shift trigger receives the low level trigger signal, each shift trigger control opens the second switch unit connected thereto, and controls The corresponding first switching unit is turned off.
  • the impedance value of the data line decreases stepwise along the symmetry of the two ends of the data driving IC.
  • the data driving IC has n output channels, the first switching unit corresponds to n; when the output channels are even, the delay control unit is n/2, which are cascaded with each other.
  • the shift flip-flop includes n/2 stages; each stage shift flip-flop is connected with a second switch unit, and the output ends of the first-stage shift flip-flops are respectively connected to the first and nth first switch units a gate of the second stage shifting flip-flop is respectively connected to the gates of the second and n-1th first switching units, and so on, wherein n is a natural number;
  • the delay control unit is (n+1)/2
  • the shift flip-flops that are cascaded with each other include (n+1)/2 levels
  • each The stage shifting trigger is connected to a second switching unit, and the output ends of the first stage shifting flip-flops are respectively connected to the gates of the first and nth first switching units; the output ends of the second-stage shifting flip-flops are respectively Connecting the gates of the second and n-1th first switching units, and so on, the output of the (n+1)/2th shifting flip-flop is connected to the (n+1)/2th first switching unit
  • the gate where n is a natural number.
  • the data driving IC has n output channels, the first switching unit corresponds to n; the delay control unit is n, and the shift triggers cascaded with each other are n levels, each The first shifting trigger is connected to a second switching unit, the output of the first stage shifting trigger is connected to the gate of the first first switching unit, and the output of the second stage shifting trigger is connected to the second The gate of the first switching unit, and so on, the output of the nth stage shifting flip-flop is connected to the gate of the nth first switching unit.
  • the high/low level trigger signal is a charging signal output by the data driving IC.
  • the cascaded shift flip-flop is a shift register in the data drive IC.
  • the clock controller is built in the data driving IC.
  • the invention provides an LCD data driving IC output compensation circuit, a compensation method and a liquid crystal display.
  • the charging signal outputted by the delay control unit to the data driving IC is sequentially delayed from the two sides to the middle, thereby compensating the data driving IC to each row of pixels.
  • the problem of impedance mismatch of the data lines between the electrodes makes the charging time of each output channel in a certain row of pixel electrodes substantially the same, while ensuring the uniform display of the liquid crystal display, since the data lines do not need to be wound,
  • the glass substrate has a small wiring space, which is more conducive to the narrow bezel design of the liquid crystal display, COF (Chip) On Film, flip-chip film can also use more output channels, reducing the cost; it also improves the EMI problem that occurs when all output channels are turned on at the same time.
  • FIG. 1 is a schematic structural diagram of a data driving IC connecting pixel regions through a data line in the prior art
  • FIG. 2 is a schematic structural diagram of a data driving IC connecting pixel regions through data lines in an embodiment of an LCD data driving IC output compensation circuit according to the present invention
  • FIG. 3 is a schematic structural diagram of an embodiment of an LCD data driving IC output compensation circuit of the present invention.
  • FIG. 4 is a schematic diagram showing the operation timing of each output channel in the embodiment of the LCD data driving IC output compensation circuit according to the present invention.
  • FIG. 5 is a schematic flow chart of an embodiment of an LCD data driving IC output compensation method according to the present invention.
  • the main solution of the present invention is: by setting an output control switch on the output channel of the data driving IC, and by stepping the switch on each output channel according to the impedance value of each data line by the delay control unit, thereby making each of the glass substrates
  • the charging time of each pixel electrode of one row is the same, which ensures the uniformity of the screen display, and the data line does not need to adopt a serpentine routing method to reduce the winding space, which is beneficial to the narrow frame design of the liquid crystal display.
  • FIG. 2 is a schematic structural diagram of the data line outputted by the data driving IC of the present invention without charging the pixel and charging the pixel electrode.
  • FIG. 3 is a schematic structural diagram of a data driving IC output compensation circuit according to the present invention.
  • the data driving IC 30 connects the pixel regions 10 through a plurality of data lines (indicated by n in the figure, n is a natural number) 20, and charges the pixel electrodes in the pixel region 10.
  • the trace When the data line 20 is output from the data driving IC 30, the trace does not make a serpentine line as shown in FIG. 1, but adopts a straight line form, which saves space wasted by the winding, so that the border of the liquid crystal panel can be made. Narrower.
  • the length of each of the data lines 20 outputted by the data driving IC 30 is different, and the impedance values thereof are also inconsistent. If all the output channels of the data driving IC 30 are simultaneously output, the data signals are charged to the corresponding pixels through each of the data lines 20.
  • the time of the data line 20 having a large impedance value is relatively short, so that the picture display of the pixel area 10 controlled by the data driving IC 3 is uneven.
  • the present invention controls the output of each output channel by the delay control unit 50 so that the output time of each output channel matches the impedance value of the corresponding data line 20, ensuring that each output channel is in a row of the pixel region 10.
  • the charging time of the pixel electrodes is uniform, so that a uniform display picture is obtained.
  • the LCD data driving IC output compensation circuit includes a data driving IC 30, a plurality of first switching units 40, and a plurality of delay control units 50, wherein:
  • the data driving IC 30 includes a plurality of output channels, and the plurality of output channels are respectively connected to the pixel electrodes of the corresponding rows in the glass substrate through the data lines 20 for outputting a charging signal to charge the pixel electrodes of the corresponding rows;
  • Each of the first switching units 40 is correspondingly disposed on each output channel, and is connected to a corresponding delay control unit 50 for controlling the output channel of the first switching unit 40 according to the delay control signal generated by the delay control unit 50. Outputting the charging signal at a predetermined delay;
  • Each delay control unit 50 is configured to generate a corresponding delay control signal according to the impedance value of the corresponding data line 20, and control the corresponding first switch unit 40 to be turned on at a predetermined delay to make the charging time of each pixel electrode equal.
  • the delay control unit 50 includes a shift trigger 501, and a second switch unit 502.
  • the first and second switch units 40 and 502 are both MOS tubes (Metal Oxide). Semiconductor Field Effect Transistor, metal oxide semiconductor type field effect transistor), wherein the first switching unit 40 is an NMOS transistor, and the second switching unit 502 is a PMOS transistor.
  • each shift flip-flop 501 of each delay control unit 50 are cascaded with each other, and each shift flip-flop 501 has a first input end, a second input end, and an output end, except for the shift flip-flop of the first stage.
  • the first input of 501 is connected to an external high/low trigger signal input (Out On), in addition to receiving the high/low level trigger signal of the external input, the first input terminals of the remaining stages of the shift flip-flops 501 are respectively connected to the output ends of the shift flip-flops 501 of the previous stage.
  • each shifting flip-flop 501 is connected to a clock controller; the output ends of the shifting flip-flops 501 are respectively connected to the drains of the corresponding second switching units 502, and are also respectively connected to the corresponding first switches.
  • the gate of unit 40; the source of each second switching unit 502 is grounded.
  • the first input end of the shifting flip-flop 501 of the first stage is also connected to the gates of the respective second switching units 502, respectively.
  • the drains of the respective first switching units 40 are connected to corresponding output channels, and the sources of the respective first switching units 40 are connected to corresponding pixel electrodes.
  • each shift flip-flop 501 When the first input end of the first stage shift flip-flop 501 receives the high level trigger signal, each shift flip-flop 501 generates a delay control signal of a predetermined delay step by step according to the frequency of the clock control signal generated by the clock controller. Opening the corresponding first switch unit 40 stepwise; when the first input end of the first stage shift flip-flop 501 receives the low level trigger signal, each shift flip-flop 501 controls to open the second switch connected thereto The unit 502 controls the corresponding first switch unit 40 to be turned off.
  • the impedance value of the data line 20 is gradually reduced along the intermediate symmetry of the data driving IC 30, and the data line 20 with the smallest impedance is not necessarily the output channel in the middle of the COF.
  • the increase in the impedance of the data line 20 is not necessarily symmetrical, and it is necessary to adjust the delay according to the actual impedance distribution to achieve the best effect.
  • the output channel corresponds to 2k-1 data lines 20, the first switching unit 40 corresponds to 2k-1; at the same time, the delay control unit 50 is defined as k, and the shift triggers 501 connected to each other include k levels, each level
  • the shift flip-flop 501 is connected to a second switch unit 502.
  • the output ends of the first stage shift flip-flops 501 are respectively connected to the gates of the first and second k-1 first switching units 40; the output ends of the second stage shift flip-flops 501 are connected to the second and second k-2, respectively.
  • the gates of the first switching units 40, and so on, the output of the kth stage shifting flip-flop 501 is connected to the gate of the kth first switching unit 40.
  • the routing of the data line 20 is as shown in FIG. 2, and the magnitude of the impedance is gradually reduced symmetrically from both ends toward the middle.
  • the kth data line 20 is output from the kth channel of the data driving IC 30, and the path between the data driving IC 30 and the pixel area 10 is the closest, the impedance is the smallest, and the channel impedances of the left and right channels are symmetrically increased successively, the first data
  • the impedance value of the line 20 is reduced one by one to the kth data line 20, and then from the k+1th data line 20, the impedance value thereof is increased one by one to the 2k-1th data line 20, wherein the first data line 20 is the same as the impedance value of the data line 20 of the 2k-1th, the impedance value of the second data line 20 and the second data line 20 is the same, and so on, the impedance of the k-1th data line 20
  • the value is the same as the impedance value of the k+1th data line 20, and the impedance value of the kth data line 20 is the smallest.
  • the delay control unit 50 if the delay control unit 50 is not operating, if each output channel of the data driving IC 30 simultaneously outputs a signal, the charging time will gradually decrease from the kth output channel toward both sides. In this way, when the same gray scale is displayed, the displayed colors will be different.
  • the specific principle is as follows:
  • 2k-1 first switching units 40 correspond one-to-one to control the switching of the output channel where 2k-1 data lines 20 are located, and the first first switching unit 40 is located on the first output channel of the data driving IC3 for Controlling the switch of the first data line 20, the second first switch unit 40 is located on the second output channel of the data drive IC 30, for controlling the switch of the second data line 20, and so on, the kth first
  • the switch unit 40 is located on the kth output channel of the data drive IC 30 for controlling the 20 switches of the kth data line, and the 2k-1 first switch unit 40 is located on the 2k-1th output channel of the data drive IC 30. The switch for controlling the 2k-1th data line 20.
  • the shift flip-flop 501 in this embodiment may be a rising edge D flip-flop.
  • the cascaded shift flip-flop 501 is a rising-edge D flip-flop 501 of k-stage series, and the output end of each stage of the rising edge D flip-flop 501 is connected to the gate of the corresponding first switching unit 40 for controlling the corresponding first The opening and closing of the switch unit 40.
  • the output of the first stage rising edge D flip-flop 501 is connected to the gate of the first switching unit 40 of the first and second k-1 data lines 20, and the output of the second stage is connected to the second and the The gate of the first switching unit 40 of the 2k-2 data lines 20, and so on, and the k-1th stage output is connected to the gate of the first switching unit 40 of the k-1th and k+1th data lines 20.
  • the output of the kth stage is connected to the gate of the first switching unit 40 of the kth data line 20.
  • each second switching unit 502 is coupled to the input of the first stage rising edge D flip-flop 501 for simultaneously receiving an externally input high/low power level trigger signal.
  • each of the second switching units 502 is connected to the gate of the first switching unit 40, that is, the first second switching unit 502 is connected to the gate of the first first switching unit 40.
  • the two second switching units 502 are connected to the gate of the second first switching unit 40 by a drain, and so on, and the drain of the kth second switching unit 502 is connected to the gate of the kth first switching unit 40.
  • the drains of the 2k-1 second switching units 502 are connected to the gates of the 2k-1 first switching units 40, and the sources of all the second switching units 502 are grounded.
  • FIG. 4 is a schematic diagram showing the operation timing of each output channel of the data driving IC 30.
  • the rising edge of the cascaded rising edge D flip-flop 501 is the rising edge of the clock signal clk of the clock control signal input terminal, the rising edge D flip-flop 501 will flip, its flipped state is received by the second input Out
  • the level of the on signal determines the level, before the time t1, Out
  • the on signal is low
  • the output of each rising edge D flip-flop 501 is low
  • all the first switching units 40 are in the off state, at time t1, Out
  • the on signal jumps from a low level to a high level.
  • the rising edge of the clock signal of the second input terminal of the D flip-flop 501 rises at the rising edge of the first stage, and the D flip-flop 501 of the first rising edge turns over, the first
  • the rising edge of the D flip-flop 501 is flipped to a high level and supplied to the second input of the second-stage rising edge D flip-flop 501, at which time the first first switching unit 40 and the 2k-1th
  • the gate of the first switching unit 40 receives a high level, controls the first data line and the 2k-1th data line to be turned on, and charges the corresponding pixel.
  • the second stage rising edge is the second of the D flip-flop 501.
  • the output of the D-flip-flop 501 of the second-stage rising edge is inverted to a high level, at this time, the second first switching unit 40 and the 2k -
  • the gates of the two first switching units 40 receive a high level, control the second data line and the second k-2 data lines to be turned on, charge the corresponding pixels, and so on, at time tk, at which time the kth level rises
  • a high level is output along the output end of the D flip-flop 501, and the gate of the kth first switching unit 40 receives a high level, and the kth block is controlled.
  • each delay control unit 50 controls the output channel of each data line 20 to be turned on at an appropriate timing, so that the data line 20 is opened one by one from the both ends to the middle, and the difference in impedance values is compensated, thereby ensuring each pixel electrode.
  • the charging time is the same.
  • the rising edge of the cascade is changed from a high level to a low level at the second input end of the D flip-flop 501.
  • the output channels of all the data lines 20 are instantaneously pulled down by the second switching unit 502. shut down.
  • the data driving IC 30 and the delay control unit 50 can pass COF or COG (chip on The glass, on the glass chip package, is pressed onto the glass substrate.
  • the data line 20 The impedance value is still uniformly decreased from both ends to the middle, and the delay control unit 50 controls the clock controller to generate a corresponding delay control signal according to the impedance value of each data line 20, so that the charging signal output by the data driving IC 30 is from the two sides to the middle.
  • the delay is sequentially performed to compensate for the problem of impedance mismatch of the data driving IC 30 to the data line 20 between each row of pixel electrodes, so that the charging time of each output channel at a certain row of pixel electrodes is substantially the same.
  • the impedance value of the data line 20 does not necessarily decrease uniformly from both ends to the middle, and the increase of the impedance from the middle to the both ends is not necessarily symmetrical, and the waveform is The delay may also be different.
  • the waveform delay of the output is adjusted according to the actual impedance distribution.
  • each stage of the rising edge D flip-flop 501 may include one or more rising edge D flip-flops 501 in series, Thereby adaptive compensation is obtained such that the charging time of each pixel electrode is uniform.
  • the cascading rising edge D flip-flop 501 can also be shared by the shift register in the data driving IC 30.
  • the clock controller can also be built in the data driving IC 30, and can also be moved by using the T-CON in the data driving IC 30.
  • the second input end of the bit controller, that is, the clock control signal receiving end is connected to the T-CON (time-control, timing controller) output, which is provided by the T-CON. Since the clock signal frequency is high at this time, it can also be controlled.
  • the cascaded rising edge of the clock signal clk of the D flip-flop 501 is used to obtain an adaptive ⁇ t, thereby ensuring that the charging time of each pixel electrode is consistent to achieve an optimal reality picture. At the same time, you can control the length of the output channel by controlling the frequency of the clk or by dividing more D flip-flops.
  • the high/low level trigger signal received by the cascaded rising edge D flip-flop 501 may also be the charging signal output by the data driving IC.
  • the output time of each output channel is adjusted, so that the output time of each channel matches the impedance value of the corresponding data line, so that the charging time of each channel in a certain row is consistent, thereby obtaining a uniform display picture.
  • the output compensation without the serpentine line is achieved, the utilization of the glass substrate is improved, the frame of the glass can be made narrower, and the data driving IC3 can adopt more output channels, thereby reducing the cost.
  • the problem that all channels are simultaneously opened to generate EMI is also improved.
  • the manner that the number of the delay control unit 50 and the output channel of the data driving IC 30 are in one-to-one correspondence may be defined, that is, when the data driving IC 30 has n channels, the delay The control unit 50 is also n, and the shift flip-flops 501 connected to each other are n stages, and the output end of the first stage shift flip-flop 501 is connected to the gate of the first first switch unit 40, and the second stage is shifted.
  • the output end of the flip-flop 501 is connected to the gate of the second first switching unit 40, and so on.
  • the output end of the n-th shift flip-flop 501 is connected to the gate of the n-th first switching unit 40, and other working modes Both the principle and the principle are the same as the foregoing preferred embodiment.
  • the present invention also provides an LCD data driving IC output compensation method, including:
  • Step S101 the delay control unit controls, according to the impedance value of each data line between the data driving IC and the pixel electrode of the corresponding row on the glass substrate, to generate a corresponding delay control signal by the clock controller, and sends the corresponding delay control signal to the output channel corresponding to the data driving IC.
  • the first switching unit controls, according to the impedance value of each data line between the data driving IC and the pixel electrode of the corresponding row on the glass substrate, to generate a corresponding delay control signal by the clock controller, and sends the corresponding delay control signal to the output channel corresponding to the data driving IC.
  • Step S102 the first switching unit on the output channel corresponding to the data driving IC controls the output channel where the first switching unit is located to output a charging signal to the corresponding pixel electrode according to the delay control signal according to the delay control signal, so that each of the corresponding rows The charging time of the pixel electrodes is equal.
  • each delay control unit when the delay control unit receives the high level trigger signal, each delay control unit generates a corresponding delay control signal according to the frequency of the clock control signal output by the clock controller.
  • the first switch unit is opened, so that the output channel corresponding to the first switch unit outputs a charging signal to the corresponding pixel electrode according to a predetermined delay; when the delay control unit receives the low level trigger signal, each delay control The unit control turns off the corresponding first switching unit.
  • the impedance value of the data line is gradually reduced along the symmetry of the two ends of the data driving IC, and the impedance value of the data line is not necessarily determined according to the design of the wiring of different liquid crystal panels. It is uniformly reduced from the two ends to the middle, and the increase of the impedance from the middle to the both ends is not necessarily symmetrical, and the delay of the waveform will also be different. At this time, the waveform delay of the output should be adjusted according to the actual impedance distribution. In order to achieve the best results.
  • the basic principle of data driver IC output compensation please refer to the above-mentioned output compensation circuit for specific implementation, and will not be described here.
  • the present invention also provides a liquid crystal display, which includes the LCD data driving IC output compensation circuit described in the above embodiments, and details are not described herein again.
  • the LCD data driving IC output compensation circuit, the compensation method and the liquid crystal display of the invention adopt the delay control unit to delay the charging signal outputted by the data driving IC from the two sides to the middle, thereby compensating the data driving IC to the pixel electrode between each row.
  • the problem of impedance mismatch of the data lines makes the charging time of each output channel in a certain row of pixel electrodes substantially the same. While ensuring the uniform display of the liquid crystal display, the data substrate does not need to be wound, so that the glass substrate is taken away. The small line space is more conducive to the narrow bezel design of the liquid crystal display.
  • the COF can also adopt more output channels, which reduces the cost; and also improves the EMI problem generated when all the output channels are simultaneously opened.

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Abstract

本发明公开了一种LCD数据驱动IC输出补偿电路及补偿方法及液晶显示器，该补偿电路包括数据驱动IC（30）、若干第一开关单元（40）以及延迟控制单元（50），数据驱动IC（30）的若干输出通道分别通过数据线（20）与玻璃基板中对应行的像素电极连接，输出充电信号为对应行的像素电极充电；每一输出通道设置第一开关单元（40），用于根据延迟控制单元（50）产生的延迟控制信号，控制该第一开关单元（40）所在的输出通道，将充电信号按预定延时输出；延迟控制单元（50）根据对应的数据线（20）的阻抗值产生对应的延迟控制信号，控制对应的第一开关单元（40）按预定延时开启，使每一像素电极的充电时间相等。该液晶显示器无需绕线，减少玻璃基板的走线空间，利于液晶显示器的窄边框设计，改善了所有输出通道同时打开时产生的EMI问题。

Description

LCD数据驱动IC输出补偿电路、补偿方法及液晶显示器
技术领域
本发明涉及液晶显示技术领域，尤其涉及一种利于液晶显示器窄边框设计的LCD数据驱动IC输出补偿电路、补偿方法及液晶显示器。
背景技术
如图1所示，液晶面板中的数据线2，在从数据驱动IC（Integrated Circuit，集成电路）3输出时，为了使每条数据线2的信号同时到达每行的每一个像素，在走线时每条数据线2的阻抗应基本一致。
在现有技术中，为了使到达每一个像素时每条走线的阻抗基本一致，通常采用一段蛇形走线来实现，数据线2会经过一段蛇形的绕线再连接到像素区域1，根据数据线2的材质和长度使得每条数据线2阻抗基本一致。这样，当扫描线打开某一行像素时，数据驱动IC3的所有输出通道同时输出，此时每一行的数据线的阻抗均一致，因此，给同一行的每个像素充电的时间都一致，这样画面的均匀性会好，反之，当数据线阻抗设计不一致时，同一行的每个像素充电的时间就会有差异，对应数据线控制区域的画面显示就会有不均匀的问题。
但是，随着单颗数据驱动IC3输出通道数的增加，为满足输出补偿，用蛇形来走线需要的空间会变大，而目前边框的发展趋势是朝窄边框的方向发展，绕线的空间将逐渐缩小，因此，现有的蛇形的数据线的走线方式无法满足绕线空间小且画面显示均匀的窄边框液晶显示器的要求。另外目前数据驱动IC3的输出通道基本都是同时输出，这样会使得在所有的输出通道同时打开时，因为需要给玻璃基板提供一个较大的电流，由此产生EMI（Electro Magnetic Interference，电磁干扰）的问题。
发明内容
本发明的主要目的在于提供一种LCD数据驱动IC输出补偿电路、补偿方法及液晶显示器，旨在减少玻璃基板的走线空间，利于液晶显示器的窄边框设计。
为了达到上述目的，本发明提出一种LCD数据驱动IC输出补偿电路，包括：数据驱动IC、若干第一开关单元以及延迟控制单元，其中：
所述数据驱动IC包括若干输出通道，所述若干输出通道分别通过数据线与玻璃基板中对应行的像素电极连接，用于输出充电信号，为所述对应行的像素电极充电；
所述第一开关单元，对应设置在每一所述输出通道上，并连接相应的所述延迟控制单元，用于根据所述延迟控制单元产生的延迟控制信号，控制该第一开关单元所在的输出通道，将所述充电信号按预定延时输出；
所述延迟控制单元，用于根据对应的所述数据线的阻抗值产生对应的延迟控制信号，控制对应的所述第一开关单元按预定延时开启，使每一所述像素电极的充电时间相等。
优选地，所述延时控制单元包括移位触发器，以及第二开关单元，所述第一、第二开关单元均为MOS管，其中：
各个所述延时控制单元的移位触发器相互级联；各移位触发器均具有第一输入端、第二输入端以及输出端，除第一级的移位触发器的第一输入端连接外部的高/低电平触发信号输入端，用于接收外部输入的高/低电平触发信号外，其余各级移位触发器的第一输入端分别连接其前一级的移位触发器的输出端；第一级移位触发器的第一输入端还分别与各个第二开关单元的栅极连接；各移位触发器的第二输入端均连接一时钟控制器，各移位触发器的输出端还分别连接对应的第二开关单元的漏极以及对应的第一开关单元的栅极；各个第二开关单元的源极接地；
各个第一开关单元的漏极连接对应的输出通道，各个第一开关单元的源极连接对应的像素电极；
当第一级移位触发器的第一输入端接收到高电平触发信号时，各移位触发器根据所述时钟控制器产生的时钟控制信号的频率逐级产生预定延时的延迟控制信号，逐级打开相应的第一开关单元；当第一级移位触发器的第一输入端接收到低电平触发信号时，各移位触发器控制分别打开与其连接的第二开关单元，控制对应的第一开关单元关闭。
优选地，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
优选地，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；当所述输出通道为偶数个时，所述延时控制单元为n/2个，相互级联的所述移位触发器包括n/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，其中，n为自然数；
或者，当所述输出通道为奇数个时，所述延时控制单元为（n+1）/2个，相互级联的所述移位触发器包括（n+1）/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，第n级移位触发器的输出端连接第（n+1）/2个第一开关单元的栅极，其中，n为自然数。
优选地，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；所述延时控制单元为n个，相互级联的所述移位触发器为n级，每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端连接第1个第一开关单元的栅极，第2级移位触发器的输出端连接第2个第一开关单元的栅极，依次类推，第n级移位触发器的输出端连接第n个第一开关单元的栅极。
优选地，所述高/低电平触发信号为所述数据驱动IC输出的充电信号。
优选地，所述级联的移位触发器为所述数据驱动IC中的移位寄存器。
优选地，所述时钟控制器内置于所述数据驱动IC中。
本发明还提出一种LCD数据驱动IC输出补偿方法，包括以下步骤：
延迟控制单元根据数据驱动IC与玻璃基板上对应行的像素电极之间的各数据线的阻抗值，由时钟控制器控制产生相应的延迟控制信号，发送至所述数据驱动IC对应的输出通道上的第一开关单元；
所述数据驱动IC对应的输出通道上的第一开关单元根据所述延迟控制信号，控制该第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极，使对应行的每一所述像素电极的充电时间相等。
优选地，该方法还包括：当所述延迟控制单元接收到高电平触发信号时，各延迟控制单元根据所述时钟控制器输出的时钟控制信号的频率，产生相应的延迟控制信号，逐级打开对应的第一开关单元，使所述对应第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极；当所述延迟控制单元接收到低电平触发信号时，各延迟控制单元控制关闭对应的第一开关单元。
优选地，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
本发明还提出一种液晶显示器，包括数据驱动IC输出补偿电路，所述数据驱动IC输出补偿电路包括：数据驱动IC、若干第一开关单元以及延迟控制单元，其中：
所述数据驱动IC包括若干输出通道，所述若干输出通道分别通过数据线与玻璃基板中对应行的像素电极连接，用于输出充电信号，为所述对应行的像素电极充电；
所述第一开关单元，对应设置在每一所述输出通道上，并连接相应的所述延迟控制单元，用于根据所述延迟控制单元产生的延迟控制信号，控制该第一开关单元所在的输出通道，将所述充电信号按预定延时输出；
所述延迟控制单元，用于根据对应的所述数据线的阻抗值产生对应的延迟控制信号，控制对应的所述第一开关单元按预定延时开启，使每一所述像素电极的充电时间相等。
优选地，所述延时控制单元包括移位触发器，以及第二开关单元，所述第一、第二开关单元均为MOS管，其中：
各个所述延时控制单元的移位触发器相互级联；各移位触发器均具有第一输入端、第二输入端以及输出端，除第一级的移位触发器的第一输入端连接外部的高/低电平触发信号输入端，用于接收外部输入的高/低电平触发信号外，其余各级移位触发器的第一输入端分别连接其前一级的移位触发器的输出端；第一级移位触发器的第一输入端还分别与各个第二开关单元的栅极连接；各移位触发器的第二输入端均连接一时钟控制器，各移位触发器的输出端还分别连接对应的第二开关单元的漏极以及对应的第一开关单元的栅极；各个第二开关单元的源极接地；
各个第一开关单元的漏极连接对应的输出通道，各个第一开关单元的源极连接对应的像素电极；
当第一级移位触发器的第一输入端接收到高电平触发信号时，各移位触发器根据所述时钟控制器产生的时钟控制信号的频率逐级产生预定延时的延迟控制信号，逐级打开相应的第一开关单元；当第一级移位触发器的第一输入端接收到低电平触发信号时，各移位触发器控制分别打开与其连接的第二开关单元，控制对应的第一开关单元关闭。
优选地，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
优选地，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；当所述输出通道为偶数个时，所述延时控制单元为n/2个，相互级联的所述移位触发器包括n/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，其中，n为自然数；
或者，当所述输出通道为奇数个时，所述延时控制单元为（n+1）/2个，相互级联的所述移位触发器包括（n+1）/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，第（n+1）/2级移位触发器的输出端连接第（n+1）/2个第一开关单元的栅极，其中，n为自然数。
优选地，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；所述延时控制单元为n个，相互级联的所述移位触发器为n级，每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端连接第1个第一开关单元的栅极，第2级移位触发器的输出端连接第2个第一开关单元的栅极，依次类推，第n级移位触发器的输出端连接第n个第一开关单元的栅极。
优选地，所述高/低电平触发信号为所述数据驱动IC输出的充电信号。
优选地，所述级联的移位触发器为所述数据驱动IC中的移位寄存器。
优选地，所述时钟控制器内置于所述数据驱动IC中。
本发明提出的一种LCD数据驱动IC输出补偿电路、补偿方法及液晶显示器，采用延迟控制单元对数据驱动IC输出的充电信号由两边向中间依次延时，以此补偿数据驱动IC至每一行像素电极之间的数据线的阻抗不匹配的问题，使得每个输出通道在某一行像素电极的充电时间是基本一致，在保证液晶显示器均匀显示画面的同时，由于数据线无需采用绕线方式，使得玻璃基板的走线空间小，更有利于液晶显示器的窄边框设计，COF（Chip On Film，覆晶薄膜）也可以采用更多的输出通道，降低了成本；也改善了所有输出通道同时打开时产生的EMI问题。
附图说明
图1是现有技术中数据驱动IC通过数据线连接像素区域的结构示意图；
图2是本发明LCD数据驱动IC输出补偿电路实施例中数据驱动IC通过数据线连接像素区域的结构示意图；
图3是本发明LCD数据驱动IC输出补偿电路实施例的结构示意图；
图4为本发明LCD数据驱动IC输出补偿电路实施例中各输出通道工作时序示意图；
图5是本发明LCD数据驱动IC输出补偿方法实施例流程示意图。
为了使本发明的技术方案更加清楚、明了，下面将结合附图作进一步详述。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明主要解决方案是：通过在数据驱动IC的输出通道上设置输出控制开关，并通过延迟控制单元根据各数据线的阻抗值，逐级打开各输出通道上的开关，从而使玻璃基板上每一行的各像素电极的充电时间相同，保证了画面显示的均匀性，数据线不需采用蛇形的走线方式，减小绕线空间，有利于液晶显示器的窄边框设计。
请一并参照图2及图3所示，图2为本发明数据驱动IC输出的数据线不需绕线，向像素电极充电的结构示意图。图3是本发明提出的数据驱动IC输出补偿电路结构示意图。
图2中，数据驱动IC30通过多条数据线（图中以n表示，n为自然数）20连接像素区域10，给像素区域10内的像素电极充电。
数据线20在从数据驱动IC30输出时，走线不做如图1所示的蛇形线，而是采用直线形式，此举节约了绕线所浪费的空间，使得液晶面板的边框可以做的更窄。但采用直线形式连接时，数据驱动IC30输出的每根数据线20的长度不同，其阻抗值也不一致，若数据驱动IC30的所有输出通道同时输出，数据信号通过每条数据线20给对应像素充电的时间不一致，阻抗值大的数据线20其充电时间相对短，从而使得受该数据驱动IC3控制的像素区域10的画面显示不均匀。为此，本发明通过延迟控制单元50控制每个输出通道的输出的时间，使每个输出通道的输出时间与对应数据线20的阻抗值匹配，保证每个输出通道在像素区域10某一行的像素电极的充电时间一致，从而得到显示均匀的画面。
具体如图3所示，该LCD数据驱动IC输出补偿电路包括数据驱动IC30、若干第一开关单元40以及若干延迟控制单元50，其中：
数据驱动IC30包括若干输出通道，若干输出通道分别通过数据线20与玻璃基板中对应行的像素电极连接，用于输出充电信号，为对应行的像素电极充电；
各个第一开关单元40，对应设置在每一输出通道上，并连接相应的延迟控制单元50，用于根据延迟控制单元50产生的延迟控制信号，控制该第一开关单元40所在的输出通道，将充电信号按预定延时输出；
各个延迟控制单元50，用于根据对应的数据线20的阻抗值产生对应的延迟控制信号，控制对应的第一开关单元40按预定延时开启，使每一像素电极的充电时间相等。
延时控制单元50包括移位触发器501，以及第二开关单元502，第一、第二开关单元40、502均为MOS管（Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体型场效应管），其中，第一开关单元40为NMOS管，第二开关单元502为PMOS管。
本实施例中各延时控制单元50的移位触发器501相互级联，各移位触发器501均具有第一输入端、第二输入端以及输出端，除第一级的移位触发器501的第一输入端连接外部的高/低电平触发信号输入端（Out on），用于接收外部输入的高/低电平触发信号外，其余各级移位触发器501的第一输入端分别连接其前一级的移位触发器501的输出端。
各移位触发器501的第二输入端均连接一时钟控制器；各移位触发器501的输出端还分别连接对应的第二开关单元502的漏极，以及还分别连接对应的第一开关单元40的栅极；各个第二开关单元502的源极接地。
此外，第一级的移位触发器501的第一输入端还分别连接各个第二开关单元502的栅极。
各个第一开关单元40的漏极连接对应的输出通道，各个第一开关单元40的源极连接对应的像素电极。
当第一级移位触发器501的第一输入端接收到高电平触发信号时，各移位触发器501根据时钟控制器产生的时钟控制信号的频率逐级产生预定延时的延迟控制信号，逐级打开相应的第一开关单元40；当第一级移位触发器501的第一输入端接收到低电平触发信号时，各移位触发器501控制分别打开与其连接的第二开关单元502，控制对应的第一开关单元40关闭。
本实施例以数据线20的阻抗值沿数据驱动IC30的两端向中间对称性的逐级减少为例进行说明，而阻抗最小的数据线20不一定是在COF中间的输出通道，由中间通道向两端，数据线20阻抗的增加也不一定对称，需要根据实际的阻抗分布对延时进行调整，才能达到最好的效果。
本实施例定义数据驱动IC30具有奇数个输出通道，并以此为例进行说明，也就是定义数据驱动IC30的输出通道n为奇数，n=2k-1，其中，k为自然数，2k-1个输出通道对应2k-1条数据线20，第一开关单元40对应为2k-1个；同时定义延时控制单元50为k个，相互级联的移位触发器501包括k级，每一级移位触发器501连接有一个第二开关单元502。第1级移位触发器501的输出端分别连接第1、第2k-1个第一开关单元40的栅极；第2级移位触发器501的输出端分别连接第2、第2k-2个第一开关单元40的栅极，依次类推，第k级移位触发器501的输出端连接第k个第一开关单元40的栅极。
数据线20的走线方式如图2所示，其阻抗的大小从两端向中间逐级对称减小。
第k条数据线20的从数据驱动IC30第k个通道输出，其在数据驱动IC30与像素区域10之间的路径最近，阻抗最小，左右的通道阻抗呈对称的逐次增大，第一条数据线20的阻抗值逐条减小至第k条数据线20，然后从第k+1条数据线20开始，其阻抗值逐条增大至第2k-1条数据线20，其中第1条数据线20与第2k-1那条数据线20的阻抗值相同，第2条数据线20与第2k-2那条数据线20的阻抗值相同，依次类推，第k-1条数据线20的阻抗值与第k+1条数据线20的阻抗值相同，第k条数据线20的阻抗值最小。这样对于每一行的像素电极而言，在延迟控制单元50不工作时，如果数据驱动IC30的每个输出通道同时输出信号，那么由第k个输出通道朝两边，充电的时间会逐渐减小，这样中间当显示同一灰阶时，显示的颜色会有差异。
通过延迟控制单元50的控制，调整数据驱动IC30每个输出通道的充电信号的输出时间，使得像素区域10中每一行的像素电极的充电时间相等，具体原理如下：
2k-1个第一开关单元40一一对应的控制2k-1条数据线20所在的输出通道的开关，第1个第一开关单元40位于数据驱动IC3的第1个输出通道上，用于控制第1条数据线20的开关，第2个第一开关单元40位于数据驱动IC30的第2个输出通道上，用于控制第2条数据线20的开关，依次类推，第k个第一开关单元40位于数据驱动IC30的第k个输出通道上，用于控制第k条数据线的20开关，第2k-1个第一开关单元40位于数据驱动IC30的第2k-1个输出通道上，用于控制第2k-1条数据线20的开关。
本实施例中移位触发器501可以为上升沿D触发器。
级联的移位触发器501为k级串联的上升沿D触发器501，每级上升沿D触发器501的输出端连接对应的第一开关单元40的栅极，用于控制对应的第一开关单元40的打开与关闭。
具体地，第1级上升沿D触发器501的输出端连接第1条和第2k-1条数据线20的第一开关单元40的栅极，第2级的输出端连接第2条和第2k-2条数据线20的第一开关单元40的栅极，依次类推，第k-1级输出端连接第k-1条和第k+1条数据线20的第一开关单元40的栅极，第k级的输出端连接第k条数据线20的第一开关单元40的栅极。
每个第二开关单元502的栅极连接第一级上升沿D触发器501的输入端，用于同时接收外部输入的高/低电电平触发信号。
每个第二开关单元502的漏极一一对应的连接第一开关单元40的栅极，即第1个第二开关单元502是漏极连接第1个第一开关单元40的栅极，第2个第二开关单元502是漏极连接第2个第一开关单元40的栅极，依次类推，第k个第二开关单元502漏极连接第k个第一开关单元40的栅极，第2k-1个第二开关单元502漏极连接第2k-1个第一开关单元40的栅极，所有第二开关单元502的源极接地。
图4为数据驱动IC30各输出通道的工作时序示意图，在级联的上升沿D触发器501的第二输入端即时钟控制信号输入端的时钟脉冲信号clk上升沿到来之时，上升沿D触发器501会发生翻转，其翻转的状态由第二输入端接收的Out on信号的电平高低来决定，在t1时刻之前，Out on信号为低电平，各上升沿D触发器501的输出端为低电平，所有第一开关单元40处于关闭状态，在t1时刻，Out on信号由低电平跃升到高电平，此时第1级上升沿D触发器501的第二输入端的时钟脉冲信号上升沿来到，第1级上升沿D触发器501发生翻转，第1级上升沿D触发器501的输出端翻转到高电平，并提供给第2级上升沿D触发器501的第二输入端，此时第1个第一开关单元40和第2k-1个第一开关单元40的栅极接收高电平，控制第1条数据线和第2k-1条数据线打开，给对应像素充电，在t2时刻，第2级上升沿D触发器501的第二输入端跃升为高电平，时钟脉冲信号在下一个上升沿来到时，第2级上升沿D触发器501的输出端翻转为高电平，此时第2个第一开关单元40和第2k-2个第一开关单元40的栅极接收高电平，控制第2条数据线和第2k-2条数据线打开，给对应像素充电，依次类推，在tk时刻，此时第k级上升沿D触发器501的输出端输出高电平，第k个第一开关单元40的栅极接收高电平，控制第k条数据线打开，至此，各延迟控制单元50控制每条数据线20的输出通道在适当时机打开，使得数据线20从两端向中间逐条打开，阻抗值的差异得到补偿，从而保证每个像素电极的充电时间一致。
在tm时刻，级联的上升沿D触发器501的第二输入端由高电平变为低电平，此时，所有数据线20所在的输出通道在第二开关单元502的下拉作用下瞬间关闭。
本实施例中数据驱动IC30和延迟控制单元50可以通过COF或者COG（chip on glass，玻璃上芯片封装）的方式压合在玻璃基板上。
对于数据驱动IC30具有偶数个输出通道即n=2k（其中，k为自然数）的情形，只是输出通道的个数不同，其数据驱动IC30输出补偿的基本原理与上述实施例相同，数据线20的阻抗值仍然是从两端向中间均匀减小，延迟控制单元50根据各数据线20的阻抗值，由时钟控制器控制产生相应的延迟控制信号，使数据驱动IC30输出的充电信号由两边向中间依次延时，以此补偿数据驱动IC30至每一行像素电极之间的数据线20的阻抗不匹配的问题，使得每个输出通道在某一行像素电极的充电时间基本一致。在其他实施例中，根据不同液晶面板走线的设计，其数据线20的阻抗值不一定是从两端向中间均匀减小，由中间向两端阻抗的增加不一定是对称的，波形的延时也会有差异，此时要根据实际的阻抗分布来对输出的波形延时进行调整，例如每级上升沿D触发器501中可包含一个或多个串联的上升沿D触发器501，从而得到适应的补偿，使得每个像素电极的充电时间一致。
其中，级联的上升沿D触发器501也可以共享于数据驱动IC30中的移位寄存器，时钟控制器也可以内置于数据驱动IC30中，还可以利用数据驱动IC30中的T-CON，将移位控制器的第二输入端即时钟控制信号接收端连接T-CON（time-control，时序控制器）输出端，由T-CON提供，由于此时时钟信号频率较高，因此也可以通过控制级联的上升沿D触发器501的时钟信号clk的频率，来得到适应的Δt，从而保证每个像素电极的充电时间一致，达到最佳的现实画面。同时，还可以通过控制clk的频率，或是相隔更多的D触发器来控制输出通道延时的长短。
此外，级联的上升沿D触发器501的第一输入端接收的高/低电平触发信号也可以为数据驱动IC输出的充电信号。
本实施例将每个输出通道输出的时间进行调整，使每个通道的输出时间与对应数据线的阻抗值匹配，保证每个通道在某一行的充电时间是一致，从而得到显示均匀的画面。这样就达到了不用蛇形线来做输出补偿，提高了玻璃基板的利用率，玻璃的边框可以做得更窄，数据驱动IC3可以采用更多的输出通道，降低了成本。而且通过这种方式，也改善了所有的通道同时打开产生EMI的问题。
根据以上优选实施例的原理，还可以在其基础上，定义延时控制单元50的个数与数据驱动IC30的输出通道一一对应的方式，即在数据驱动IC30具有n个通道时，延时控制单元50也为n个，相互级联的移位触发器501为n级，第1级移位触发器501的输出端连接第1个第一开关单元40的栅极，第2级移位触发器501的输出端连接第2个第一开关单元40的栅极，依次类推，第n级移位触发器501的输出端连接第n个第一开关单元40的栅极，而其他工作方式与原理均与前述优选实施例相同。
如图5所示，本发明还提出一种LCD数据驱动IC输出补偿方法，包括：
步骤S101，延迟控制单元根据数据驱动IC与玻璃基板上对应行的像素电极之间的各数据线的阻抗值，由时钟控制器控制产生相应的延迟控制信号，发送至数据驱动IC对应的输出通道上的第一开关单元；
步骤S102，数据驱动IC对应的输出通道上的第一开关单元根据延迟控制信号，控制该第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极，使对应行的每一像素电极的充电时间相等。
本发明LCD数据驱动IC输出补偿方法中，当延迟控制单元接收到高电平触发信号时，各延迟控制单元根据所述时钟控制器输出的时钟控制信号的频率，产生相应的延迟控制信号，逐级打开对应的第一开关单元，使所述对应第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极；当延迟控制单元接收到低电平触发信号时，各延迟控制单元控制关闭对应的第一开关单元。
本发明LCD数据驱动IC输出补偿方法中，数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少，而根据不同液晶面板走线的设计，其数据线的阻抗值不一定是从两端向中间均匀减小，由中间向两端阻抗的增加不一定是对称的，波形的延时也会有差异，此时要根据实际的阻抗分布来对输出的波形延时进行调整，才能达到最好的效果。数据驱动IC输出补偿的基本原理请参照上述输出补偿电路具体实施，在此不赘述。
此外，本发明还提出一种液晶显示器，该液晶显示器包括上述实施例所述的LCD数据驱动IC输出补偿电路，在此不再赘述。
本发明LCD数据驱动IC输出补偿电路、补偿方法及液晶显示器，采用延迟控制单元对数据驱动IC输出的充电信号由两边向中间依次延时，以此补偿数据驱动IC至每一行像素电极之间的数据线的阻抗不匹配的问题，使得每个输出通道在某一行像素电极的充电时间是基本一致，在保证液晶显示器均匀显示画面的同时，由于数据线无需采用绕线方式，使得玻璃基板的走线空间小，更有利于液晶显示器的窄边框设计，COF也可以采用更多的输出通道，降低了成本；也改善了所有输出通道同时打开时产生的EMI问题。
以上所述仅为本发明的优选实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种LCD数据驱动IC输出补偿电路，其特征在于，包括：数据驱动IC、若干第一开关单元以及延迟控制单元，其中：
    所述数据驱动IC包括若干输出通道，所述若干输出通道分别通过数据线与玻璃基板中对应行的像素电极连接，用于输出充电信号，为所述对应行的像素电极充电；
    所述第一开关单元，对应设置在每一所述输出通道上，并连接相应的所述延迟控制单元，用于根据所述延迟控制单元产生的延迟控制信号，控制该第一开关单元所在的输出通道，将所述充电信号按预定延时输出；
    所述延迟控制单元，用于根据对应的所述数据线的阻抗值产生对应的延迟控制信号，控制对应的所述第一开关单元按预定延时开启，使每一所述像素电极的充电时间相等。
  2. 根据权利要求1所述的LCD数据驱动IC输出补偿电路，其特征在于，所述延时控制单元包括移位触发器，以及第二开关单元，所述第一、第二开关单元均为MOS管，其中：
    各个所述延时控制单元的移位触发器相互级联；各移位触发器均具有第一输入端、第二输入端以及输出端，除第一级的移位触发器的第一输入端连接外部的高/低电平触发信号输入端，用于接收外部输入的高/低电平触发信号外，其余各级移位触发器的第一输入端分别连接其前一级的移位触发器的输出端；第一级移位触发器的第一输入端还分别与各个第二开关单元的栅极连接；各移位触发器的第二输入端均连接一时钟控制器，各移位触发器的输出端还分别连接对应的第二开关单元的漏极以及对应的第一开关单元的栅极；各个第二开关单元的源极接地；
    各个第一开关单元的漏极连接对应的输出通道，各个第一开关单元的源极连接对应的像素电极；
    当第一级移位触发器的第一输入端接收到高电平触发信号时，各移位触发器根据所述时钟控制器产生的时钟控制信号的频率逐级产生预定延时的延迟控制信号，逐级打开相应的第一开关单元；当第一级移位触发器的第一输入端接收到低电平触发信号时，各移位触发器控制分别打开与其连接的第二开关单元，控制对应的第一开关单元关闭。
  3. 根据权利要求2所述的LCD数据驱动IC输出补偿电路，其特征在于，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
  4. 根据权利要求3所述的LCD数据驱动IC输出补偿电路，其特征在于，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；当所述输出通道为偶数个时，所述延时控制单元为n/2个，相互级联的所述移位触发器包括n/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，其中，n为自然数；
    或者，当所述输出通道为奇数个时，所述延时控制单元为（n+1）/2个，相互级联的所述移位触发器包括（n+1）/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，第（n+1）/2级移位触发器的输出端连接第（n+1）/2个第一开关单元的栅极，其中，n为自然数。
  5. 根据权利要求3所述的LCD数据驱动IC输出补偿电路，其特征在于，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；所述延时控制单元为n个，相互级联的所述移位触发器为n级，每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端连接第1个第一开关单元的栅极，第2级移位触发器的输出端连接第2个第一开关单元的栅极，依次类推，第n级移位触发器的输出端连接第n个第一开关单元的栅极。
  6. 根据权利要求2所述的LCD数据驱动IC输出补偿电路，其特征在于，所述高/低电平触发信号为所述数据驱动IC输出的充电信号。
  7. 根据权利要求2所述的LCD数据驱动IC输出补偿电路，其特征在于，所述级联的移位触发器为所述数据驱动IC中的移位寄存器。
  8. 根据权利要求6所述的LCD数据驱动IC输出补偿电路，其特征在于，所述时钟控制器内置于所述数据驱动IC中。
  9. 一种LCD数据驱动IC输出补偿方法，其特征在于，包括以下步骤：
    延迟控制单元根据数据驱动IC与玻璃基板上对应行的像素电极之间的各数据线的阻抗值，由时钟控制器控制产生相应的延迟控制信号，发送至所述数据驱动IC对应的输出通道上的第一开关单元；
    所述数据驱动IC对应的输出通道上的第一开关单元根据所述延迟控制信号，控制该第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极，使对应行的每一所述像素电极的充电时间相等。
  10. 根据权利要求9所述的LCD数据驱动IC输出补偿方法，其特征在于，还包括：当所述延迟控制单元接收到高电平触发信号时，各延迟控制单元根据所述时钟控制器输出的时钟控制信号的频率，产生相应的延迟控制信号，逐级打开对应的第一开关单元，使所述对应第一开关单元所在的输出通道按预定延时输出充电信号至对应的像素电极；当所述延迟控制单元接收到低电平触发信号时，各延迟控制单元控制关闭对应的第一开关单元。
  11. 根据权利要求9所述的LCD数据驱动IC输出补偿方法，其特征在于，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
  12. 一种液晶显示器，包括数据驱动IC输出补偿电路，其特征在于，所述数据驱动IC输出补偿电路包括：数据驱动IC、若干第一开关单元以及延迟控制单元，其中：
    所述数据驱动IC包括若干输出通道，所述若干输出通道分别通过数据线与玻璃基板中对应行的像素电极连接，用于输出充电信号，为所述对应行的像素电极充电；
    所述第一开关单元，对应设置在每一所述输出通道上，并连接相应的所述延迟控制单元，用于根据所述延迟控制单元产生的延迟控制信号，控制该第一开关单元所在的输出通道，将所述充电信号按预定延时输出；
    所述延迟控制单元，用于根据对应的所述数据线的阻抗值产生对应的延迟控制信号，控制对应的所述第一开关单元按预定延时开启，使每一所述像素电极的充电时间相等。
  13. 根据权利要求12所述的液晶显示器，其特征在于，所述延时控制单元包括移位触发器，以及第二开关单元，所述第一、第二开关单元均为MOS管，其中：
    各个所述延时控制单元的移位触发器相互级联；各移位触发器均具有第一输入端、第二输入端以及输出端，除第一级的移位触发器的第一输入端连接外部的高/低电平触发信号输入端，用于接收外部输入的高/低电平触发信号外，其余各级移位触发器的第一输入端分别连接其前一级的移位触发器的输出端；第一级移位触发器的第一输入端还分别与各个第二开关单元的栅极连接；各移位触发器的第二输入端均连接一时钟控制器，各移位触发器的输出端还分别连接对应的第二开关单元的漏极以及对应的第一开关单元的栅极；各个第二开关单元的源极接地；
    各个第一开关单元的漏极连接对应的输出通道，各个第一开关单元的源极连接对应的像素电极；
    当第一级移位触发器的第一输入端接收到高电平触发信号时，各移位触发器根据所述时钟控制器产生的时钟控制信号的频率逐级产生预定延时的延迟控制信号，逐级打开相应的第一开关单元；当第一级移位触发器的第一输入端接收到低电平触发信号时，各移位触发器控制分别打开与其连接的第二开关单元，控制对应的第一开关单元关闭。
  14. 根据权利要求13所述的液晶显示器，其特征在于，所述数据线的阻抗值沿数据驱动IC的两端向中间对称性的逐级减少。
  15. 根据权利要求14所述的液晶显示器，其特征在于，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；当所述输出通道为偶数个时，所述延时控制单元为n/2个，相互级联的所述移位触发器包括n/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，其中，n为自然数；
    或者，当所述输出通道为奇数个时，所述延时控制单元为（n+1）/2个，相互级联的所述移位触发器包括（n+1）/2级；每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端分别连接第1、第n个第一开关单元的栅极；第2级移位触发器的输出端分别连接第2、第n-1个第一开关单元的栅极，依次类推，第（n+1）/2级移位触发器的输出端连接第（n+1）/2个第一开关单元的栅极，其中，n为自然数。
  16. 根据权利要求14所述的液晶显示器，其特征在于，所述数据驱动IC具有n个输出通道，所述第一开关单元对应为n个；所述延时控制单元为n个，相互级联的所述移位触发器为n级，每一级移位触发器连接有一个第二开关单元，第1级移位触发器的输出端连接第1个第一开关单元的栅极，第2级移位触发器的输出端连接第2个第一开关单元的栅极，依次类推，第n级移位触发器的输出端连接第n个第一开关单元的栅极。
  17. 根据权利要求13所述的液晶显示器，其特征在于，所述高/低电平触发信号为所述数据驱动IC输出的充电信号。
  18. 根据权利要求13所述的液晶显示器，其特征在于，所述级联的移位触发器为所述数据驱动IC中的移位寄存器。
  19. 根据权利要求18所述的液晶显示器，其特征在于，所述时钟控制器内置于所述数据驱动IC中。
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