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WO2011129050A1 - Circuit intégré à semiconducteur et système de capture d'image incluant celui-ci - Google Patents

Circuit intégré à semiconducteur et système de capture d'image incluant celui-ci Download PDF

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Publication number
WO2011129050A1
WO2011129050A1 PCT/JP2011/001247 JP2011001247W WO2011129050A1 WO 2011129050 A1 WO2011129050 A1 WO 2011129050A1 JP 2011001247 W JP2011001247 W JP 2011001247W WO 2011129050 A1 WO2011129050 A1 WO 2011129050A1
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WIPO (PCT)
Prior art keywords
signal
code
image sensor
integrated circuit
semiconductor integrated
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Ceased
Application number
PCT/JP2011/001247
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English (en)
Japanese (ja)
Inventor
村山謙太朗
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Panasonic Corp
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Panasonic Corp
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Publication date
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2101/00—Still video cameras

Definitions

  • the present invention relates to an imaging system including an image sensor and a receiving circuit, and particularly belongs to a technique effective when applied to an imaging system of a camera such as a digital still camera.
  • the number of pixels of the image sensor is an important factor that determines the image quality. Due to the improvement in the number of pixels, it is required to increase the speed of the interface between the image sensor and the system LSI that controls image processing.
  • the above test pulse is for adjusting the phase of data acquisition in the DSP, and does not indicate at what timing the video signal is transmitted from the image sensor. That is, the DSP needs to know at what timing the video signal is sent from the image sensor, but it is difficult to know such timing from the test pulse.
  • a dedicated pin for receiving the test pulse is required for the DSP.
  • the present invention makes it possible to determine whether or not the data signal output from the image sensor on the DSP side is a video signal without adding a signal line between the image sensor and the DSP. Is an issue.
  • An imaging system includes a pixel array including a collection of light receiving elements, a code generation unit that generates a code sequence including an error correction code, and a signal output from the pixel array and a code generated by the code generation unit
  • An image sensor having a transmission interface for transmitting a series to the outside and a semiconductor integrated circuit for processing an external signal output from the image sensor, the semiconductor integrated circuit receiving an external signal output from the image sensor A reception interface, a signal delay unit that delays the received external signal and outputs the first signal, an error correction unit that performs error correction of the code sequence of the first signal, and a processing result of the error correction unit
  • an image signal determination unit that determines whether or not the external signal is an image signal.
  • a data signal including an error correction code is repeatedly transmitted from the image sensor to the semiconductor integrated circuit during part or all of the horizontal and / or vertical blanking period, and the semiconductor integrated circuit is based on the error correction processing result. It is then determined whether the data signal is an image signal.
  • the present invention it is possible to determine whether or not it is a video signal from the data signal itself output from the image sensor without providing an additional signal line between the image sensor and the DSP.
  • FIG. 1 is a configuration diagram of an imaging system according to the first embodiment.
  • FIG. 2 is a schematic diagram of a data transmission cycle of the image sensor.
  • FIG. 3 is a timing chart of the data signal and clock signal of each delay amount after the phase adjustment is completed.
  • FIG. 4 is a timing chart of the data signal and clock signal of each delay amount before the phase adjustment is completed.
  • FIG. 5 is a flowchart of signal delay amount increase / decrease in the signal delay unit.
  • FIG. 6 is a flowchart for making a phase adjustment possible from a state where the phase is completely out of phase.
  • FIG. 7 is a configuration diagram of an imaging system according to the second embodiment.
  • FIG. 8 is a timing chart of data signals and clock signals output from the image sensor.
  • FIG. 1 shows a configuration of an imaging system according to the first embodiment.
  • the video system according to the present embodiment includes an image sensor 1 and a system LSI 2 that are connected to each other via a data signal line 104 and a clock signal line 105.
  • a pixel array 101 and a code generation unit with an error correction code addition function (hereinafter simply referred to as “code generation unit”) 102 are connected to a transmission interface 103.
  • the transmission interface 103 does not always output pixel data, but is generated from the code generation unit 102 during a part or all of the invalid period for generating an image, which is generally called a blanking period.
  • Send a signal It is possible to control how much of the invalid period is used to transmit the error correction signal, and put the imaging system in the power saving mode during the period when neither the error correction signal nor the pixel data is output. Is also possible.
  • the reception interface 201 receives an external signal output from the image sensor 1.
  • the signal delay unit 202 can generate three types of delays: a relatively large delay, a relatively small delay, and an intermediate delay between the signals received by the reception interface 201.
  • Each time-delayed data signal is connected to a standard delay FF 203, a small delay FF 204, and a large delay FF 205, respectively.
  • FF is an abbreviation for flip-flop. Since these FFs are connected to the same clock signal, the latch operation is performed at timings before, in the middle, and after the data signal.
  • the information latched by the small delay FF 204 and the large delay FF 205 is then held by the shift registers 207 and 208.
  • the number of bits of the shift registers 207 and 208 is adjusted to the number of bits per pixel in the pixel array 101.
  • the shift registers 207 and 208 are also configured as 8-bit shift registers.
  • the signal latched in the standard delay FF 203 is subjected to video processing such as pre-processing and YC processing through the image processing unit 210, and is recorded on an SD memory card (not shown) or the like and input to the error correction unit 206. .
  • the error correction unit 206 always looks at the reception result of the standard delay FF 203 and performs error correction processing on the code sequence of the signal latched in the standard delay FF 203.
  • Each code sequence includes a data part and an error correction code part, and is continuously transmitted from the image sensor 1 in the following code output area.
  • the error correction unit 206 notifies the delay adjustment unit 209 of information regarding whether or not there is an error in the code sequence and the position information of the error in the code sequence.
  • the delay adjustment unit 209 receives the notification from the error correction unit 206, determines whether or not the delay control is necessary by means described later, and if an error has occurred and the delay control is necessary, the signal delay The delay time is increased or decreased for the unit 202.
  • FIG. 2 is a schematic two-dimensional representation of the signal of the image sensor 1 output horizontally for each row.
  • the data transmission cycle of the image sensor 1 is roughly classified into two, a pixel output period and a vertical blanking period. A period during which valid video information is actually transmitted is a pixel output period, and video information is not included in the vertical blanking period.
  • the image sensor 1 stops outputting to reduce power, and then continuously outputs a signal including an error correction code in the code output area.
  • the data transmission cycle of the image sensor 1 is not limited to this example, and may further include a blanking period in the horizontal direction or no power saving area.
  • the image signal determination unit 211 determines whether the data signal sent from the image sensor 1 is an image signal based on the processing result of the error correction unit 206. Specifically, as a first determination method, by storing information on how many cycles the effective image area is reached in the data portion in each code sequence, the image signal determination unit 211 is based on the information. It is possible to detect the timing at which the image signal is sent and prepare the operation of each internal circuit such as the image processing unit 210.
  • the image signal determination unit 211 may determine the effective image region based on whether or not code sequence errors occur continuously.
  • the image sensor 1 and the system LSI 2 both transmit and receive an error correction code obtained by a predetermined calculation formula, so that the result of the error correction decoding operation is always error-free.
  • the value of each pixel of the image array 101 is transferred in the effective image area.
  • the value of the pixel is a result of light reception by the image array 101. For example, in a situation where intense light enters and is saturated, it becomes 0xFF, and in a situation where no light enters at all, it becomes 0x00. For this reason, the value of each pixel depends on the subject to be photographed and becomes a virtually random value.
  • the value is set to 1 when a fixed value is output so that the first area of the effective image area always has an error, or when the pixel data coincides with the error correction code. It is possible to take a countermeasure such that an error is intentionally detected by shifting.
  • the effective image area and the code output area appear alternately. Therefore, an error has occurred in the code output area as soon as the error correction unit 206 has reached the effective image area. That is, when errors occur continuously in the error correction unit 206, it can be determined that it is an effective image area.
  • the reliability of image region determination can be further increased.
  • FIG. 3 is a timing chart of the data signal and clock signal of each delay amount after the phase adjustment is completed.
  • the data signal becomes effective in order from the smallest delay amount. Since each FF latches the data signal at the rising edge of the clock signal, in the case of FIG. 3, any FF can latch the data signal at the correct valid timing.
  • FIG. 4 is a timing chart of the data signal and clock signal of each delay amount before the phase adjustment is completed.
  • a data signal with a small delay amount is effective at the rising edge of the clock signal. That is, valid data (for example, “0”) is latched if the data signal has a small delay amount, and invalid data (for example, “1”) is latched if the data signal has other delay amounts. Since the system LSI 2 may malfunction in this state, the delay adjustment unit 209 adjusts the delay amount in the signal delay unit 202 as follows.
  • FIG. 5 shows a flow of increasing / decreasing the signal delay amount in the signal delay unit 202.
  • the error correction unit 206 performs error correction processing of the code sequence. If there is an error, the delay adjustment unit 209 compares the error correction processing target code sequence with the outputs of the shift registers 207 and 208, respectively. Based on this, the signal delay amount in the signal delay unit 202 is increased or decreased. For example, it is assumed that the code sequence subject to error correction is “10111011” and there is an error in the third bit. Assume that the outputs of the shift registers 207 and 208 are “10011011” and “10111011”, respectively.
  • the delay adjustment unit 209 compares the third bit of the code sequence subject to error correction processing with the third bit of the output of the shift registers 207 and 208, and the output of the shift register 207 having a different bit value is correct. That is, it is determined that the delay amount of the data signal should be reduced. Then, the delay adjustment unit 209 instructs the signal delay unit 202 to reduce the signal delay amount as a whole. As a result, the phase of the data signal changes from the state shown in FIG. 4 to the state shown in FIG. 3, and the data signal can be correctly latched in the system LSI 2.
  • the error correction unit 206 always decodes the data signal that is sent and detects the code output area. This period is, for example, two screens, and if waiting for this period, the code output area should elapse at least once. Strictly speaking, the waiting time for the code output area to elapse once may be shorter than two screens, but for simplification of explanation, two screens are waited here. If the code output area can be detected at this point, it is a state in which the approximate phase adjustment has been performed, and thereafter the normal phase adjustment described above may be performed.
  • the delay time is shifted as a whole to search for a delay time that can be detected by the code output area.
  • a method of implementing this brute force a method of starting from a predetermined initial value or a method of starting from the minimum value of the adjustment range can be considered, but as long as the entire range of the adjustment range can be covered as a result, The method may be used.
  • the present embodiment it is possible to determine whether or not the data signal is a video signal from the error correction processing result of the data signal output from the image sensor 1, and to adjust the latch timing of the data signal.
  • FIG. 7 shows a configuration of an imaging system according to the second embodiment.
  • code generation unit with a code recording function (hereinafter simply referred to as “code generation unit”) 102 stores a plurality of predetermined code sequences, and corresponds to the state of the image sensor 1. An appropriate code sequence is output.
  • the bit width of the data signal line 104 is 8 bits, and the transmission interface 103 transmits the data signal by shifting the timing bit by bit from the MSB of the data signal line 104 in order.
  • the signal delay unit 202 can generate three types of delays, that is, a relatively large delay, a relatively small delay, and an intermediate delay for each bit of the signal received by the reception interface 201. .
  • the system LSI 2 has three buses: a bus max having a relatively large delay, a bus min having a relatively small delay, and a bus type having an intermediate delay. These buses are connected to latch logic with a signal line selection function (hereinafter simply referred to as “latch logic”) 213, 214, and 215, respectively.
  • the latch logics 213, 214, and 215 have a function of latching a data signal from the MSB of each bus and sending a signal to the subsequent stage for each cycle.
  • FIG. 8 is a timing chart of data signals and clock signals output from the image sensor 1.
  • the code generation unit 102 stores seven patterns of 8-bit codes from code A to code G.
  • the code A consists of 8 bits A0, A1, A2, A3, A4, A5, A6 and A7.
  • the transmission interface 103 When outputting the code A in the code output area, the transmission interface 103 outputs A0 to Data [7], which is the most significant bit of the data signal 104, in the first cycle.
  • A1 is output to the second Data [6] from the top.
  • A7 is finally output to Data [0].
  • the same output is performed for the code B and thereafter, and after the code G is finally output, the same output is repeated from the code A. Therefore, error correction codes are scattered over all bits of the data bus.
  • the latch logics 213, 214, and 215 send signals to the subsequent stage in order from the MSB, for example, assuming that A0 starts the operation to send to the subsequent stage at the timing of Data [7], the code A is finally sent to the subsequent stage. Will be. If B0 is at the timing of Data [7], the code B is sent to the subsequent stage. As described above, if the image sensor 1 transmits a code over a plurality of bits bus according to a predetermined rule and the system LSI 2 receives the code according to the rule, the original code can be restored.
  • the signal delay is increased or decreased for each bit. That is, the delay adjustment unit 209 controls the signal delay unit 202 so that the signal delay amount of Data [5] is reduced when there is an error in the third bit as in the example shown in FIG.
  • the phase of the circuit according to the first embodiment can be reduced with a circuit scale smaller than simply arranging the configuration according to the bit width. Adjustments can be made.
  • the bit position of the code is uniquely determined as the bit of the data signal line, and it is advantageous to perform the error correction calculation to shift every one cycle.
  • the imaging system according to the present invention can determine whether or not it is a video signal from the data signal itself output from the image sensor without providing an additional signal line between the image sensor and the DSP. Therefore, it is useful as a digital video camera or a digital still camera that requires moving images or continuous shooting.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un système de capture d'image qui détermine, à partir d'un signal de données délivrée par un capteur d'image, si le signal de données est ou non lui-même un signal d'image vidéo sans disposer une ligne de signal supplémentaire entre le capteur d'image et un DSP. Le système de capture d'image comprend un capteur d'image (1), comprenant en outre un réseau de pixels (101), une unité génératrice de codage (102) et une interface de transmission (103) ; et un circuit intégré à semiconducteur (102) qui traite un signal externe délivré par le capteur d'image (101). Le circuit intégré à semiconducteur (2) comprend en outre une interface de réception (201) qui reçoit le signal externe délivré par le capteur d'image (1) ; une unité de retard de signal (202) qui retarde le signal externe reçu et délivre un premier signal ; une unité de correction d'erreur (206) qui effectue une correction d'erreur d'une séquence de codage du premier signal ; et une unité de détermination de signal d'image (211) qui détermine si le signal externe est ou non un signal d'image en se basant sur le résultat du traitement de l'unité de correction d'erreur (206).
PCT/JP2011/001247 2010-04-12 2011-03-03 Circuit intégré à semiconducteur et système de capture d'image incluant celui-ci Ceased WO2011129050A1 (fr)

Applications Claiming Priority (2)

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JP2010091472A JP2011223391A (ja) 2010-04-12 2010-04-12 半導体集積回路およびそれを備えた撮像システム
JP2010-091472 2010-04-12

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WO2011129050A1 true WO2011129050A1 (fr) 2011-10-20

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JP6488844B2 (ja) * 2015-04-14 2019-03-27 富士ゼロックス株式会社 制御装置及び画像形成装置
US11184530B2 (en) 2018-09-12 2021-11-23 Hitachi Kokusai Electric Inc. Drive substrate for camera and broadcast camera

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06225273A (ja) * 1993-01-25 1994-08-12 Matsushita Electric Ind Co Ltd 誤り訂正装置
JP2009147894A (ja) * 2007-11-22 2009-07-02 Sony Corp 信号送信装置及び信号送信方法
JP2010098436A (ja) * 2008-10-15 2010-04-30 Canon Inc 撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06225273A (ja) * 1993-01-25 1994-08-12 Matsushita Electric Ind Co Ltd 誤り訂正装置
JP2009147894A (ja) * 2007-11-22 2009-07-02 Sony Corp 信号送信装置及び信号送信方法
JP2010098436A (ja) * 2008-10-15 2010-04-30 Canon Inc 撮像装置

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