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WO2009110715A2 - Boucle à verrouillage de phase pourvue d'un élément de réajustement permettant d'éliminer la gigue dans un diviseur de fréquence variable - Google Patents

Boucle à verrouillage de phase pourvue d'un élément de réajustement permettant d'éliminer la gigue dans un diviseur de fréquence variable Download PDF

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Publication number
WO2009110715A2
WO2009110715A2 PCT/KR2009/001015 KR2009001015W WO2009110715A2 WO 2009110715 A2 WO2009110715 A2 WO 2009110715A2 KR 2009001015 W KR2009001015 W KR 2009001015W WO 2009110715 A2 WO2009110715 A2 WO 2009110715A2
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WO
WIPO (PCT)
Prior art keywords
output
frequency
divider
phase
prescaler
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2009/001015
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English (en)
Korean (ko)
Other versions
WO2009110715A3 (fr
Inventor
이정철
황명운
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FCI Inc Korea
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FCI Inc Korea
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Filing date
Publication date
Application filed by FCI Inc Korea filed Critical FCI Inc Korea
Publication of WO2009110715A2 publication Critical patent/WO2009110715A2/fr
Publication of WO2009110715A3 publication Critical patent/WO2009110715A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Definitions

  • the present invention relates to a phase locked loop (PLL). More specifically, the output of a program divider for dividing a phase of a voltage controlled oscillator output signal is retimed and transmitted to a phase detector for comparison.
  • the present invention relates to a phase-locked loop provided with a retiming unit for jitter removal of a program divider, which can remove in-band noise caused by output jitter of a divider.
  • the phase locked loop 100 detects a phase difference between an input signal and an output signal and controls a voltage controlled oscillator (VCO) to fix the frequency of the output signal at a constant level.
  • VCO voltage controlled oscillator
  • the reference divider 110 for supplying a stable reference frequency
  • the phase detector 120 for outputting a pulse by comparing the phase of the output frequency divided through the reference frequency and the main divider, and in proportion to the pulse width
  • a charge pump 130 for supplying charge
  • a loop filter 140 for varying the voltage by the change of the accumulated charge amount
  • a voltage controlled oscillator 150 for outputting a specific frequency by the variable voltage
  • a reference divider Adaptive frequency control unit 160 for detecting a frequency by using the output of the output and the main divider, and the output frequency of the voltage-controlled oscillator is fed back and divided and transmitted to the phase detector Servings is configured to include the period (170).
  • the reference divider 100 is composed of a temperature compensated X-tal oscillator (TCXO) for supplying a stable reference frequency (f ref ) without being influenced by an external temperature
  • the phase detector PFD: Phase Frequency Detector (120) is configured to compare the reference frequency of the TCXO divided by the reference divider and the output frequency divided by the main divider and output a pulse string corresponding to the difference.
  • the charge pump 130 pushes or pulls by the amount of charge corresponding to the pulse width output from the phase detector, and accumulates and discharges charges in a capacitor disposed in parallel to the loop filter 140. It is configured to cause a change in the amount of charge and to supply a variable voltage of the voltage controlled oscillator 150 accordingly.
  • the voltage controlled oscillator (VCO) 150 is configured to output a specific frequency by a variable input voltage in the loop filter.
  • the adaptive frequency calibration unit (AFC) 160 adjusts the frequency of the voltage controlled oscillator (VCO), and the frequency of the reference frequency divider (161) divided by 1 / R (f R2 ) and 1 A frequency comparator 163 for comparing the output frequency f N2 of the main frequency divider 162 divided by / N, a pumping voltage monitoring circuit 165 for monitoring the voltage level V cp of the charge pump, And a state machine 164 for providing a frequency AFC out of a predetermined bit to the voltage controlled oscillator and controlling the voltage controlled oscillators GW1 and GW2 by the frequency detected by the frequency comparator.
  • the main divider 170 receives the output frequency f out of the voltage controlled oscillator and feeds back the prescaler 171 to set the division ratios in advance, and dynamically divides the division ratios of the prescaler. and the output frequency of the voltage controlled oscillator 150, a ratio of the variable frequency divider (f out), the program divider which frequency divider 172 and a Sigma dividing provide data to the programmable frequency divider for the frequency division ratio variable-delta And a modulator (SDM: ⁇ - ⁇ Modulator) 173.
  • SDM ⁇ - ⁇ Modulator
  • phase-locked loop PLL
  • FMN2 phase detector
  • the voltage controlled oscillator (VCO) of the voltage divider (VCO) is caused by static phase error and jitter or noise of the sigma-delta modulator (SDM) generated at the output of the main divider, in particular the program divider.
  • SDM sigma-delta modulator
  • the technical problem to be solved by the present invention is the phase generated by the output terminal and the program divider of the voltage controlled oscillator by retiming and transmitting the output frequency of the voltage-controlled oscillator which has been divided in the prescaler and the program divider before transmitting to the phase detector.
  • the present invention provides a phase locked loop having a retimer for jitter elimination of a program divider capable of eliminating errors and jitter to improve performance of in-band noise.
  • the phase locked loop provided with a jitter eliminating retiming unit for the program divider for achieving the above technical problem is a phase locked loop (PLL) for fixing the output frequency constant by comparing the output frequency of the voltage controlled oscillator with a reference frequency.
  • a main divider for feeding back the output frequency F VCO of the voltage controlled oscillator and transmitting the output frequency to which the division is completed to a retiming unit;
  • a retiming unit for retiming the output frequency divided by the main frequency divider and transmitting the phase frequency to the phase detector for phase comparison.
  • the main divider may include: a prescaler receiving and feeding back an output frequency (F VCO ) of the voltage controlled oscillator and dividing at a dynamically varying division ratio; A program divider which divides the output frequency divided by the prescaler and transmits the divided frequency to the retiming unit; And a sigma-delta modulator for providing division data to the program divider for varying the division ratio.
  • F VCO output frequency
  • the program divider may include: a first counter which receives an output frequency divided by the prescaler and divides the divided frequency by a division ratio (1 / N) of a program divider and transmits the divided output frequency to a retiming unit; A second counter that receives the output frequency divided by the prescaler and counts pulses to change the division ratio of the prescaler; And a controller for generating a control signal for changing the division ratio of the prescaler based on the output of the first counter and the output of the second counter, and outputting the control signal to the prescaler.
  • the retiming unit may further include: a first flip flop to which an output of the first counter is input; A delay cell for delaying an output frequency F VCO of the voltage controlled oscillator; And a second flip-flop for receiving an output of the first flip-flop, an output of the delay cell as a clock signal, and transmitting a retimed signal to the phase detector.
  • the first flip-flop is configured to receive the output of the prescaler as a clock signal, receive the output of the program divider divided by the first counter as an input signal, and retime the output to the second flip-flop. It is characterized by.
  • the present invention removes jitter in the main divider by retiming the output frequency of the voltage-controlled oscillator in the main divider immediately before phase comparison with the reference frequency. Compared with the phase of, the in-band noise performance can be significantly improved.
  • 1 is a configuration diagram of a conventional phase locked loop
  • FIG. 2 is a block diagram of a phase locked loop having a retiming unit for removing jitter of a program divider according to the present invention
  • FIG. 3 is a detailed configuration diagram of the retiming unit according to the present invention.
  • FIG. 4 is a waveform diagram of a measurement result of in-band phase noise in a conventional phase locked loop.
  • FIG. 5 is a waveform diagram of measurement results of in-band phase noise in a phase-locked loop retimed according to the present invention.
  • the phase-locked loop 200 having a retiming unit for jitter removal of a program divider includes a reference divider 210 for supplying a stable reference frequency, and a reference.
  • Phase detector 220 for outputting a pulse by comparing the phase of the output frequency divided through the frequency and the main divider, a charge pump 230 for supplying charges in proportion to the pulse width, and the amount of charge accumulated
  • the voltage controlled oscillator 250 for outputting a specific frequency by the variable voltage, and the output of the reference divider and the output of the main divider.
  • An adaptive frequency controller 260 for detecting a frequency, a main divider 270 for feeding back and dividing an output frequency of the voltage controlled oscillator, and an output frequency F VCO of a voltage controlled oscillator divided in the main divider. It is configured to include a retiming unit 300 for retiming and transmit to the phase detector.
  • the reference divider 210, the phase detector 220, the charge pump 230, the loop filter 240, the voltage controlled oscillator 250, and the adaptive frequency controller 260 are conventional. Since it is configured in the same manner as the phase-locked loop, a detailed description thereof will be omitted.
  • the configuration of the program divider 272 and the retiming unit 300 for transmitting the output frequency divided by the main divider to the retiming unit will be described below. The structure of this invention is demonstrated.
  • FIG. 3 is a block diagram illustrating a program divider and a retiming unit according to the present invention.
  • the main divider 270 receives and outputs the output frequency F VCO of the voltage controlled oscillator and divides the prescaler by the division ratio P / P + 1 which is dynamically changed.
  • sigma-delta modulator 273 for providing data.
  • the program divider 272 includes a first counter (A-Counter) 410 and a second counter (B-) to which an output frequency F VCO of the voltage controlled oscillator (VCO) 250 transmitted through the prescaler is applied.
  • a counter 420, and a flip-flop (DFF) 400, and a controller 430 that receives the outputs of the first counter and the second counter and outputs them through the flip-flop to vary the division ratio of the prescaler. It is configured to include.
  • the prescaler 271 is for dispensing a high output frequency F VCO , which is difficult to directly dispense with a program divider, and divides the output frequency F VCO before dividing at 1 / N from the program divider 272.
  • a predetermined dispense ratio is dispensed.
  • the prescaler 271 is preferably composed of a dual modulus prescaler having a division ratio of 1 / P and 1 / (P + 1), and the output frequency F VCO divided by the division ratio is the first counter 410. ) And the second counter 420.
  • the output of the prescaler 271 may include a flip-flop (DFF) 400 provided in the program divider and a first flip-flop (DFF1) 310 forming a retiming unit. It is input to the clock input terminal.
  • DFF flip-flop
  • DFF1 first flip-flop
  • the first counter (A-Counter) 410 is a program counter to input the output frequency (F VCO ) divided by a specific division ratio, for example, 1 / P or 1 / (P + 1) division ratio in the prescaler. And divides by the division ratio 1 / N of the program divider 272 and outputs the output (existing Nout).
  • the second counter (B-Counter) 420 is a swirl counter used for the prescaler's dividing ratio control, and after dividing a predetermined pulse, the second counter (B-Counter) 420 is divided into 1 / P and 1 / (P + 1). It is configured to change between.
  • the controller 430 generates a control signal for changing the division ratio of the prescaler between 1 / P and 1 / (P + 1) by using the output of the first counter and the output of the second counter.
  • the control signal may be output through a flip-flop (DFF) 400 provided in the prescaler and applied to the prescaler.
  • DFF flip-flop
  • the retiming unit 300 includes a first flip-flop (DFF1) 310 to which an output of the first counter 410 is input, and an output frequency F VCO of the voltage controlled oscillator 150.
  • DFF1 first flip-flop
  • F VCO voltage controlled oscillator 150.
  • a delay cell 320 for delaying the < RTI ID 0.0 >),< / RTI > and a second flip flop 330 to which the output of the first flip flop is input and the output of the delay cell is applied as a clock signal.
  • the first flip-flop (DFF1) 310 receives the output of the prescaler 271 as a clock signal and inputs the output of the program divider 272 divided by the first counter (A-Counter). And receive and output a signal, thereby retiming the output of the program divider using the output of the prescaler.
  • the output signal of the first flip-flop (DFF1) 310 output as described above is input to the second flip-flop (DFF2) 330.
  • the delay cell 320 is required to secure the setup or hold time of the first flip-flop, and the output frequency F VCO received by the voltage controlled oscillator VCO . After receiving the delay and delivers to the second flip-flop (DFF2) (330).
  • the second flip-flop (DFF2) 330 receives the output of the first flip-flop 310 and inputs an output frequency F VCO of the voltage controlled oscillator delayed by the delay cell 320 as a clock signal. And is connected to one end of the phase detector 220 to transmit the output signal Retiming Nout of the retimed program divider 272 to the phase detector.
  • the output frequency applied to the phase detector can be totally retimed. Therefore, the pulse difference between the reference frequency and the output frequency is small when comparing the pulses in the phase detector, so that the characteristics of static phase error and jitter become worse, and inband noise becomes worse. It can be prevented.
  • FIG. 4 illustrates measurement results of conventional inband phase noise without retiming the output of the program divider.
  • FIG. 5 illustrates inband phase noise after retiming the output of the program divider. Phase Noise
  • in-band phase noise was about ⁇ 70 dBc when the program divider output was not retimed (ie, conventional Nout in FIG. 3). Therefore, if the jitter of the divider output is removed by retiming the program divider output (that is, Retiming Nout of FIG. 3), the in-band phase noise is about -80 dBc, which is approximately 10 dBc due to retiming. It can be seen that the performance of the band noise is improved.
  • the phase locked loop 100 detects a phase difference between an input signal and an output signal and controls a voltage controlled oscillator (VCO) to fix the frequency of the output signal constantly.
  • VCO voltage controlled oscillator
  • Inband noise of the voltage controlled oscillator (VCO) is deteriorated due to static phase error and jitter or noise of the sigma-delta modulator (SDM). As a result, it can be applied to various fields.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne une boucle à verrouillage de phase (PLL), plus particulièrement une PLL pourvue d'un élément de réajustement permettant d'éliminer la gigue dans un diviseur de fréquence programmable. L'invention permet d'éliminer les bruits dans la bande causés par la gigue de sortie d'un diviseur de fréquence programmable qui divise la phase d'un signal de sortie d'un oscillateur commandé en tension, par réajustement d'une sortie du diviseur et transmission à un détecteur de phase pour comparaison.
PCT/KR2009/001015 2008-03-03 2009-03-03 Boucle à verrouillage de phase pourvue d'un élément de réajustement permettant d'éliminer la gigue dans un diviseur de fréquence variable Ceased WO2009110715A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2008-0019538 2008-03-03
KR1020080019538A KR100980499B1 (ko) 2008-03-03 2008-03-03 프로그램 분주기의 지터 제거용 리타이밍부가 구비된위상고정루프

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WO2009110715A2 true WO2009110715A2 (fr) 2009-09-11
WO2009110715A3 WO2009110715A3 (fr) 2009-12-30

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PCT/KR2009/001015 Ceased WO2009110715A2 (fr) 2008-03-03 2009-03-03 Boucle à verrouillage de phase pourvue d'un élément de réajustement permettant d'éliminer la gigue dans un diviseur de fréquence variable

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WO (1) WO2009110715A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240305304A1 (en) * 2023-03-06 2024-09-12 Ess Technology, Inc. Method and Apparatus For Reducing Jitter In A Phase-Locked Loop

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101488177B1 (ko) * 2013-05-20 2015-02-04 부산대학교 산학협력단 분수 분주형 위상 고정 루프, 이를 포함하는 시스템 온 칩 및 전자 장치
KR101601023B1 (ko) * 2014-05-13 2016-03-09 고려대학교 산학협력단 디지털 보상기를 갖는 스프레드 스펙트럼 클록 생성기 및 이를 이용한 클록생성 방법
KR102788469B1 (ko) * 2022-11-16 2025-03-31 주식회사 로젠시스 위상 고정 루프를 이용한 초고속 데이터 송수신용 트랜스미터

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KR100194624B1 (ko) * 1996-12-02 1999-06-15 이계철 데이타 리타이밍 회로
KR100261294B1 (ko) * 1997-10-14 2000-07-01 이계철 고속 비복귀 기록 데이터 복구장치
JP3921411B2 (ja) 2002-04-19 2007-05-30 Ｎｅｃエンジニアリング株式会社 リタイミング回路
KR100682279B1 (ko) 2005-07-14 2007-02-15 (주)에프씨아이 주파수 합성기의 적응 주파수 조정장치

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240305304A1 (en) * 2023-03-06 2024-09-12 Ess Technology, Inc. Method and Apparatus For Reducing Jitter In A Phase-Locked Loop
US12224757B2 (en) * 2023-03-06 2025-02-11 Ess Technology, Inc. Method and apparatus for reducing jitter in a phase-locked loop

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Publication number Publication date
KR100980499B1 (ko) 2010-09-07
KR20090094540A (ko) 2009-09-08
WO2009110715A3 (fr) 2009-12-30

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