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WO2008156100A1 - 回路基板及び半導体装置 - Google Patents

回路基板及び半導体装置 Download PDF

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Publication number
WO2008156100A1
WO2008156100A1 PCT/JP2008/061099 JP2008061099W WO2008156100A1 WO 2008156100 A1 WO2008156100 A1 WO 2008156100A1 JP 2008061099 W JP2008061099 W JP 2008061099W WO 2008156100 A1 WO2008156100 A1 WO 2008156100A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode pad
circuit board
semiconductor device
resist layer
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/061099
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English (en)
French (fr)
Inventor
Tadahiro Morifuji
Shigeyuki Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of WO2008156100A1 publication Critical patent/WO2008156100A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

　半導体チップがフリップチップ実装される回路基板１は、基板本体２の表面に形成される電極パッド３と、基板本体２の表面を覆い、電極パッド３を露出させる開口部４ａを有するソルダレジスト層４と、を備える。ソルダレジスト層４は、電極パッド３と接しないように形成され、且つ、前記電極パッドの最大幅をＬ、前記ソルダレジスト層の厚みをＨとした場合に、Ｈ／Ｌが１．０≦Ｈ／Ｌ≦１．５を満たすように形成される。
PCT/JP2008/061099 2007-06-18 2008-06-18 回路基板及び半導体装置 Ceased WO2008156100A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007159631A JP5243735B2 (ja) 2007-06-18 2007-06-18 回路基板及び半導体装置
JP2007-159631 2007-06-18

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WO2008156100A1 true WO2008156100A1 (ja) 2008-12-24

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TW (1) TW200919679A (ja)
WO (1) WO2008156100A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225778A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 撮像装置
CN111276471A (zh) * 2020-02-27 2020-06-12 京东方科技集团股份有限公司 一种背光模组及其制作方法、显示装置
CN111668125A (zh) * 2020-06-19 2020-09-15 绍兴同芯成集成电路有限公司 一种晶圆锡球印刷工艺
WO2024066221A1 (zh) * 2022-09-30 2024-04-04 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI464847B (zh) * 2009-12-07 2014-12-11 精材科技股份有限公司 電子元件封裝體及其製造方法
JP2012156257A (ja) 2011-01-25 2012-08-16 Fujitsu Ltd 回路基板及び電子装置
WO2014024338A1 (ja) * 2012-08-10 2014-02-13 パナソニック株式会社 部品実装基板の製造方法及び製造システム
US9263378B1 (en) 2014-08-04 2016-02-16 International Business Machines Corporation Ball grid array and land grid array assemblies fabricated using temporary resist
CN114365584A (zh) * 2020-06-29 2022-04-15 庆鼎精密电子（淮安）有限公司 线路板及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06267964A (ja) * 1993-03-17 1994-09-22 Rohm Co Ltd バンプの形成法
JPH11191670A (ja) * 1997-12-25 1999-07-13 Victor Co Of Japan Ltd プリント配線基板及びその製造方法
JP2004111840A (ja) * 2002-09-20 2004-04-08 Fujitsu Ltd バンプ電極付き電子部品の製造方法
JP2006202881A (ja) * 2005-01-19 2006-08-03 Ibiden Co Ltd プリント配線板及びその製法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000277898A (ja) * 1999-03-24 2000-10-06 Nippon Avionics Co Ltd ボールグリッドアレイパッケージ実装用基板
JP3836449B2 (ja) * 2003-07-16 2006-10-25 シャープ株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06267964A (ja) * 1993-03-17 1994-09-22 Rohm Co Ltd バンプの形成法
JPH11191670A (ja) * 1997-12-25 1999-07-13 Victor Co Of Japan Ltd プリント配線基板及びその製造方法
JP2004111840A (ja) * 2002-09-20 2004-04-08 Fujitsu Ltd バンプ電極付き電子部品の製造方法
JP2006202881A (ja) * 2005-01-19 2006-08-03 Ibiden Co Ltd プリント配線板及びその製法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010225778A (ja) * 2009-03-23 2010-10-07 Toshiba Corp 撮像装置
CN111276471A (zh) * 2020-02-27 2020-06-12 京东方科技集团股份有限公司 一种背光模组及其制作方法、显示装置
CN111668125A (zh) * 2020-06-19 2020-09-15 绍兴同芯成集成电路有限公司 一种晶圆锡球印刷工艺
WO2024066221A1 (zh) * 2022-09-30 2024-04-04 长鑫存储技术有限公司 半导体结构和半导体结构的制造方法

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