WO2008153128A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2008153128A1 WO2008153128A1 PCT/JP2008/060844 JP2008060844W WO2008153128A1 WO 2008153128 A1 WO2008153128 A1 WO 2008153128A1 JP 2008060844 W JP2008060844 W JP 2008060844W WO 2008153128 A1 WO2008153128 A1 WO 2008153128A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode pad
- semiconductor device
- pad portion
- barrier metal
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/01—Chemical elements
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- H01L2924/0504—14th Group
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- H01L2924/11—Device type
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
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- H01L2924/351—Thermal stress
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008800202805A CN101681859B (zh) | 2007-06-15 | 2008-06-13 | 半导体器件 |
| US12/663,563 US8436467B2 (en) | 2007-06-15 | 2008-06-13 | Semiconductor device |
| US13/856,905 US8922010B2 (en) | 2007-06-15 | 2013-04-04 | Semiconductor device |
| US14/337,959 US9053991B2 (en) | 2007-06-15 | 2014-07-22 | Semiconductor device |
| US14/491,556 US9123628B2 (en) | 2007-06-15 | 2014-09-19 | Semiconductor device |
| US14/803,207 US9466583B2 (en) | 2007-06-15 | 2015-07-20 | Semiconductor device |
| US15/219,912 US9685419B2 (en) | 2007-06-15 | 2016-07-26 | Semiconductor device |
| US15/591,456 US10032739B2 (en) | 2007-06-15 | 2017-05-10 | Semiconductor device |
| US16/018,128 US10510700B2 (en) | 2007-06-15 | 2018-06-26 | Semiconductor device |
| US16/683,647 US11037897B2 (en) | 2007-06-15 | 2019-11-14 | Semiconductor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007159354A JP5243734B2 (ja) | 2007-06-15 | 2007-06-15 | 半導体装置 |
| JP2007159351A JP5280650B2 (ja) | 2007-06-15 | 2007-06-15 | 半導体装置 |
| JP2007-159354 | 2007-06-15 | ||
| JP2007-159351 | 2007-06-15 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US12/663,563 A-371-Of-International US8436467B2 (en) | 2007-06-15 | 2008-06-13 | Semiconductor device |
| US13/856,905 Division US8922010B2 (en) | 2007-06-15 | 2013-04-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2008153128A1 true WO2008153128A1 (ja) | 2008-12-18 |
Family
ID=40129731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2008/060844 Ceased WO2008153128A1 (ja) | 2007-06-15 | 2008-06-13 | 半導体装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (9) | US8436467B2 (ja) |
| CN (1) | CN101681859B (ja) |
| TW (1) | TW200915511A (ja) |
| WO (1) | WO2008153128A1 (ja) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008153128A1 (ja) | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | 半導体装置 |
| US8841766B2 (en) | 2009-07-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
| TWI452354B (zh) * | 2009-08-19 | 2014-09-11 | United Microelectronics Corp | 光學元件的製造方法 |
| EP2629323A1 (en) * | 2010-10-12 | 2013-08-21 | Kabushiki Kaisha Yaskawa Denki | Electronic device and electronic component |
| TWI474451B (zh) * | 2011-09-15 | 2015-02-21 | Chipmos Technologies Inc | 覆晶封裝結構及其形成方法 |
| US9224674B2 (en) * | 2011-12-15 | 2015-12-29 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages |
| US9583425B2 (en) * | 2012-02-15 | 2017-02-28 | Maxim Integrated Products, Inc. | Solder fatigue arrest for wafer level package |
| US20130341780A1 (en) * | 2012-06-20 | 2013-12-26 | Infineon Technologies Ag | Chip arrangements and a method for forming a chip arrangement |
| US9673093B2 (en) * | 2013-08-06 | 2017-06-06 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of making wafer level chip scale package |
| US10163828B2 (en) * | 2013-11-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
| US9504152B2 (en) | 2014-07-02 | 2016-11-22 | Samsung Electronics Co., Ltd. | Printed circuit board for semiconductor package |
| CN104066270A (zh) * | 2014-07-02 | 2014-09-24 | 三星半导体(中国)研究开发有限公司 | 用于电路板的表面镀层、焊盘和电路板 |
| JP6436531B2 (ja) * | 2015-01-30 | 2018-12-12 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
| US9786634B2 (en) * | 2015-07-17 | 2017-10-10 | National Taiwan University | Interconnection structures and methods for making the same |
| US9646943B1 (en) | 2015-12-31 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connector structure and method of forming same |
| JP6562467B2 (ja) * | 2016-06-21 | 2019-08-21 | サムスン エレクトロニクス カンパニー リミテッド | ファン−アウト半導体パッケージ |
| US9859241B1 (en) * | 2016-09-01 | 2018-01-02 | International Business Machines Corporation | Method of forming a solder bump structure |
| US10710461B2 (en) * | 2016-11-11 | 2020-07-14 | Ford Global Technologies, Llc | Absorbing power down energy of an external motor device in a power generation vehicle |
| JP6680705B2 (ja) * | 2017-02-10 | 2020-04-15 | キオクシア株式会社 | 半導体装置及びその製造方法 |
| US10420211B2 (en) * | 2017-08-09 | 2019-09-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor package device |
| JP7214966B2 (ja) * | 2018-03-16 | 2023-01-31 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
| US10796987B2 (en) * | 2018-11-06 | 2020-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US10847408B2 (en) | 2019-01-31 | 2020-11-24 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
| US11114406B2 (en) * | 2019-01-31 | 2021-09-07 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
| KR20230144697A (ko) * | 2022-04-07 | 2023-10-17 | 삼성전자주식회사 | 반도체 장치 및 그의 제조 방법 |
Citations (3)
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| JPS5773936U (ja) * | 1980-10-24 | 1982-05-07 | ||
| JPH01187949A (ja) * | 1988-01-22 | 1989-07-27 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2001035876A (ja) * | 1999-07-23 | 2001-02-09 | Nec Corp | フリップチップ接続構造、半導体装置および半導体装置製造方法 |
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| JPS523425A (en) | 1975-06-25 | 1977-01-11 | Tokyo Kouon:Kk | Film jointing device of small size camera |
| JPS5773936A (en) | 1980-10-27 | 1982-05-08 | Toshiba Corp | Cassette holder for electron beam exposure |
| JPH09129647A (ja) | 1995-10-27 | 1997-05-16 | Toshiba Corp | 半導体素子 |
| JPH11340265A (ja) * | 1998-05-22 | 1999-12-10 | Sony Corp | 半導体装置及びその製造方法 |
| JP4058198B2 (ja) | 1999-07-02 | 2008-03-05 | 富士通株式会社 | 半導体装置の製造方法 |
| JP2001085560A (ja) * | 1999-09-13 | 2001-03-30 | Sharp Corp | 半導体装置およびその製造方法 |
| TW449813B (en) * | 2000-10-13 | 2001-08-11 | Advanced Semiconductor Eng | Semiconductor device with bump electrode |
| TW517334B (en) * | 2000-12-08 | 2003-01-11 | Nec Corp | Method of forming barrier layers for solder bumps |
| US6815324B2 (en) * | 2001-02-15 | 2004-11-09 | Megic Corporation | Reliable metal bumps on top of I/O pads after removal of test probe marks |
| US6737353B2 (en) * | 2001-06-19 | 2004-05-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having bump electrodes |
| US6489229B1 (en) * | 2001-09-07 | 2002-12-03 | Motorola, Inc. | Method of forming a semiconductor device having conductive bumps without using gold |
| TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
| KR100659527B1 (ko) * | 2003-10-22 | 2006-12-20 | 삼성전자주식회사 | 3차원 범프 하부 금속층을 갖는 플립 칩 본딩용 반도체칩과 그 실장 구조 |
| JP2005259848A (ja) | 2004-03-10 | 2005-09-22 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP4327656B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
| JP4360293B2 (ja) | 2004-07-02 | 2009-11-11 | 株式会社村田製作所 | 半田バンプ電極構造 |
| KR100630698B1 (ko) * | 2004-08-17 | 2006-10-02 | 삼성전자주식회사 | 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법 |
| JP4452217B2 (ja) | 2005-07-04 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
| JP5118300B2 (ja) * | 2005-12-20 | 2013-01-16 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
| JP2007273624A (ja) * | 2006-03-30 | 2007-10-18 | Fujitsu Ltd | 半導体装置及びその製造方法 |
| JP2007317979A (ja) * | 2006-05-29 | 2007-12-06 | Toshiba Corp | 半導体装置の製造方法 |
| WO2008153128A1 (ja) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | 半導体装置 |
-
2008
- 2008-06-13 WO PCT/JP2008/060844 patent/WO2008153128A1/ja not_active Ceased
- 2008-06-13 CN CN2008800202805A patent/CN101681859B/zh active Active
- 2008-06-13 TW TW097122280A patent/TW200915511A/zh unknown
- 2008-06-13 US US12/663,563 patent/US8436467B2/en active Active
-
2013
- 2013-04-04 US US13/856,905 patent/US8922010B2/en active Active
-
2014
- 2014-07-22 US US14/337,959 patent/US9053991B2/en active Active
- 2014-09-19 US US14/491,556 patent/US9123628B2/en active Active
-
2015
- 2015-07-20 US US14/803,207 patent/US9466583B2/en active Active
-
2016
- 2016-07-26 US US15/219,912 patent/US9685419B2/en active Active
-
2017
- 2017-05-10 US US15/591,456 patent/US10032739B2/en active Active
-
2018
- 2018-06-26 US US16/018,128 patent/US10510700B2/en active Active
-
2019
- 2019-11-14 US US16/683,647 patent/US11037897B2/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5773936U (ja) * | 1980-10-24 | 1982-05-07 | ||
| JPH01187949A (ja) * | 1988-01-22 | 1989-07-27 | Fujitsu Ltd | 半導体装置の製造方法 |
| JP2001035876A (ja) * | 1999-07-23 | 2001-02-09 | Nec Corp | フリップチップ接続構造、半導体装置および半導体装置製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US9685419B2 (en) | 2017-06-20 |
| US10032739B2 (en) | 2018-07-24 |
| US8436467B2 (en) | 2013-05-07 |
| US20180301429A1 (en) | 2018-10-18 |
| US20140332954A1 (en) | 2014-11-13 |
| US20100187685A1 (en) | 2010-07-29 |
| TW200915511A (en) | 2009-04-01 |
| US20170243844A1 (en) | 2017-08-24 |
| US20200098713A1 (en) | 2020-03-26 |
| US9123628B2 (en) | 2015-09-01 |
| US20150325541A1 (en) | 2015-11-12 |
| CN101681859A (zh) | 2010-03-24 |
| US20130256881A1 (en) | 2013-10-03 |
| CN101681859B (zh) | 2011-10-19 |
| US8922010B2 (en) | 2014-12-30 |
| US20150021765A1 (en) | 2015-01-22 |
| US9053991B2 (en) | 2015-06-09 |
| US10510700B2 (en) | 2019-12-17 |
| US9466583B2 (en) | 2016-10-11 |
| US11037897B2 (en) | 2021-06-15 |
| US20160336288A1 (en) | 2016-11-17 |
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