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WO2004049073A3 - Procede de sechage pour pellicules dielectriques a faible constante k - Google Patents

Procede de sechage pour pellicules dielectriques a faible constante k Download PDF

Info

Publication number
WO2004049073A3
WO2004049073A3 PCT/US2003/038019 US0338019W WO2004049073A3 WO 2004049073 A3 WO2004049073 A3 WO 2004049073A3 US 0338019 W US0338019 W US 0338019W WO 2004049073 A3 WO2004049073 A3 WO 2004049073A3
Authority
WO
WIPO (PCT)
Prior art keywords
low
drying process
dielectric films
exposing
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/038019
Other languages
English (en)
Other versions
WO2004049073A2 (fr
Inventor
Carlo Waldfried
Qingyuan Han
John Hallock
Ivan Berry
Ari Margolis
Orlando Escorcia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axcelis Technologies Inc
Original Assignee
Axcelis Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axcelis Technologies Inc filed Critical Axcelis Technologies Inc
Priority to JP2004555813A priority Critical patent/JP4359847B2/ja
Publication of WO2004049073A2 publication Critical patent/WO2004049073A2/fr
Publication of WO2004049073A3 publication Critical patent/WO2004049073A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Solid Materials (AREA)

Abstract

L'invention concerne un procédé pour sécher et enlever des contaminants contenus dans une pellicule diélectrique à faible constante k d'une plaquette de circuits imprimés. Ce procédé consiste, entre autres : à exposer la couche diélectrique à faible constante k à des photons ; et pendant, avant ou après cette exposition photonique, à exposer le substrat à un traitement permettant d'enlever efficacement lesdits contaminants sans entraîner une quelconque dégradation de la couche à faible constante k. Selon l'invention, ledit traitement peut se présenter sous la forme d'un traitement thermique, d'un traitement par le vide, d'un traitement au plasma exempt d'oxygène, ou de combinaisons de ces traitements.
PCT/US2003/038019 2002-11-26 2003-11-26 Procede de sechage pour pellicules dielectriques a faible constante k Ceased WO2004049073A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004555813A JP4359847B2 (ja) 2002-11-26 2003-11-26 低ｋ誘電体フィルムのための乾燥処理

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/065,861 US20040099283A1 (en) 2002-11-26 2002-11-26 Drying process for low-k dielectric films
US10/065,861 2002-11-26

Publications (2)

Publication Number Publication Date
WO2004049073A2 WO2004049073A2 (fr) 2004-06-10
WO2004049073A3 true WO2004049073A3 (fr) 2004-11-18

Family

ID=32323603

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/038019 Ceased WO2004049073A2 (fr) 2002-11-26 2003-11-26 Procede de sechage pour pellicules dielectriques a faible constante k

Country Status (3)

Country Link
US (1) US20040099283A1 (fr)
JP (1) JP4359847B2 (fr)
WO (1) WO2004049073A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6936551B2 (en) * 2002-05-08 2005-08-30 Applied Materials Inc. Methods and apparatus for E-beam treatment used to fabricate integrated circuit devices
US7060330B2 (en) * 2002-05-08 2006-06-13 Applied Materials, Inc. Method for forming ultra low k films using electron beam
US6913992B2 (en) * 2003-03-07 2005-07-05 Applied Materials, Inc. Method of modifying interlayer adhesion
US20050250346A1 (en) 2004-05-06 2005-11-10 Applied Materials, Inc. Process and apparatus for post deposition treatment of low k dielectric materials
US20060251827A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. Tandem uv chamber for curing dielectric materials
US20060249175A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. High efficiency UV curing system
US8039049B2 (en) * 2005-09-30 2011-10-18 Tokyo Electron Limited Treatment of low dielectric constant films using a batch processing system
US7501355B2 (en) * 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
US7598183B2 (en) * 2006-09-20 2009-10-06 Applied Materials, Inc. Bi-layer capping of low-K dielectric films
US7964039B2 (en) * 2007-09-07 2011-06-21 Imec Cleaning of plasma chamber walls using noble gas cleaning step
US10811370B2 (en) 2018-04-24 2020-10-20 Cree, Inc. Packaged electronic circuits having moisture protection encapsulation and methods of forming same

Citations (7)

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US5447613A (en) * 1990-12-20 1995-09-05 Mitel Corporation Preventing of via poisoning by glow discharge induced desorption
US5866945A (en) * 1997-10-16 1999-02-02 Advanced Micro Devices Borderless vias with HSQ gap filled patterned metal layers
US6043165A (en) * 1996-10-28 2000-03-28 Samsung Electronics Co., Ltd. Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent
US6235453B1 (en) * 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US20020111017A1 (en) * 2000-12-14 2002-08-15 Kirkpatrick Brian K. Pre-pattern surface modification for low-k dielectrics using A H2 plasma
US20020164877A1 (en) * 2001-05-02 2002-11-07 Catabay Wilbur G. Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

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US4341592A (en) * 1975-08-04 1982-07-27 Texas Instruments Incorporated Method for removing photoresist layer from substrate by ozone treatment
US4885047A (en) * 1986-08-11 1989-12-05 Fusion Systems Corporation Apparatus for photoresist stripping
WO1990012126A1 (fr) * 1989-03-31 1990-10-18 Canon Kabushiki Kaisha Procede pour former un film polycristallin par depot en phase gazeuse par voie chimique
US5290383A (en) * 1991-03-24 1994-03-01 Tokyo Electron Limited Plasma-process system with improved end-point detecting scheme
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US5705232A (en) * 1994-09-20 1998-01-06 Texas Instruments Incorporated In-situ coat, bake and cure of dielectric material processing system for semiconductor manufacturing
US6203582B1 (en) * 1996-07-15 2001-03-20 Semitool, Inc. Modular semiconductor workpiece processing tool
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JP4043705B2 (ja) * 2000-09-27 2008-02-06 株式会社東芝 半導体装置の製造方法、ウェハ処理装置、及びウェハ保管箱
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JP3739325B2 (ja) * 2001-09-20 2006-01-25 株式会社日立製作所 有機絶縁膜のエッチング方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5447613A (en) * 1990-12-20 1995-09-05 Mitel Corporation Preventing of via poisoning by glow discharge induced desorption
US6043165A (en) * 1996-10-28 2000-03-28 Samsung Electronics Co., Ltd. Methods of forming electrically interconnected lines using ultraviolet radiation as an organic compound cleaning agent
US5866945A (en) * 1997-10-16 1999-02-02 Advanced Micro Devices Borderless vias with HSQ gap filled patterned metal layers
US6235453B1 (en) * 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US20020111017A1 (en) * 2000-12-14 2002-08-15 Kirkpatrick Brian K. Pre-pattern surface modification for low-k dielectrics using A H2 plasma
US20020164877A1 (en) * 2001-05-02 2002-11-07 Catabay Wilbur G. Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

Also Published As

Publication number Publication date
JP4359847B2 (ja) 2009-11-11
US20040099283A1 (en) 2004-05-27
WO2004049073A2 (fr) 2004-06-10
JP2006508535A (ja) 2006-03-09

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