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US20040099283A1 - Drying process for low-k dielectric films - Google Patents

Drying process for low-k dielectric films Download PDF

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Publication number
US20040099283A1
US20040099283A1 US10/065,861 US6586102A US2004099283A1 US 20040099283 A1 US20040099283 A1 US 20040099283A1 US 6586102 A US6586102 A US 6586102A US 2004099283 A1 US2004099283 A1 US 2004099283A1
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US
United States
Prior art keywords
low
dielectric layer
substrate
exposing
contaminants
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Abandoned
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US10/065,861
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English (en)
Inventor
Carlo Waldfried
Qingyaun Han
John Hallock
Ivan Berry
Ari Margolis
Orlando Escorcia
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Axcelis Technologies Inc
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Axcelis Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Axcelis Technologies Inc filed Critical Axcelis Technologies Inc
Priority to US10/065,861 priority Critical patent/US20040099283A1/en
Assigned to AXCELIS TECHNOLOGIES, INC. reassignment AXCELIS TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BERRY, IVAN, ESCORCIA, ORLANDO, HALLOCK, JOHN, HAN, QINGYAUN, WALDFRIED, CARLO, MARGOLIS, ARI
Priority to PCT/US2003/038019 priority patent/WO2004049073A2/fr
Priority to JP2004555813A priority patent/JP4359847B2/ja
Publication of US20040099283A1 publication Critical patent/US20040099283A1/en
Assigned to SILICON VALLEY BANK reassignment SILICON VALLEY BANK SECURITY AGREEMENT Assignors: AXCELIS TECHNOLOGIES, INC.
Abandoned legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31058After-treatment of organic layers
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Definitions

  • This disclosure relates generally to a method for drying and removing contaminants from low-k dielectric films.
  • the low k dielectric materials used in advanced integrated circuits typically comprise organic polymers or oxides and have dielectric constants less than about 3.5.
  • the low k dielectric materials can be spun onto the substrate as a solution or deposited by a chemical vapor deposition process.
  • Important low k film properties include thickness and uniformity, dielectric constant, refractive index, adhesion, chemical resistance, thermal stability, pore size and distribution, coefficient of thermal expansion, glass transition temperature, film stress, and copper diffusion coefficient.
  • the wafers are generally subjected to many process steps before finished integrated circuits can be produced.
  • Low-k dielectric materials can be sensitive to some of these process steps.
  • plasma used during an “ashing” step can strip both photoresist material as well as remove a portion of the low-k dielectric film.
  • Ashing refers to a plasma stripping process by which residual photoresist and post etch residues are stripped or removed from a substrate upon exposure to the plasma.
  • the ashing process generally occurs after an etching or implant process has been performed in which a photoresist material is used as a mask for etching a pattern into the underlying substrate or for selectively implanting ions into the exposed areas of the substrate.
  • the remaining photoresist and any post etch or post implant residues on the wafer after the etch process or implant process is complete must be removed prior to further processing for numerous reasons generally known to those skilled in the art.
  • the ashing step is typically followed by a wet chemical treatment to remove traces of the residue, which can cause further degradation of the low k dielectric and may cause increase in the dielectric constant.
  • the photoresist can be removed by the use of wet strippers.
  • Wet strippers include acids, bases, and solvents as are known to those skilled in the art. The particular wet strippers used are well within the skill of those in the art. For example, nitric acid, sulfuric acid, ammonia are commonly employed as wet strippers.
  • the substrate is immersed, puddled, streamed, sprayed or the like by the wet stripper and subsequently rinsed with deionized water.
  • a rinsing step is typically employed to remove the stripper, contaminants and/or photoresist residuals.
  • the rinsing step employs deionized water.
  • ashing processes significantly differ from etching processes. Although both processes may be plasma mediated, an etching process is markedly different in that the plasma chemistry is chosen to permanently transfer an image into the substrate by removing portions of the substrate surface through openings in a photoresist mask.
  • the plasma generally includes high energy ion bombardment at low temperatures to remove portions of the substrate.
  • the portions of the substrate exposed to the ions are generally removed at a rate equal to or greater than the removal rate of the photoresist mask.
  • ashing processes generally refer to selectively removing the photoresist mask and any polymers or residues formed during etching.
  • the ashing plasma chemistry is much less aggressive than etching chemistries and is generally chosen to remove the photoresist mask layer at a rate much greater than the removal rate of the underlying substrate. Moreover, most ashing processes heat the substrate to temperatures greater than 200° C. to increase the plasma reactivity. Thus, etching and ashing processes are directed to removal of significantly different materials and as such, require completely different plasma chemistries and processes. Successful ashing processes are not used to permanently transfer an image into the substrate. Rather, successful ashing processes are defined by the photoresist, polymer and residue removal rates without affecting or removing underlying layers, e.g., low k dielectric layers.
  • Solvents such as those comprising the wet chemical treatment or wet strippers, can adhere, become adsorbed and/or trapped in pores of the low k dielectric film. This entrainment can cause an increase in the dielectric constant of the film, thus defeating the purpose of using the low-k dielectric. An increase in dielectric constant undesirably affects interconnect capacitance and cross talk. Moreover, trapped cleaning chemicals can also lead to metal corrosion and reduced device reliability since a surface of the dielectric layer typically abuts a conductive metal layer. These problems are exacerbated for those low k dielectrics that contain pores.
  • You et al. also describe a method for removing or reducing trapped solvents by employing heat and/or a vacuum.
  • the described drying process is relatively slow and relies on the volatility of the contaminants being sufficiently volatile to be outgassed from the low k dielectric film layer.
  • some of the contaminants are residual photoresist materials, which are based on polymers and typically are not sufficiently volatile to be removed by the heat and/or vacuum processing by itself.
  • a drying process for removing moisture and contaminants from a substrate having a low k dielectric layer thereon in a process chamber.
  • the process comprises exposing the low k dielectric layer to photons; and simultaneously with, prior to, or subsequent to the photon exposure, exposing the substrate to a process effective to remove the contaminants without causing degradation of the low k dielectric layer, wherein the process is selected from the group consisting of a heat process, a vacuum process, an oxygen free plasma process, and combinations thereof.
  • a process for removing contaminants adsorbed, adhered, or trapped within a low k dielectric layer, wherein the contaminants comprise residual water, moisture, silanols, residual plasma or wet etch chemistries residuals of wet clean chemistries, acids, bases, and solvents comprises exposing the low k dielectric layer in a process chamber to radiation comprising a wavelength of about 150 nanometers to about 500 nanometers; and exposing the substrate to oxygen free plasma, or heat, or a vacuum, or a combination thereof to remove the contaminants without causing degradation of the low k dielectric layer.
  • FIG. 1 illustrates a cross section of an exemplary exposure tool for drying a low k dielectric layer
  • FIG. 2 is a FTIR spectra of before and after drying results for a porous doped oxide low-k dielectric film.
  • a process for drying and removing contaminants from low-k dielectric films is described herein.
  • the drying process generally comprises exposing a surface of the low k dielectric film to photons, and simultaneously, prior to, or subsequently applying plasma, or heat or a vacuum, or a combination of two or more of the foregoing processes to remove the contaminants adhered to, adsorbed, and/or trapped by the low k dielectric layer.
  • the photons could be included in ultraviolet (UV), x-ray, and/or other forms of electromagnetic radiation.
  • the source of photons is from a UV light exposure.
  • the drying process follows an ashing and/or wet stripping process to remove residues and solvents adhered to, adsorbed, or trapped by the low k dielectric layer.
  • ashing and/or wet stripping process to remove residues and solvents adhered to, adsorbed, or trapped by the low k dielectric layer.
  • excitation, scission and/or fragmentation of molecular bonds of the contaminants contained therein or thereon occurs, which facilities the removal of these contaminants.
  • the species generated by excitation, scission and/or fragmentation exhibit greater volatility and can be removed with the plasma or heat or vacuum treatment or the combination of two or more of the foregoing processes applied to the substrate simultaneous with or subsequent to the photon exposure.
  • Low k dielectrics are hereinafter defined as those insulating materials suitable for use in the manufacture of integrated circuits or the like having a dielectric constant less than about 3.5.
  • Low k dielectrics can generally be categorized as one of two types: organic, and doped oxides.
  • organic low k dielectric materials include polyimides, benzocyclobutene, parylenes, diamond-like carbon, poly(arylene ethers), cyclotenes, fluorocarbons and the like, such as those dielectrics commercially available under the trademarks SiLK, or BCB.
  • doped oxide low k dielectric materials include methyl silsesquioxane, hydrogen silsesquioxanes, nanoporous oxides, carbon doped silicon dioxides, and the like, such as, for example, those dielectrics commercially available under the trademarks CORAL, BLACK DIAMOND and AURORA. Both types of low-k materials exist in dense and porous versions. Porous versions thereof are commercially known under trademarks such as LKD, ORION, BOSS, or porous SiLK. Other low k dielectric materials will be apparent to one of ordinary skill in the art in view of this disclosure.
  • the photons could be included in ultraviolet (UV), x-ray, and/or other forms of electromagnetic radiation.
  • UV ultraviolet
  • x-ray x-ray
  • other forms of electromagnetic radiation For exemplary purposes, reference will now be made in detail to the preferred embodiments, wherein the photon source is a UV light source. The use of other proton sources will be well within the skill of those in the art in view of this disclosure.
  • the wavelength of the UV light exposure can be emitted as a narrow wavelength or as a broadband spectrum.
  • the UV light exposure is emitted as a broadband spectrum.
  • the term “broadband spectrum” refers to a radiation source having at least one wavelength band having a full-width half-maximum greater than about 10 nanometers (nm), with preferably greater than about 100 nm more preferred, and with greater than 200 nm even more preferred.
  • FWHM full-width half-maximum
  • the UV radiation comprises wavelengths of about 150 nanometers (nm) to about 500 nm, with about 200 nm to about 400 nm more preferred.
  • the energy incident to the low k dielectric surface is preferably, on average, about 10 milliwatts per square centimeter (mW/cm 2 ) to about 1 watt (W/cm 2 ).
  • the exposure times are directly dependent on the intensity of the light source (as well as other factors). In terms of throughput, the exposure times are preferably less than about 180 seconds, with less than about 60 seconds more preferred, and with less than about 30 seconds even more preferred.
  • the substrate is subjected to plasma, or heat or vacuum or a combination comprising two or more of the foregoing processes.
  • the plasma is preferably an oxygen free plasma such as is described in U.S. Pat. No. 6,281,135 to Han et al., herein incorporated by reference in its entirety.
  • the oxygen free plasma is generated from a gas composition comprising an inert gas and optionally, a hydrogen bearing gas.
  • the hydrogen bearing compounds include those compounds that contain hydrogen, such as for example, hydrocarbons, hydrofluorocarbons, hydrogen precursor gas, hydrogen gas, and hydrogen gas mixtures.
  • the hydrogen bearing compound is a non-flammable hydrogen gas mixture containing an inert gas such as nitrogen.
  • Preferred hydrogen precursor gases are those that exist in a gaseous state and release hydrogen to form reactive hydrogen species such as free radical or hydrogen ions under plasma forming conditions.
  • the gas may be a hydrocarbon that is unsubstituted or may be partially substituted with a halogen such as bromine, chlorine or fluorine, or with oxygen, nitrogen, hydroxyl and amine groups.
  • the hydrocarbon has at least one hydrogen and from one to twelve carbon atoms, and more preferably has from three to ten carbon atoms.
  • suitable hydrogen bearing gases include methane, ethane, ammonia, and propane.
  • Preferred hydrogen gas mixtures are those gases that contain hydrogen gas and an inert gas.
  • the inert gas include argon, nitrogen, neon, helium or the like.
  • Especially preferred hydrogen gas mixtures are so-called forming gases that consist essentially of hydrogen gas and nitrogen gas or hydrogen gas and helium, or hydrogen gas and argon.
  • Particularly preferable is a forming gas, wherein the hydrogen gas ranges in an amount from about 3 to about 5 percent by volume of the total forming gas composition due to safety considerations.
  • Plasma asher devices particularly suitable for use in the present disclosure are downstream plasma ashers, such as for example, those microwave plasma ashers available under the trade names GEMINI ES, ES3, or ES31, and commercially available from Axcelis Technologies. Portions of the microwave plasma asher are described in U.S. Pat. Nos. 5,498,308 and 4,341,592, and PCT International Application No. WO/97/37055, herein incorporated by reference in their entireties. The disclosure is not limited to any particular plasma asher in this or in the following embodiments. For instance, an inductively coupled plasma reactor can be used.
  • the amount of heat applied to the substrate will depend on the thermal stability of the particular low k dielectric layer as well as the other layers and components already formed in the substrate.
  • the substrate is preferably exposed to heat of sufficient intensity and duration to cause the contaminants to diffuse out of the low-k dielectric layer and volatize without causing degradation of any other components or layers in the substrate.
  • the wafer is heated from about 20° C. to about 400° C., with about 100° C. to about 300° C. more preferred.
  • the wafer is heated from about 80° C. to a maximum of about 180° C.
  • the maximum temperatures for organic dielectrics are dependent on the intrinsic properties of the organic low k material used and can be determined by thermal analysis techniques known to those skilled in the art. The temperature may be step-wise increased during processing or remain static throughout the drying process.
  • a vacuum if employed, is preferably operated at about 1 mTorr to about 100 mTorr, with about 1 mTorr to about 50 mTorr more preferred, and with about 1 mTorr to about 10 mTorr even more preferred.
  • FIG. 1 illustrates an exemplary exposure tool 10 suitable for practicing the drying process.
  • the exposure tool 10 generally includes a process chamber 12 and a radiation source chamber 14 .
  • the process chamber 12 includes a chuck 16 on which a substrate 18 is disposed.
  • the chuck 16 or process chamber 12 may be adapted to provide a heat source (not shown) for heating the wafer during processing.
  • An example of optional heating is a heated chuck.
  • the exposure tool 10 further includes a radiation source 20 and a plate 22 may be disposed between the radiation source 18 and the chuck 16 .
  • Conduits 24 are disposed in fluid communication with the process chamber 12 for purging the chamber 12 , regulating a pressure within the process chamber 12 , and the like.
  • the exposure tool 10 may further include additional features such as the structural features described in U.S. Pat. No. 4,885,047 to Matthews et al., incorporated herein by reference in its entirety, for providing a uniform exposure of light to the wafer surface.
  • the drying process includes loading the substrate 18 into the process chamber 12 and exposing the substrate 18 to UV radiation emitted by the radiation source 20 .
  • the process chamber 112 is configured for automatic handling such that manual handling of the substrate 18 is eliminated.
  • the process includes purging the process chamber 12 with one or more inert gases to remove the air within the process chamber 12 and then exposing the substrate 18 to UV radiation.
  • Suitable inert gases for purging air from the process chamber 12 include, but are not limited to, nitrogen, argon, helium, forming gas, combinations comprising at least one of the foregoing gases, and the like.
  • the substrate may be subjected to heat and/or a vacuum for removing the volatile components from the low k dielectric layer.
  • a porous doped oxide low k dielectric layer with a thickness of approximately 1 micrometer was spin coated onto a silicon substrate, cured, and exposed to ambient moisture.
  • the peaks associated with moisture and contaminant absorption can be readily observed in an FTIR spectra of the substrate at wavelengths of about 3000 to about 3400 angstroms and at about 1400 angstroms.
  • the substrate was then placed in a UV process chamber having features similar to that shown in FIG. 1 and purged with nitrogen.
  • the substrate was then exposed to a UV radiation having a broadband wavelength spectrum ranging from 220 to 400 nm.
  • the exposure time was 30 seconds and the wafer was heated to 240° C. during the exposure.
  • the process can be used to remove contaminants from a low k dielectric layer, thus avoiding degradation that can occur because of the adhered, adsorbed, and/or trapped contaminants.
  • the photon mediated drying process is believed to more efficiently remove contaminants since large molecules can be fragmented to form volatile compounds upon exposure to the UV radiation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Solid Materials (AREA)
US10/065,861 2002-11-26 2002-11-26 Drying process for low-k dielectric films Abandoned US20040099283A1 (en)

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Application Number Priority Date Filing Date Title
US10/065,861 US20040099283A1 (en) 2002-11-26 2002-11-26 Drying process for low-k dielectric films
PCT/US2003/038019 WO2004049073A2 (fr) 2002-11-26 2003-11-26 Procede de sechage pour pellicules dielectriques a faible constante k
JP2004555813A JP4359847B2 (ja) 2002-11-26 2003-11-26 低k誘電体フィルムのための乾燥処理

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050130404A1 (en) * 2002-05-08 2005-06-16 Applied Materials, Inc. Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices
US20050153073A1 (en) * 2002-05-08 2005-07-14 Applied Materials, Inc. Method for forming ultra low k films using electron beam
US20060249175A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. High efficiency UV curing system
US20060249078A1 (en) * 2005-05-09 2006-11-09 Thomas Nowak High efficiency uv curing system
US20070141855A1 (en) * 2003-03-07 2007-06-21 Applied Materials, Inc. Methods of modifying interlayer adhesion
US20080014761A1 (en) * 2006-06-29 2008-01-17 Ritwik Bhatia Decreasing the etch rate of silicon nitride by carbon addition
US20080070421A1 (en) * 2006-09-20 2008-03-20 Ping Xu Bi-layer capping of low-k dielectric films
US7910897B2 (en) 2004-05-06 2011-03-22 Applied Materials, Inc. Process and apparatus for post deposition treatment of low dielectric materials
WO2019209543A1 (fr) * 2018-04-24 2019-10-31 Cree, Inc. Circuits électroniques conditionnés ayant une encapsulation de protection contre l'humidité et leurs procédés de formation

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8039049B2 (en) * 2005-09-30 2011-10-18 Tokyo Electron Limited Treatment of low dielectric constant films using a batch processing system
US7964039B2 (en) * 2007-09-07 2011-06-21 Imec Cleaning of plasma chamber walls using noble gas cleaning step

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4341592A (en) * 1975-08-04 1982-07-27 Texas Instruments Incorporated Method for removing photoresist layer from substrate by ozone treatment
US4885047A (en) * 1986-08-11 1989-12-05 Fusion Systems Corporation Apparatus for photoresist stripping
US5151296A (en) * 1989-03-31 1992-09-29 Canon Kk Method for forming polycrystalline film by chemical vapor deposition process
US5322590A (en) * 1991-03-24 1994-06-21 Tokyo Electron Limited Plasma-process system with improved end-point detecting scheme
US5498308A (en) * 1994-02-25 1996-03-12 Fusion Systems Corp. Plasma asher with microwave trap
US5705232A (en) * 1994-09-20 1998-01-06 Texas Instruments Incorporated In-situ coat, bake and cure of dielectric material processing system for semiconductor manufacturing
US6021672A (en) * 1998-09-18 2000-02-08 Windbond Electronics Corp. Simultaneous in-situ optical sensing of pressure and etch rate in plasma etch chamber
US6203582B1 (en) * 1996-07-15 2001-03-20 Semitool, Inc. Modular semiconductor workpiece processing tool
US6235453B1 (en) * 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
US6238161B1 (en) * 1997-09-05 2001-05-29 Applied Materials, Inc. Cost effective modular-linear wafer processing
US20010010950A1 (en) * 1999-04-02 2001-08-02 Silicon Valley Group Thermal Systems Llc Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
US6281135B1 (en) * 1999-08-05 2001-08-28 Axcelis Technologies, Inc. Oxygen free plasma stripping process
US6303524B1 (en) * 2001-02-20 2001-10-16 Mattson Thermal Products Inc. High temperature short time curing of low dielectric constant materials using rapid thermal processing techniques
US20010037822A1 (en) * 1998-10-09 2001-11-08 Tamer Elsawy Vapor drying system and method
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US20010048867A1 (en) * 2000-03-29 2001-12-06 Lebar Technology, Inc. Method and apparatus for processing semiconductor wafers
US20010051082A1 (en) * 1997-09-05 2001-12-13 Kirkpatrick Thomas I. Cost effective modular-linear wafer processing
US20020037655A1 (en) * 2000-09-27 2002-03-28 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device having low dielectric constant insulating film, wafer processing equipment and wafer storing box used in this method
US6452275B1 (en) * 1999-06-09 2002-09-17 Alliedsignal Inc. Fabrication of integrated circuits with borderless vias
US6495825B1 (en) * 1999-12-22 2002-12-17 International Business Machines Corporation Apparatus for photo exposure of materials with subsequent capturing of volatiles for analysis
US20030003243A1 (en) * 1998-03-27 2003-01-02 Tomo Ueno Method for forming film
US20060065624A1 (en) * 2001-09-20 2006-03-30 Michinobu Mizumura Etching method of organic insulating film

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2032763C (fr) * 1990-12-20 2001-08-21 Mitel Corporation Prevention de la contamination du circuit de transit par desorption induite obtenue par decharge luminescente
KR100219562B1 (ko) * 1996-10-28 1999-09-01 윤종용 반도체장치의 다층 배선 형성방법
US5866945A (en) * 1997-10-16 1999-02-02 Advanced Micro Devices Borderless vias with HSQ gap filled patterned metal layers
US6720247B2 (en) * 2000-12-14 2004-04-13 Texas Instruments Incorporated Pre-pattern surface modification for low-k dielectrics using A H2 plasma
US6503840B2 (en) * 2001-05-02 2003-01-07 Lsi Logic Corporation Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4341592A (en) * 1975-08-04 1982-07-27 Texas Instruments Incorporated Method for removing photoresist layer from substrate by ozone treatment
US4885047A (en) * 1986-08-11 1989-12-05 Fusion Systems Corporation Apparatus for photoresist stripping
US5151296A (en) * 1989-03-31 1992-09-29 Canon Kk Method for forming polycrystalline film by chemical vapor deposition process
US5322590A (en) * 1991-03-24 1994-06-21 Tokyo Electron Limited Plasma-process system with improved end-point detecting scheme
US5498308A (en) * 1994-02-25 1996-03-12 Fusion Systems Corp. Plasma asher with microwave trap
US5705232A (en) * 1994-09-20 1998-01-06 Texas Instruments Incorporated In-situ coat, bake and cure of dielectric material processing system for semiconductor manufacturing
US20010030101A1 (en) * 1996-07-15 2001-10-18 Berner Robert W. Modular semiconductor workpiece processing tool
US6203582B1 (en) * 1996-07-15 2001-03-20 Semitool, Inc. Modular semiconductor workpiece processing tool
US6238161B1 (en) * 1997-09-05 2001-05-29 Applied Materials, Inc. Cost effective modular-linear wafer processing
US20010051082A1 (en) * 1997-09-05 2001-12-13 Kirkpatrick Thomas I. Cost effective modular-linear wafer processing
US20030003243A1 (en) * 1998-03-27 2003-01-02 Tomo Ueno Method for forming film
US6021672A (en) * 1998-09-18 2000-02-08 Windbond Electronics Corp. Simultaneous in-situ optical sensing of pressure and etch rate in plasma etch chamber
US6328809B1 (en) * 1998-10-09 2001-12-11 Scp Global Technologies, Inc. Vapor drying system and method
US20010037822A1 (en) * 1998-10-09 2001-11-08 Tamer Elsawy Vapor drying system and method
US20020033136A1 (en) * 1999-04-02 2002-03-21 Silicon Valley Group, Thermal Systems Llc. Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
US20010010950A1 (en) * 1999-04-02 2001-08-02 Silicon Valley Group Thermal Systems Llc Semiconductor wafer processing system with vertically-stacked process chambers and single-axis dual-wafer transfer system
US6452275B1 (en) * 1999-06-09 2002-09-17 Alliedsignal Inc. Fabrication of integrated circuits with borderless vias
US6559045B2 (en) * 1999-06-09 2003-05-06 Alliedsignal Inc. Fabrication of integrated circuits with borderless vias
US6235453B1 (en) * 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
US6281135B1 (en) * 1999-08-05 2001-08-28 Axcelis Technologies, Inc. Oxygen free plasma stripping process
US6495825B1 (en) * 1999-12-22 2002-12-17 International Business Machines Corporation Apparatus for photo exposure of materials with subsequent capturing of volatiles for analysis
US20010048867A1 (en) * 2000-03-29 2001-12-06 Lebar Technology, Inc. Method and apparatus for processing semiconductor wafers
US6319809B1 (en) * 2000-07-12 2001-11-20 Taiwan Semiconductor Manfacturing Company Method to reduce via poison in low-k Cu dual damascene by UV-treatment
US20020037655A1 (en) * 2000-09-27 2002-03-28 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device having low dielectric constant insulating film, wafer processing equipment and wafer storing box used in this method
US6303524B1 (en) * 2001-02-20 2001-10-16 Mattson Thermal Products Inc. High temperature short time curing of low dielectric constant materials using rapid thermal processing techniques
US20060065624A1 (en) * 2001-09-20 2006-03-30 Michinobu Mizumura Etching method of organic insulating film

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256139B2 (en) 2002-05-08 2007-08-14 Applied Materials, Inc. Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices
US20050153073A1 (en) * 2002-05-08 2005-07-14 Applied Materials, Inc. Method for forming ultra low k films using electron beam
US20050130404A1 (en) * 2002-05-08 2005-06-16 Applied Materials, Inc. Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices
US7422774B2 (en) 2002-05-08 2008-09-09 Applied Materials, Inc. Method for forming ultra low k films using electron beam
US20070275569A1 (en) * 2002-05-08 2007-11-29 Farhad Moghadam Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices
US7563728B2 (en) 2003-03-07 2009-07-21 Applied Materials, Inc. Methods of modifying interlayer adhesion
US8569166B2 (en) 2003-03-07 2013-10-29 Applied Materials, Inc. Methods of modifying interlayer adhesion
US7960294B2 (en) 2003-03-07 2011-06-14 Applied Materials, Inc. Method of modifying interlayer adhesion
US20070141855A1 (en) * 2003-03-07 2007-06-21 Applied Materials, Inc. Methods of modifying interlayer adhesion
US7910897B2 (en) 2004-05-06 2011-03-22 Applied Materials, Inc. Process and apparatus for post deposition treatment of low dielectric materials
US7663121B2 (en) 2005-05-09 2010-02-16 Applied Materials, Inc. High efficiency UV curing system
US20060251827A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. Tandem uv chamber for curing dielectric materials
US20060249078A1 (en) * 2005-05-09 2006-11-09 Thomas Nowak High efficiency uv curing system
US20090162259A1 (en) * 2005-05-09 2009-06-25 Thomas Nowak High efficiency uv curing system
US20060249175A1 (en) * 2005-05-09 2006-11-09 Applied Materials, Inc. High efficiency UV curing system
US7501355B2 (en) 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
US20090137132A1 (en) * 2006-06-29 2009-05-28 Ritwik Bhatia Decreasing the etch rate of silicon nitride by carbon addition
US7951730B2 (en) 2006-06-29 2011-05-31 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
US20080014761A1 (en) * 2006-06-29 2008-01-17 Ritwik Bhatia Decreasing the etch rate of silicon nitride by carbon addition
US20100022100A1 (en) * 2006-09-20 2010-01-28 Applied Materials, Inc. Bi-layer capping of low-k dielectric films
US7598183B2 (en) 2006-09-20 2009-10-06 Applied Materials, Inc. Bi-layer capping of low-K dielectric films
US20080070421A1 (en) * 2006-09-20 2008-03-20 Ping Xu Bi-layer capping of low-k dielectric films
WO2019209543A1 (fr) * 2018-04-24 2019-10-31 Cree, Inc. Circuits électroniques conditionnés ayant une encapsulation de protection contre l'humidité et leurs procédés de formation
US10811370B2 (en) 2018-04-24 2020-10-20 Cree, Inc. Packaged electronic circuits having moisture protection encapsulation and methods of forming same
CN112106188A (zh) * 2018-04-24 2020-12-18 克里公司 具有防潮包封的封装电子电路及其形成方法
KR20200142030A (ko) * 2018-04-24 2020-12-21 크리, 인코포레이티드 수분 보호 캡슐화를 갖는 패키징된 전자 회로 및 그 형성 방법
KR102440804B1 (ko) 2018-04-24 2022-09-07 울프스피드, 인크. 수분 보호 캡슐화를 갖는 패키징된 전자 회로 및 그 형성 방법
US11682634B2 (en) 2018-04-24 2023-06-20 Wolfspeed, Inc. Packaged electronic circuits having moisture protection encapsulation and methods of forming same

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