WO1997050111A1 - Semiconducteur chip and reticle for manufacturing semiconductor - Google Patents

Abstract

An alignment marker used for another use, such as in a stepper, has been conventionally used for finding the position, specified by CAD data, of a final functional defect of a semiconductor chip detected by fail bit inspections. However, this alignment marker does not coincide exactly with a design coordinate system which is established on the basis of a virtually existing scribe center and, when the semiconductor chip is positioned by using the marker, an error of tens of micrometers occurs. Therefore, at the time of observing a defect at a point designated by design coordinate values, a considerable amount of man-hour has been required, because the designated point of the defect to be observed is deviated from the actual position by about several to ten cells and the vicinity of the point must be visually searched for the defect. According to this invention, patterns such that the position on each coordinate axis of the design coordinate axis is encoded so that the position in the chip formed on a semiconductor wafer can be recognized from design coordinate values are provided in horizontal and vertical specific areas of the uppermost layer at the time of visual observation or of a layer which is detectable at the time of observation by utilizing the peripheral region of the chip. The patterns are inputted into a computer at the time of observation, positional information on each coordinate axis is read out by decoding the encoded pattern, and the chip is positioned.

Description

 Specification

Technical field of semiconductor chips and semiconductor manufacturing reticles

 The present invention relates to a semiconductor chip and a reticle for manufacturing a semiconductor, and more particularly to a reticle for manufacturing a semiconductor chip and a semiconductor chip whose design coordinate position can be easily specified by a pattern provided on the semiconductor chip.

 Conventionally, the location of the final functional defect of a semiconductor chip detected by fail bit inspection is specified by CAD data, and when visually checking the cause of the defect for observation and analysis, the semiconductor chip to be observed is Alternatively, load the semiconductor wafer on which the semiconductor chip is built into a stage equipped with a microscope, such as a review station, and locate it at the location specified by the CAD data. To this end, alignment techniques used for other applications such as steppers were used.

However, the alignment force used for other uses such as steppers does not exactly match the design coordinate system based on the virtually existing scribe center, and this alignment marker is used. When it is positioned by positioning it, it will be out of order of tens of micrometers. For this reason, when observing a defect indicated by design coordinate values using a review station or the like described in the prior art, even if the stage is moved to the indicated coordinate values, several to ten cells are required from the target location. It is located some distance away, and it takes a lot of man-hours to look around the area visually. Correspondence with design coordinate system on actual chip It is necessary to reduce the man-hours required for the observation by taking measures to make the observation possible. Disclosure of the invention

 The problem described above is to utilize the peripheral area of the chip formed on the semiconductor wafer, and to set the position in the chip to the uppermost layer part during visual observation or to the layer that can be detected at the time of observation by design coordinates in this area. As can be seen, a pattern obtained by encoding the position on each coordinate axis of the design coordinate system is provided in a specific area in the outer peripheral part on the chip in a horizontal and vertical direction, so that the pattern is read by a computer at the time of observation and encoded. This is achieved by reading the position information on each coordinate axis by decoding from and positioning the chip. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a plan view showing an arrangement of semiconductor chips on a semiconductor wafer, and FIG. 2 is a view showing a variation of an XY coordinate system on the semiconductor chip.

 FIG. 3 is a plan view showing a schematic configuration of a semiconductor chip. FIG. 4 is an enlarged plan view showing a part of the corner of the gardening portion when the present invention selects the gardening portion of the semiconductor chip as a predetermined region. FIGS. 5 and 6 are plan views showing a method of encoding a pattern in a girder drilling part when a girder part of a semiconductor chip is selected as a predetermined region according to the present invention. The figure is a diagram for explaining a correspondence table between an encoding pattern and a decoded value according to the present invention.

 FIG. 8 is a plan view showing a method of coding a pattern in the guarding portion when the present invention selects a guarding portion of a semiconductor chip as a predetermined region.

FIG. 9 shows that the present invention is applied to a semiconductor chip gardening as a predetermined region. FIG. 6 is an enlarged plan view showing a corner portion of the semiconductor chip when the outside of the portion is selected.

 FIG. 10 is a plan view showing a method of encoding a pattern in a scribe area when the present invention selects a scribe area as a predetermined area. FIG. 11 and FIG. FIG. 7 is a plan view showing another example of a method of encoding a pattern in a scribe area.

 FIG. 13 is an enlarged plan view showing a part of a corner of a semiconductor chip when the present invention is selected between a bonding portion and a circuit pattern forming region region as a predetermined region. is there. BEST MODE FOR CARRYING OUT THE INVENTION

 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an enlarged view of one of the semiconductor chips built on a semiconductor substrate.

 The rectangular area around the diagonal line shown by 1 is one semiconductor chip, and the diagonal area around 8 is the semiconductor chip built on the semiconductor wafer adjacent to the 1 semiconductor chip. Is shown. The dashed-dotted line indicated by 2 is called a scribe center, and serves as a guideline when dicing the semiconductor chip 1 and surrounding chips to separate them and finally cut them into individual semiconductor chips.

 In Fig. 1, two vertically running scribe centers and two horizontally running scribe centers are indicated by alternate long and short dash lines. The position in the semiconductor chip 1 shown at the center is defined by the XY coordinate system defined by the X and Y coordinates shown in FIG. , 4, 5, and 6 are rectangular areas.

The origin indicated by 3 is called the design origin. For example, semiconductor chip 1 The design origin of the upper adjacent semiconductor chip is 4, and the same coordinate system and area are defined recursively. Depending on the design data, the design origin may be 4, 5, or 6, instead of 3. Also, as shown in FIG. 2, there are eight possible ways to define the XY coordinate system, including the method shown in FIG. Hereinafter, the description will be made using the design origin position shown in FIG. 1 and the design coordinate system defined by the XY coordinate system.

 Design data such as all wiring patterns and circuit positions in the semiconductor chip is described by XY coordinate values with the origin 3 as the origin shown in FIG. FIG. 3 is an enlarged view of the semiconductor chip 1 shown in FIG. Reference numeral 7 denotes a region sandwiched between the rectangular regions 3, 4, 5, and 6 and the semiconductor chip 1, and is called a scribe region. Reference numeral 8 denotes a region provided on the outer peripheral portion of the semiconductor chip 1 and is called a bonding portion.

 The guard ring is provided to prevent moisture and sodium from entering the chip from the side, and is made of aluminum or silicon oxide with a width of about tens of microphones. Is formed by the material used in the above. Reference numeral 10 denotes a circuit pattern forming area of the chip body in which a wiring circuit pattern that actually functions is formed. Reference numeral 9 denotes an area between the normal gardening portion 8 and the circuit pattern formation area 10, which is usually a blank area of 100 to 200 microphones D-torl. The area for forming a pattern that encodes the position on each coordinate axis of the design coordinate system so that the position in the circuit pattern formation area 10 can be identified by the design coordinate value includes the scribe area 7, the guard-ring section 8, and the blank area. 9 It may be used.

First, a case where the gardening unit 8 is used as a first embodiment will be described. FIG. 4 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by the X and Y axes defined by the design coordinate origin 3 and the scribe center. 8 is a girdering part, 10 is a circuit pattern formation area. A rectangular wave pattern is cut around the outer periphery of the guiding portion 8 shown in FIG. The coordinate value on the X axis or the coordinate value on the Y axis is encoded using the cut position of the rectangular wave in the directions corresponding to the X axis and the Y axis, the size of the rectangular wave, and the distance between the rectangular waves.

 FIG. 5 shows a first specific example of encoding using a gardening unit. The interval U represents one unit of the encoded pattern. Section D is a delimiter that indicates a break in the pattern unit. Section B is a bit pattern. If there is a rectangular cut pattern as shown in part of section B, the value is set to binary code 1; otherwise, it is set to 0.

 In FIG. 5, the cut width of the rectangle is set to one half of the bit area section B. This width may be an arbitrary fixed distance. The delimiter and the bit pattern are distinguished by the difference of each pattern width s1 and S2. In Figure 5

Although expressed as S1: S2 = 2: 1, this ratio is arbitrary as long as it is the same between each pattern unit.

 In FIG. 5, the code coded by the pattern unit is read as follows. First, a delimiter of pattern width S1 is detected, and the bit pattern following it is read. In FIG. 5, the width is written in 9 bits, but this bit width may be changed as necessary.

 The bit pattern in FIG. 5 is 101 1 110 1, which represents a decimal number of 370. In the 9-bit pattern, 0 to 5 1 1 can be represented. Therefore, as shown in FIG. 5, when considered in the X direction, the size XS in the X direction of the circuit pattern formation area 10 shown in FIG. Is defined as X unit, and the starting position of the pattern unit is determined in advance as X start as shown in Fig. 4, so that the pattern unit shown in Fig. 5 Start position X n

X n = X start + X unitx 3 7 O (101110010: binary Expression)

Can be determined.

 Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the gardening section 8 for the Y axis, the encoded pattern in the X and Y directions of the gardening section 8 is formed. Thus, the positions of X and Y are determined, and the position indicated by any design coordinates in the circuit pattern formation region 10 can be determined.

 As described above, when it is desired to define the position of Xn finely, the distance of the pattern unit section U may be shortened and the bit width may be increased. The same applies to the Y direction.

 FIG. 6 shows a second embodiment using a girder ring. Section U represents one unit of the encoded pattern. The section D is a delimiter indicating a break between the patterns Pl, P2, and P3 encoded by the length.

 The pattern lengths indicated by Pl, P2, and P3 are quantized in 10 steps. That is, if the minimum unit distance is d, the pattern length P n is

 P n = d X n (n = l, 2, "ヽ 1 0)

Take the length of 10 steps. Therefore, the number of combinations of Pl, P2, and P3, which is the third power of 10th, that is, 10000 combinations is possible. Therefore, by measuring the first three pattern lengths P1, P2, and P3 from one delimiter, the position of the delimiter can be specified.

However, in order to realize this, the combination of the following three pattern lengths starting from any delimiter must be unique, that is, it corresponds to one axis direction of X or Y in one chip. The condition is that there is no overlap in the combination of three consecutive pattern lengths, which are in the drawing 8. This is hereinafter referred to as a non-duplication condition. In determining the pattern length, the following must be considered. First, the pattern length must be determined cyclically. That is, if P1, P2, and P3 are determined, the first two of the next pattern are P2 and P3, and P2, P3 It is necessary to determine the next pattern P4 following. Second, the distance U including the three pattern lengths needs to be averaged as a whole. This means that one part is (PI, P2, P3) = (d, d, d) and another part is (pl, p2, p3) = (10d, 10d, 10d). This is because the distribution of the delimiters for determining the coordinate position greatly varies, which causes practical inconvenience.

 The combination of P1, P2, and P3 determined under the above conditions complicates the correspondence with the actual coordinates, and as shown in Fig. 7, the combination of P1, P2, and P3 The combination is used as an index, and table data is stored in advance so that the coordinate value X can be obtained.

 Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the gardening section 8 with respect to the Y-axis, the encoding of the gardening section 8 in the X and Y directions is performed. The positions of X and Y are determined from the obtained pattern, and the position indicated by arbitrary design coordinates in the chip 10 can be determined. As described above, when it is desired to define the position of Xn more finely, it is only necessary to shorten the distance of the butterfly unit section U and increase the bit width. The same applies to the Y direction. In the above description, the pattern combination is 3 and the pattern length is 10 steps. However, the number of combinations of patterns and the number of steps of the pattern length may be different values.

FIG. 8 shows a third embodiment using a guiding part. This method is a modification of the first embodiment using the gardening unit shown in FIG. 5, and a section U represents one unit of the encoded pattern. Section D is a pattern This is a delineation showing the end of the unit. Section B is a bit pattern. If there is a rectangular cut pattern as shown in part of section B, it is set to binary code 1; otherwise, it is set to 0.

 In FIG. 8, the cut width of the rectangle is set to one half of the bit area section B, but this width may be an arbitrary constant distance. The delimiter and the 'bit pattern are identified by the difference between the pattern widths S1 and S2. In FIG. 8, the ratio is expressed as S 1: S 2 = 2: 1, but this ratio is arbitrary as long as it is the same between each pattern unit.

 The first embodiment using the guarding part is that one bit has a depth d. d is quantized in six steps. That is, assuming that the minimum unit distance is w, the path length P n is

 d = w X n (n = 0, 1, 2, "ヽ 5)

 Take the length of 6 steps. This makes it possible to represent a hexadecimal number with one bit, and the value of 6 to the fourth power, that is, a value from 0 to 1 295, is set to the first unit length using the gardening unit. It can be expressed by about half as compared with the embodiment. The correspondence with the coordinate values is the same as in the first embodiment.

 In the above, three embodiments using the guarding section have been described. As another encoding method, the bit pattern encoding method such as NRZ-I, MFM, and MDM used in magnetic recording devices and the like is used. Etc. can also be applied. Further, the pattern provided to the girdering portion may be outside or inside the girdering. Further, although the pattern to be formed is described as a rectangle, any other shape may be used as long as it can be detected, for example, a sawtooth shape, a triangle, a semicircle, or the like.

Next, a case where the scribe area 7 is used as a second embodiment will be described. FIG. 9 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by the design coordinate origin 3 and the X and Y axes defined by the scribe center. 8 is Gardrin And 10, a circuit pattern forming area.

 The oblique hatched rectangular area 11 shown in FIG. 9 is a pattern formed for the same purpose as the pattern formed on the edge of the gardening portion in the above-described embodiment using the gardening portion. The coordinate value on the X axis or the coordinate value on the Y axis is encoded using the position of the rectangular pattern in the direction corresponding to the X axis and the Y axis, the size of the rectangular pattern, and the distance between the rectangular patterns.

 FIG. 10 shows a first specific example of encoding using a scribe area. Section U represents one unit of the encoded pattern. Section D is a delimiter that indicates a break in the unit in the palace. Section B is a bit pattern. If there is a sheep-shaped notch pattern as shown in part of section B, set it to binary code 1; otherwise, set it to 0. In FIG. 10, the width of the rectangular pattern is set to one half of the bit area section B, but the width may be any constant distance.

 The delimiter and bit pattern are identified by the difference between each pattern width S 1 and S 2. In FIG. 10, S 1: S 2 = 2: 1 is shown, but this ratio is arbitrary as long as it is the same between each pattern unit.

 In FIG. 10, the code coded by the pattern unit is read as follows. First, a delimiter with a pattern width of S1 is detected, and the subsequent bit pattern is read. In Fig. 10, it is written in 9-bit width, but this bit width may be changed as needed. The bit pattern in FIG. 10 is 101 1 110 0 10 and represents a decimal number of 3700.

In the 9-bit pattern, 0 to 5 1 1 can be represented.Thus, considering in the X direction as shown in Fig. 10, the X direction size XS of chip 10 shown in Fig. 3 is 5 12 or less. If the appropriate divided distance is defined as X unit and the starting position of the pattern unit is determined in advance as X start as shown in Fig. 9, the starting position of the pattern unit shown in Fig. 10 X n

 X n = X st a r t + X u n i t x 3 7 O (101110010: binary representation)

Can be determined.

 Similarly, if a pattern in which the coordinate position on the Y-axis coordinate is encoded is formed in the scribe area 7 for the Y axis, the X and Y encoded patterns in the X and Y directions of the scribe area 7 can be obtained. Is determined, and a position indicated by arbitrary design coordinates in the circuit pattern formation region 10 can be determined.

 As described above, when it is desired to define the position of Xn more finely, it is only necessary to shorten the distance of the pattern unit section U and increase the bit width. The same applies to the Y direction.

 A second embodiment using a scribe area is shown in FIG. Section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break between patterns P1, P2, and P3 encoded by the length. The pattern lengths indicated by Pl, P2, and P3 are quantized in 10 steps. That is, if the minimum unit distance is d, the pattern length P n is

 P n = d X n (n = l, 2,-, 1 0)

Take the length of 10 steps. Therefore, the number of combinations of Pl, P2, and P3, which is the third power of 10th, that is, 10000 combinations is possible.

Therefore, the position of the delimiter can be specified by measuring the first three pattern lengths P1, P2, and P3 from one delimiter. However, in order to achieve this, the combination of the following three pattern lengths starting from an arbitrary delimiter must be unique, that is, a scribe area corresponding to one X or Y axis direction in one chip. The condition is that there is no overlap in the combination of three consecutive pattern lengths. This is hereinafter referred to as a non-overlapping condition.

 In determining the pattern length, the following must be considered. First, the pattern length must be determined cyclically. That is, if P 1, P 2, and P 3 are determined, the first two of the following patterns are P 2 and P 3, and under these conditions, P 2 It is necessary to determine the next pattern P4 following P3.

 Second, the distance U including the three pattern lengths needs to be averaged as a whole. This means that if one part is (Pl, P2, P3) = (d, d, d) and another part is (Pl, p2, p3) = (10d, 10d, 10d), the coordinate position is determined. This is because the distribution of the delimiters for the above-mentioned purpose greatly varies, which causes practical inconvenience.

 The combination of P 1, P 2, and P 3 determined under the above conditions complicates the correspondence with the actual coordinate values. Therefore, as shown in FIG. 7, P 1, P 2, and P 3 The combination is used as an index, and table data is stored in advance so that the coordinate value X can be obtained.

 Similarly, if a pattern in which the coordinate positions on the Y-axis coordinates are encoded is formed in the scribe area 7 for the Y axis, the scribe area 7 can be encoded in the X and Y directions. The positions of X and Y are determined from the obtained pattern, and the position indicated by arbitrary design coordinates in the circuit pattern formation region 10 can be determined.

 As described above, when it is desired to define the position of X n more finely, it is only necessary to shorten the distance of the pattern unit unit U and increase the bit width. The same applies to the Y direction.

In the above description, the combination of patterns is 3 and the length of the pattern is 10 levels. However, the number of pattern combinations and the number of levels of the pattern length may be different values. FIG. 8 shows a third embodiment using a scribe area. This method is a modification of the first embodiment using the scribe area shown in FIG. 10, and a section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break in the unit of the pattern. Section B is a bit pattern. If a rectangular cut pattern as shown in the figure exists in a part of section B, the binary code is set to 1. Otherwise, it is set to 0.

 In FIG. 12, the cut width of the rectangle is set to one half of the bit area section B, but this width may be an arbitrary constant distance. The delimiter and the bit pattern are identified by the difference between the pattern widths S 1 and S 2. In FIG. 12, S1: S2 = 2: 1 is shown, but this ratio is arbitrary as long as it is the same between each pattern unit.

 The first embodiment using the gardening part is that one bit has a depth d. d is quantized in six stages. That is, if the minimum unit distance is w, the pattern length P n is

 d = w X n (n = 0, l, 2, "-, 5)

Take the length of 6 steps. This makes it possible to represent a hexadecimal number with one bit. The value of 6 to the fourth power, that is, a value from 0 to 1295, and the length of one unit can be expressed by the first It can be expressed in about half as compared with the embodiment. The correspondence with the coordinate values is the same as in the first embodiment using the scribe area.

 The three embodiments using the scribe area have been described above. Other coding methods include bit pattern coding methods such as NRZ-I, MFM, and M used in magnetic recording devices and the like. Etc. are also applicable. Further, the pattern to be formed has been described as a rectangle, but any other shape, such as a sawtooth shape, a triangle, or a semicircle, may be used as long as it can be detected.

Next, as a third embodiment, the galling portion 8 and the circuit pattern formation area The case where the blank area 9 between the areas 10 is used will be described. FIG. 13 is a further enlarged view of the lower left corner of the semiconductor chip shown in FIG. The design coordinate system is represented by the design coordinate origin 3 and the X and Y axes defined by the scribe center. Reference numeral 8 denotes a guard portion, 10 denotes a circuit pattern forming region, and 9 denotes a blank region between the guard portion 8 and the circuit pattern forming region.

A hatched rectangular area 12 shown in FIG. 13 corresponds to _c X-axis and Y-axis, which are patterns formed for the same purpose as the pattern described in the above embodiment using the scribe area. Using the position of the rectangular pattern in the direction, the size of the rectangular pattern, and the distance between the rectangular patterns, the coordinate value on the X axis or the coordinate value on the Y axis is encoded.

 The same pattern as the pattern disclosed in the scribe area 7 can be applied to the encoded pattern in the embodiment using the 9 blank areas. X start in FIG. 13 corresponds to X start in the first embodiment using the scribe area disclosed in the scribe area 7. As described above, the case where the pattern in which the position information is encoded is formed in the corner portion, the case where the pattern is formed in the scribe region, and the case where the pattern is formed between the scribe region and the chip have been described. The encoded pattern only needs to be formed on the uppermost layer or a layer that can be observed by a method using an optical or an electron beam and a method using an ultrasonic wave during visual observation. .

As described above, the pattern in which the position information formed on the semiconductor chip is encoded has been described. In order to form this pattern at the above-described predetermined position of each chip on the wafer, a step in the exposure process is required. The reticle used must also be formed in a corresponding position. 上 の Business availability

 As described above, according to the present invention, a pattern that encodes the position on each coordinate axis of the design coordinate system is provided on the chip so that the position in the chip can be identified by the design coordinate value. Observing the pattern, extracting the pattern by image processing, decoding the coded pattern information, and reading out the position information on each coordinate axis to obtain the chip position accurately Becomes possible.

 This allows the specimen to be connected to CAD in cases such as fail-bit inspection, where the defect location is specified by design data and the defect cause is visually checked to observe and analyze the cause. By setting the sample on the stage and positioning the sample using CAD data, the defect position to be observed and analyzed can be easily and accurately located, reducing the number of man-hours for observation. It becomes possible.

 In addition, by applying the semiconductor chip to which the present invention is applied to the production process of a semiconductor device, it becomes possible to observe a defect position that causes a final functional defect of the semiconductor chip in a short time, thereby making it possible to process the semiconductor chip in a short time. It is expected that the feedback for improvement will be faster.

Claims

The scope of the claims 1. A semiconductor chip, wherein an encoded pattern corresponding to data on a design coordinate system at the desired position is formed at a desired position in a predetermined area of the semiconductor chip.  2. The semiconductor chip according to claim 1, wherein the encoding is performed by changing an interval between patterns of the same shape formed in a predetermined region of the semiconductor chip.  3. The semiconductor chip according to claim 1, wherein the encoding is performed by combining shapes of a pattern formed in a predetermined region of the semiconductor chip.  4. The semiconductor according to any one of claims 1 to 3, wherein the predetermined region on the semiconductor chip is a gardening portion of each chip formed on the semiconductor wafer. Chips. 5. The predetermined area on the chip is a scribe area of each chip formed on a semiconductor wafer, and the predetermined area on the chip is a scribe area of each chip. Semiconductor chip.  6. The predetermined region on the chip is a region between a guard ring portion of each chip formed on a semiconductor wafer and a circuit pattern formation region. 4. The semiconductor chip according to any one of items 1 to 3. 7. A reticle for manufacturing a semiconductor device, wherein an encoded pattern corresponding to data on a design coordinate system at the desired position is formed at a desired position in a predetermined area where a circuit pattern is formed. 8. The semiconductor device according to claim 7, wherein the encoding is performed by changing an interval between patterns of the same shape formed in a predetermined area where the circuit pattern is formed. Manufacturing reticle. 9. The reticle for manufacturing a semiconductor device according to claim 7, wherein the encoding is performed by combining shapes of a pattern formed in a predetermined area in which the circuit pattern is formed.  10. The claim 7, wherein the predetermined area in which the circuit pattern is formed is an area corresponding to a galling portion of each chip formed on the semiconductor wafer. 10. The reticle for manufacturing a semiconductor device according to claim 9.  11. The method according to claim 7, wherein the predetermined region in which the circuit pattern is formed is a region corresponding to a scribe region of each chip formed on the semiconductor substrate. 10. The reticle for manufacturing a semiconductor device according to claim 9.  12. The predetermined region in which the circuit pattern is formed is a region corresponding to a region between a guard portion and a circuit pattern formation region of each chip formed on the semiconductor wafer. A reticle for manufacturing a semiconductor device according to any one of claims 7 to 9.